Is this your business? Claim it to manage your IP and profile
Soft Mixed Signal's PCI-Express PHY IP is a versatile and power-efficient solution designed to meet the standards of the PCI-Express Base Specification Revision 1.0a. This transceiver core is particularly optimized for high-performance and scalable applications, making it ideal for use in enterprise-level networking solutions and other demanding scenarios. It is compliant with the Physical Interface (PHY) for PCI-Express (PIPE) standards, ensuring broad interoperability and reliable performance. The PCI-Express PHY core achieves high efficiency through a proprietary multi-lane methodology that leverages silicon area vitality, reducing die size the smallest in its class. Such compactness is paired with a unique clock recovery architecture, providing resilience in environments often troubled by electronic noise. The integration of both PMA and PCS layers reflects its robustness, accommodating direct connections to various MAC layers via configurable PIPE interfaces. Targeting both 180nm and 130nm process nodes initially, this IP offers designers a flexible path towards implementing PCI-Express architecture in their products. The core allows for the incorporation of auxiliary power options, enhancing its applicability in power-conscious systems like multi-port controllers. Together with support for electrical idle detection and embedded error testing, this PHY core ensures data integrity and system reliability across a multitude of applications.
The USB 2.0 PHY Core from Soft Mixed Signal is engineered to meet the modern demands of USB connectivity by offering full compliance with the latest USB 2.0 specifications. This core delivers a complete transceiver solution with support for high-speed modes while incorporating On-The-Go (OTG) capabilities, which allows devices to operate independently in a manner of host or peripheral, enhancing interaction versatility. Important design features include clock recovery from high data rates of 480 Mbps, operated through a high-frequency PLL. Advanced transmitter and receiver capabilities support both high-speed and full-speed modes, maintaining robust signal integrity under various operational conditions. The implementation of UTMI and/or UTMI+ interfaces allows for efficient data transfer across differing bus widths, accommodating both 8-bit and 16-bit architectures. For added functionality, the solution is equipped with calibrated switchable resistors for differential signaling, alongside optional charge pumps and VBus functionalities for OTG applications. This enhances flexibility in supporting diverse hardware platforms such as PC peripherals, mobile devices, and more, thus reducing integration time and risk for system developers striving to meet stringent market requirements.
The fully integrated Gigabit Ethernet and Fibre Channel Transceiver Core by Soft Mixed Signal Corporation is designed to deliver high-performance connectivity for gigabit Ethernet applications. It utilizes advanced very high-speed serial link solutions that are crucial for efficient data transmission in fiber-based networks. This includes a suite of essential blocks such as high-speed drivers, sophisticated PLL architecture, and serializer/deserializer (SERDES) functionalities. The design ensures low jitter and precise comma detection for optimal data alignment, making it a robust choice for gigabit applications. Notably, the transceiver core supports IEEE 802.3z standards, offering a 1.25 Gigabit/s data rate. The PHY also features a 10-bit interface for seamless data transmission and reception, complementing its inherently full-duplex operation. Critical design elements such as programmable transmit equalization and PECL clock options are integrated, minimizing transmit jitter and distortion. Furthermore, the system's proprietary phase detector technology ensures superior receive jitter performance, enhancing signal reliability even in challenging conditions. This solution is crafted to be budget-friendly while maintaining low power consumption, owing to its full CMOS implementation. It is compatible with both 75 and 50-ohm terminations, providing flexibility for various deployment scenarios. The inclusion of embedded bit error rate testing further streamlines the evaluation of system performance, ensuring that the design meets rigorous standards for telecommunication applications.
Soft Mixed Signal's OC-3/12 Transceiver Core represents a significant advancement in SONET/SDH networking technology. Designed using a deep sub-micron single poly CMOS process, this transceiver core addresses the rigorous demands of current telecommunication standards by integrating clock synthesis and recovery with wave shaping and a low-jitter LVPECL interface. Adhering strictly to ANSI, Bellcore, and ITU jitter specifications, this core is an essential asset for any infrastructure requiring high-reliability data transmission over optical networks. The transceiver features an innovative architecture that excels in jitter performance. Proprietary signal processing techniques are employed to enhance clock recovery, providing immunity to external physical board noise—a common challenge in modern electronics. The design is aimed at multi-port applications, facilitating integration into complex system-level environments and potentially serving as a building block for future process migrations or new application domains. This scalable technology supports data rates of 622.08 Mbit/s for OC-12 and 2.4 Gbit/s for OC-48 applications, with selectable reference frequencies to accommodate various system requirements. The transceiver is also prepared for customization, offering a configurable serializer-deserializer option to better align with specific customer needs. This adaptability ensures high compatibility with various external optical units, enhancing the functional versatility of the core in diverse telecommunications solutions.
The Serial ATA (SATA) PHY IP from Soft Mixed Signal Corporation represents a robust solution for storage applications requiring high-efficiency data transfers. Designed to meet and exceed the Serial ATA specifications of Gen1 at 1.5Gbps and Gen2 at 3.0Gbps, this PHY IP core offers complete compliance with SATA 1.0a and II standards. Its versatility also extends to Serial Attached SCSI (SAS), supporting critical handshake and signaling protocols. Engineered for scalability, the SATAPhy can be adjusted to support multiple port and lane configurations, optimizing power consumption while maintaining superior performance metrics. This implementation features integrated digital processing, including the out-of-band (OOB) processor and K28.5 COMMA detection associated with SATA link management. The flexibility to scale with evolving storage needs makes this IP an excellent fit for both consumer and enterprise storage solutions. SATA technology is gaining traction as a preferable storage interface due to its streamlined design, cost-effectiveness, and reliability. As such, Soft Mixed Signal's SATA PHY IP is tailored to bring these benefits to high-demand environments, providing seamless connectivity for data-driven applications ranging from set-top boxes to advanced computing infrastructures.
Join the world's most advanced semiconductor IP marketplace!
It's free, and you'll get all the tools you need to evaluate IP, download trial versions and datasheets, and manage your evaluation workflow!
To evaluate IP you need to be logged into a buyer profile. Select a profile below, or create a new buyer profile for your company.
