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The Calibrator for AI-on-Chips epitomizes precision in maintaining high accuracy for AI System-on-Chips through advanced post-training quantization (PTQ) techniques. It offers architecture-aware quantization that sustains accuracy levels up to 99.99% even in fixed-point architectures like INT8. This ensures that AI chips deliver maximum performance while staying within defined precision margins. Central to its operation, Calibrator uses a unique precision simulator to emulate various precision-change points in a data path, incorporating control information that synchronizes with ONNC's compiler for enhanced performance. The integration with ONNC's calibration protocols allows for the seamless refinement of precision, thereby reducing precision drop significantly. Highly adaptable, the Calibrator supports multiple hardware architectures and bit-width configurations, ensuring robust interoperability with various deep learning frameworks. Its proprietary entropy calculation policies and architecture-aware algorithms ensure optimal scaling factors, culminating in a deep learning model that is both compact and precise.
Forest Runtime provides a sophisticated platform for executing compiled neural network models, supporting a variety of AI applications across multiple hardware configurations. Its unique C++ API, with bindings in C and Python, allows seamless integration into diverse systems ranging from data centers to mobile and TinyML devices. With its retargetable design, Forest Runtime ensures compatibility with various platforms, dynamically adjusting to the demands of modern neural network architectures. One defining feature of Forest Runtime is its ability to support "hot batching," a technique that enables runtime changes in model batch sizes and input shapes without invoking compilation transformations. This feature is particularly advantageous in data centers, enhancing throughput by optimizing hardware utilization and minimizing response times. Moreover, Forest Runtime scales effectively with technologies like model fusion and context switching, facilitating the management of multiple neural network models and tasks. Its use of modern linker technology to bridge tasks across accelerator cards further enhances system efficiency, ensuring comprehensive platform utilization.
The ONNC Compiler is designed to meet the growing demands of AI-on-chip development, serving as a cornerstone for transforming neural networks into machine instructions suitable for diverse processing elements. Its robust architecture supports key deep learning frameworks such as PyTorch and TensorFlow, seamlessly converting various file formats into intermediate representations using MLIR frameworks. ONNC facilitates the compilation process with advanced pre-processing capabilities powered by machine learning algorithms to convert input files optimally. The compiler is highly versatile, supporting both single-backend and multi-backend modes to cater to different IC designs. In the single-backend mode, it generates machine instructions for general-purpose CPUs like RISC-V or domain-specific accelerators like NVDLA. For complex AI SoCs, the multi-backend mode manages resources across different processing elements, ensuring robust machine instruction streams. ONNC's enhanced performance is achieved through hardware/software co-optimization, particularly in handling memory and bus allocations within heterogeneous multicore systems. By employing advanced techniques such as software pipelining and DMA allocation, ONNC maximizes resource utilization and curtails energy consumption without compromising on computational accuracy.
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