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Specializing in double data rate performance, the InfiniBand DDR Link Layer Core delivers bidirectional speeds of up to 20GBits/second. The design requires integration with a 5 GHz SerDes and is operational across a collection of FPGA platforms, including Xilinx's Virtex4FX, Virtex5, and Kintex7, as well as in ASICs. This core is tailored to meet mid-level speed grades, maximizing its application range while ensuring robust connectivity and data throughput.
Enhancing InfiniBand infrastructure, Polybus's Transport Layer Core is crucial for sophisticated data acquisition and computing solutions. It supports UC SEND and UC RDMA Write operations, accommodating up to eight virtual lanes and 1024 queue pairs. This adaptability permits seamless integration into networking scenarios, bolstered by both DDR and QDR configurations. The core's versatility ensures high-speed, low-latency operations, paving the way for advanced high-performance networking use cases.
Polybus offers an extensive set of test patterns for Xilinx FPGAs that ensures a comprehensive assessment of the FPGA functionalities and interconnects. With over 400 detailed tests, this suite not only identifies handling issues but also anticipates potential faults, enhancing the reliability of upgradable FPGA-based systems. Primarily aimed at providing thorough in-system testing, these patterns guard against failures and amplify the dependability of hardware solutions.
Polybus’s InfiniBand QDR Link Layer Core is engineered for ultimate data transfer, handling up to 80G in ASIC configurations with support for various operation modes. In FPGAs, it supports both DDR and QDR modes, tailored with a PCS layer for compatibility with Altera and Xilinx’s latest technologies. This core is quintessentially suited for high-speed environments requiring maximal throughput and low latency, integrating seamlessly into existing network topologies.
The InfiniBand SDR Link Layer Core from Polybus is designed to manage impressive data transmission rates, efficiently handling bidirectional speeds of up to 10GBits/second. It is optimized for both Xilinx and Altera FPGA applications and evidences extensive use in Xilinx Virtex and Altera Stratix platforms. The SDR core’s architecture sustains performance even in lower speed grades, contributing to its versatility and broad applicability in various high-demand environments.
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