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The InfiniBand SDR Link Layer Core is engineered to offer seamless connectivity across high-speed data networks. It operates at 125 MHz, delivering bidirectional data transfer rates of up to 10Gbits/second. This core is integrated with Xilinx Virtex2P, Virtex4FX, Virtex5, and Altera Stratix2GX FPGAs, and is available for ASIC applications as well. Constructed to perform optimally within lower-speed grade FPGAs, the core excels in maintaining data integrity in rigorous communication environments. The SDR Link Layer Core serves as the foundational element of Polybus's InfiniBand offerings, ensuring reliable data transport in computing and networking infrastructures.
The InfiniBand Transport Layer Core offers a sophisticated solution for high-performance data acquisition and networking tasks. Supporting both DDR and QDR configurations, this core facilitates UC SEND and UC RDMA Write operations, underpinning a wide range of virtual lane and queue pair configurations. With wire speed operations and remarkably low latency, the Transport Layer Core excels in applications demanding rapid data throughput and efficient packet handling. It is particularly advantageous in technologies requiring seamless integration across different data transmission standards, including PCI, Ethernet, FibreChannel, and more.
The InfiniBand DDR Link Layer Core is designed to facilitate enhanced data throughput in demanding network operations. Operating at 250 MHz, it achieves two-way data transmission rates of 20Gbits/second, set to accommodate the performance needs of mid-grade FPGAs such as the Xilinx Virtex4FX, Virtex5, and Altera Stratix2GX. The core's implementation requires sophisticated SerDes functionality, making it a suitable choice for applications where data rate and reliability are crucial. The DDR Link Layer Core expands upon the capabilities set by the SDR version, providing a powerful solution for bandwidth-intensive tasks in distributed computing systems.
The QDR version of the InfiniBand Link Layer Core stands at the forefront of high-speed data processing, functioning at 500 MHz in ASIC environments and 250 MHz in FPGA implementations. It supports both 1X and 4X QDR operations, with the capacity for 8X DDR operations in FPGAs. The inclusion of a robust PCS Layer ensures cross-compatibility with high-end FPGA systems such as Altera Stratix5GX, Xilinx Kintex7, and Virtex7. The QDR Link Layer Core is engineered to manage substantial data flows, empowering industries such as data acquisition and telecommunications to achieve optimum throughput in their operations.
The Xilinx FPGA Test Patterns offered by Polybus provide an extensive suite of over 400 testing configurations designed to verify and enhance the functionality of Xilinx FPGAs. These patterns test the internal logic and interconnect integrity, helping to identify defects arising from handling or during system upgrades. Catering to the diverse architectures of numerous Xilinx FPGA models, these patterns support rigorous in-system testing and provide a safety net against defective components reaching operational stages. Through these tests, Polybus helps ensure that only the most reliable FPGA configurations are deployed, contributing to the enhancement of system reliability and performance.
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