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The pPLL03F-GF22FDX is a specialized all-digital PLL crafted for performance computing applications. Optimized for use in GlobalFoundries' 22FDX, it delivers low-jitter clocking, suitable for complex SoCs with multiple clock domains. This PLL can handle frequencies up to 4GHz, ensuring high performance for ADC/DAC systems with moderate SNR requirements. Designed with Perceptia's second-generation PLL technology, it offers a compact footprint and minimal power draw, catering to performance computing and critical timing needs. It features fractional multiplication, offering flexible frequency selection, and supports integration into SoCs through standard views and back-end models. The pPLL03F-GF22FDX includes two separately programmable PLL outputs and is equipped with a lock-detect function to enhance system reliability. This technology ensures consistent performance across various process nodes and offers customization and migration support to meet varied technological demands.
The pPLL02F Family is engineered for general-purpose applications, delivering all-digital Fractional-N PLL capabilities. Ideal for moderate-speed digital systems and microprocessors, this family supports frequencies up to 2GHz. Its architecture ensures low-jitter performance (<18ps RMS), minimal power consumption (<3.5mW), and a compact footprint (<0.01 sq mm), making it suitable for diverse clocking demands. The second-generation digital PLL architecture offers integer and fractional multiplication, enabling an output frequency up to 400 times the input reference. It provides two additional PLL outputs through programmable post-scalers. Engineered for high testability, the pPLL02F Family includes ATPG vectors and supports industry-standard flows for seamless integration into SoC designs. This PLL is available across various foundries, including GlobalFoundries, Samsung, TSMC, and UMC. The versatile PLL is designed to deliver consistent performance across different processes, making it a robust choice for systems requiring integrated power supply regulation and multi-domain clock systems.
Specialized in RF applications, the pPLL08 Family supports advanced technologies such as 5G and WiFi. These all-digital RF frequency synthesizer PLLs are precise, delivering sub-300fs jitter performance, crucial for RF and high-speed data applications. The family is versatile, supporting frequency operations up to 8GHz through fractional-N PLL architecture, aiding in standard compliance across multiple wireless platforms. The small form factor and low power requirement make it optimal for use in loaded RF environments through easy integration. The pPLL08 Family leverages Perceptia's second-gen technological advancements, making it adaptable across different foundries and nodes. Its superior architecture guarantees minimal interference and supports challenging SNDR standards, rendering it ideal for SoC designs demanding high fidelity and speed.
Paired for low power and low voltage applications, the pPLL05 Family excels in embedding clocks for IoT and digital systems. Operating efficiently below standard core voltages, this family offers fractional-N PLL capability for systems running at frequencies up to 1GHz, revolutionizing power efficiency in design. Utilizing the second-generation all-digital PLL architecture, the pPLL05 Family sustains a compact size and maintains excellent functional performance across processes. It offers fine-grained control over input/output frequencies, facilitating ease in porting across different technologies and foundries. Aimed at enhancing integration in digital environments, the pPLL05 features high testability and offers several deliverables including detailed behavioral models and integration guides. This design guarantees consistent results and supports high precision with use across multiple nodes and foundries.
The pPOR01 empowers power management through vigilant supply monitoring, delivering a precise power-on reset (POR) solution. It's a compact, three-pin cell construct engineered to prevent system malfunctions by controlling reset signals during voltage thresholds crossing. Utilizing clever hysteresis design, pPOR01 provides stability through calibrated corner optimization that ensures logic cells operate accurately. It boasts minimal quiescent current draw, making it energy efficient while providing a robust reset signal delaying functionality via internal 35-microsecond sequencing. Integrating easily into diverse circuits, the macrocell supports CMOS outputs necessary for operating within specified threshold ranges, optimizing systems for resilience especially in challenging environments. This solution maximizes reliability through variations like migrating or customizing process-specific adaptations.
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