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The pPLL03F-GF22FDX is part of Perceptia's second-generation all-digital PLLs, tailored for high-stakes clocking needs in performance computing applications. Designed for clocking solutions with critical timing demands, this PLL provides fractional multiplication up to 4GHz with exceptionally low jitter. Its architecture allows the pPLL03F to fit in compact areas, under 0.01 sq mm, while maintaining power consumption below 5mW. Such attributes make it a prime candidate for SoCs with extensive clock domains, where each domain might be individually driven by a PLL. The design includes built-in regulation, enabling shared power supplies between the PLL and its associated blocks, simplifying integration. pPLL03F incorporates dual PLL outputs from separate postscalers, programmable up to a factor of 2,040, and offers enhanced testability through standard ATPG vectors. Its versatile application potential spans high-speed digital processing and moderate-SNR ADC/DAC setups, further enriched by Perceptia's support services for customization and migration.
The pPLL08 Family is a set of all digital fractional-N RF frequency synthesizer PLLs, specifically designed for RF applications like 5G and WiFi. These PLLs are notable for their exceptionally low jitter and compact area, enabling optimal performance in high-frequency environments up to 8GHz. Employing a second-generation digital PLL architecture, the pPLL08 family features a LC tank oscillator to achieve industry-leading phase noise performance while maintaining low power consumption below 15mW. Its design ensures minimal interference from other chip components, crucial for supporting high SNDR in RF systems. This makes it particularly suitable for use as a local oscillator or for clocking ADCs/DACs with stringent SNR requirements. Available in multiple technologies, including prominent foundries like Samsung and TSMC, the pPLL08 family boasts flexibility and integration simplicity, complete with models and views essential for backend flows. Additionally, Perceptia offers customization and technical support to adapt this PLL to various deployment scenarios, ensuring that it fits perfectly within its intended application environment.
The pPLL02F series is a versatile set of all-digital fractional-N PLLs designed for a wide range of clocking applications. These PLLs are optimized for low jitter and compact form factor, making them ideal for moderate-speed microprocessor and other digital systems. With output frequencies reaching up to 2GHz, they are capable of serving as clock generators for various logic applications. Built on Perceptia's second-generation digital PLL technology, the pPLL02F family assures consistent performance across multiple fabrication processes. Its architecture accommodates fractional and integer multiplication, enhancing flexibility in selecting input and output clock frequencies. The compact design allows seamless integration into systems with numerous clock domains, supported by an onboard power supply regulator that permits shared power lines. Engineered for straightforward integration, the pPLL02F supports multi-PLL configurations, each instance maintaining a minimal size under 0.01 sq mm and consuming less than 3.5mW. This IP block also includes all necessary deliverables, such as a detailed datasheet, integration guide, and verification reports, ensuring no complications during implementation.
The pPOR01 is a power-on reset macrocell designed to ensure reliable operation of power-sensitive circuits by providing a stable reset signal on power-up and power-down cycles. This reset circuit is essential in maintaining proper function across various supply range fluctuations. Specifically architected for use in 1.2-V cores, this macrocell optimizes its reset thresholds to ensure logical accuracy under varying conditions. The pPOR01 incorporates a standard CMOS output, with a footprint suitable for integration either within a standard pad cell or as a standalone design within other systems. The pPOR01 offers users a reliable reset function, combined with features such as a minimal quiescent current draw and standardized deliverables including integration guidelines, SPICE models, and functional test benches. Its power-on timing ensures that logic cells will operate correctly regardless of supply noise, making it a fundamental part of SoCs requiring robust power management strategies.
The pPLL05 Family encompasses a series of low power, all digital fractional-N PLLs suited for IoT and embedded systems with power constraints. These PLLs are crafted to function under low voltage conditions without compromising on jitter performance or integration ease. Built on advanced digital PLL technology, the pPLL05 series promises identical performance across various processes regardless of PVT variations. It supports clock frequencies up to 1GHz, making it appropriate as a reliable clock source for moderate-speed microprocessor blocks. The power consumption is remarkably low, less than 1.0mW, complementing its ultra-compact design that occupies less than 0.01 sq mm. This product series is designed to integrate seamlessly into any SoC layout, with deliverables covering datasheets, characterization reports, and thorough guides for both design integration and testing. The pPLL05 can serve either as an integer-N or fractional-N, providing the flexibility needed in choosing the best input-output frequency combinations for specific applications. Perceptia supports these PLLs with extensive customization and support services, ensuring they meet diverse client requirements.
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