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The Alcora V-by-One HS is a compact and efficient FMC daughter card that brings the V-by-One HS interface to any FPGA development board with high-speed transceivers. Supporting up to 16 RX and TX lanes when combining two cards, Alcora excels in transmitting high-resolution video signals, accommodating resolutions up to 4K at 120Hz or 8K at 30Hz. Alcora's design is flexible, available with either 51-pin or 41-pin headers, catering to different setup requirements. It includes two clock generators to sysnthesize reference clocks for the transceivers, ensuring reduced jitter on recovered RX clocks. The V-by-One HS technology is perfect for high-frame-rate video applications in the flat panel display sector. This versatile card is targeted at manufacturers and developers looking to implement high-speed, high-quality video interfaces within their products. Its robust design and high performance make it an excellent choice for embedding into video-centric FPGA applications, ensuring stellar performance in visually demanding environments.
Tentiva is a versatile Video FMC board designed for modular video processing applications. It stands out with its high degree of customization enabled by two dedicated PHY slots, which support an array of PHY cards for flexible connectivity. The PHY slots facilitate robust high-speed communication, with data rates reaching up to 20 Gbps, ideal for demanding video processing tasks. Modularity is at the heart of the Tentiva design, allowing users to effortlessly add or remove PHY cards as needed. This adaptability makes it suitable for a wide range of applications, whether it's for cascading multiple boards or supporting different video standards. The available PHY cards include DisplayPort transmitters and receivers as well as embedded DisplayPort solutions, covering a broad spectrum of connectivity needs. Integrated to work with FPGA development boards equipped with FMC headers, Tentiva ensures compatibility across a variety of vendor products, offering seamless integration for video processing workflows. Its design is particularly beneficial for developers seeking a scalable and adaptable solution to integrate into FPGA-based systems.
Parretto's JPEG-LS Encoder offers a high-efficiency solution for lossless image compression on FPGAs, implementing JPEG-LS standards (ISO/IEC 14495-1) for superior image quality. Notably more resource-efficient than JPEG-2000, JPEG-LS IP provides top-tier compression results without needing external memory, while maintaining latency under one line. The core supports sample depths from 8 to 16 bits, making it suitable for a wide range of imaging applications. It’s capable of handling one pixel per clock cycle, ensuring rapid processing speeds. The output data word width is configurable, fitting different application needs for image sizes ranging up to ultra-high definition. Intended for use in diverse fields requiring precise image preservation without data loss, the JPEG-LS Encoder’s low resource usage makes it an ideal choice for embedded systems where hardware efficiency is paramount. Its ease of integration using standard streaming interfaces further simplifies its inclusion in complex video workflows.
The DisplayPort 1.4 IP core by Parretto is tailored for seamless integration into advanced video applications. This compact and versatile core is designed to handle both DisplayPort source (DPTX) and sink (DPRX) functionalities, ensuring compatibility with a broad spectrum of display devices. Supporting link rates from 1.62 to 8.1 Gbps, including eDP rates, it efficiently manages video data across 1, 2, and 4 DP lanes. The core provides native video interfaces and AXI stream interfaces for smooth data transfer. Parretto's DisplayPort 1.4 IP facilitates Single Stream and Multi Stream transport modes, catering to various applications with its support for dual and quad pixels per clock. It accommodates 8 & 10-bit video depths with RGB and YUV colorspaces, ensuring vibrant color reproduction for high-quality displays. Additionally, it includes a Video Toolbox for processing tasks like test patterns and timing generation, simplifying video management. The IP is well-supported across a range of FPGA platforms, such as AMD UltraScale+, Intel Cyclone 10 GX, and Lattice CertusPro-NX. Source code is available on GitHub, offering customization flexibility and integration assurance for bespoke applications.
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