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Mobiveil’s RapidIO-AXI Bridge is a versatile and configurable IP component designed to interface between RIO and AXI systems. This bridge facilitates integration with a RapidIO controller acting as either a host or a device, using high-speed multi-channel DMA and message controllers to meet the bandwidth requisites of RapidIO frameworks. This advanced bridge solution optimizes data throughput and system communication efficiency, catering to robust data handling requirements.
Mobiveil's NVM Express Controller is an innovative hardware design aimed at maximizing the potential of PCIe-based SSDs in both enterprise and client applications. This controller supports multi-core systems, facilitating unrestricted thread and interrupt handling across various cores without lock mechanisms. Designed with efficiency in mind, it optimizes link utilization, throughput, and silicon footprint while ensuring minimal latency and power consumption. This NVM Express Controller works seamlessly with Mobiveil's own PCI Express Controller and other NAND Flash controllers.
The RapidIO Verification IP (VIP) created by Mobiveil offers an advanced compliance verification solution tailored for the RapidIO protocol. Built with System Verilog (SV) and supporting Universal Verification Methodology (UVM), this VIP is adaptable and can integrate with other UVM-verification elements for comprehensive system checks. Featuring a layered architecture divided into logical, transport, and physical sections, the RapidIO monitors provide thorough protocol review adhering to the standard specifications. Moreover, it includes comprehensive compliance test suites to validate various protocol scenarios effectively, utilizing automated stimulus generation for high flexibility in test scenarios.
The 5G NR LDPC Decoder IP by Mobiveil provides an adept solution for decoding in the realm of 5G communications. Utilizing the Min-Sum algorithm, it enhances decoding efficiency while allowing programmable internal bit widths. Featuring an early iteration termination capability through a concurrent parity check engine, it optimizes performance further by permitting early exit from iterations. Additionally, the core supports retaining computed LLRs from failed transmissions using HARQ, making it an indispensable tool in advanced 5G applications.
The Universal Multi-port Memory Controller (UMMC) by Mobiveil is an adaptive design supporting a plethora of memory types, including RLDRAM2, RLDRAM3, and various JEDEC-compliant DDR formats. Targeted at applications requiring high bandwidth and low power, this controller is essential for advanced mobile, networking, and consumer technologies. Its architecture guarantees robust and reliable high-frequency operation, encompassing dynamic power management and expediting system debugging processes.
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