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Menta's Adaptive Digital Signal Processor (DSP) IP offers a sophisticated solution tailored for deployment within an embedded FPGA architecture. This DSP IP stands out due to its automatic inference capabilities, facilitated through the Origami tool suite, which allows customization of the DSP architecture to meet specific hardware requirements. The intrinsic flexibility of this DSP makes it well-suited for a wide variety of signal processing tasks. A core characteristic of the Adaptive DSP is its reconfigurability, allowing it to dynamically alter its operating modes through programmed bitstreams. This capability ensures that the DSP can adapt its functionality on-the-fly, in sync with varying computational requirements. The reconfiguration is so granular that it can be controlled on a per-clock cycle basis, providing unparalleled adaptability in signal processing applications. Through the adaptive DSP offerings, users can precisely control operand sizes for both multipliers and ALUs, facilitating optimization based on power, performance, and area constraints. Menta also offers a patented DSP FIR engine that enables users to generate optimized FIR RTL code, with tunable parameters ranging from 4 to 512 taps. This level of customization helps meet specific frequency, area, and latency goals, catering to both high-performance and cost-sensitive applications.
The eFPGA IP Cores offered are versatile solutions designed for embedding programmable logic into your SoC or ASIC designs. High-density in nature, these cores can cater to a broad range of applications across different markets. By integrating eFPGA IPs, designers can tailor the resources to match their application requirements precisely. These eFPGA solutions are available in Soft RTL or Hard GDSII formats, giving developers flexibility in design methodologies. One of the remarkable advantages of eFPGA IPs is their cost-effectiveness. As production volumes increase, traditional on-board FPGAs tend to become financially burdensome, but Menta's embedded solutions offer a more economical alternative. These IPs significantly reduce manufacturing costs and board-space demands while maintaining the vital capability for field upgrades. Moreover, when incorporated into a SoC, they help minimize dependence on chip-to-chip communication, thereby enhancing overall device performance. The eFPGA IPs are well-regarded for power efficiency. Unlike typical commercial FPGAs that incorporate power-hungry elements like high-speed interfaces and controllers, Menta's solutions consume only 10 to 50% of the power needed for similar tasks on a traditional FPGA. This efficiency is especially beneficial in applications where power consumption is critical. Furthermore, the eFPGA's design accommodates rapid process-portability, ensuring adaptability to various technology nodes and foundries.
The Origami Programmer is an innovative software suite specifically designed to optimize and generate bitstreams for eFPGA architectures. This powerful tool bridges design and deployment, ensuring that user RTL is efficiently targeted and optimized for integration with Menta's eFPGA solutions. The Origami Programmer encompasses several critical components such as synthesis, place & route operations, and static timing analysis, providing a comprehensive tool for eFPGA slating. A key feature of the Origami Programmer is its ability to support various hardware descriptive languages, including VHDL, Verilog, and System-Verilog, making it versatile for a wide range of design preferences. This adaptability extends to its user interface, which provides a graphical and user-friendly experience that allows for manual floor planning and resources management. By delivering low LUT usage with optimal routing capabilities, it ensures that designs are both efficient and effective. This software suite sets itself apart by being free from export-control and patent related issues, thus providing peace of mind and operational freedom to international users and developers. Furthermore, its capability to execute density statistics and resource usage summaries provides users with granular control over their designs, all culminated in a streamlined process that enhances productivity and design precision.
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