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The RV32EC_P2 Processor Core is a compact, high-efficiency RISC-V processor designed for low-power, small-scale embedded applications. Featuring a 2-stage pipeline architecture, it efficiently executes trusted firmware. It supports the RISC-V RV32E base instruction set, complemented by compression and optional integer multiplication instructions, greatly optimizing code size and runtime efficiency. This processor accommodates both ASIC and FPGA workflows, offering tightly-coupled memory interfaces for robust design flexibility. With a simple machine-mode architecture, the RV32EC_P2 ensures swift data access. It boasts extended compatibility with AHB-Lite and APB interfaces, allowing seamless interaction with memory and I/O peripherals. Designed for enhanced power management, it features an interrupt system and clock-gating abilities, effectively minimizing idle power consumption. Developers can benefit from its comprehensive toolchain support, ensuring smooth firmware and virtual prototype development through platforms such as the ASTC VLAB. Further distinguished by its vectored interrupt system and support for application-specific instruction sets, the RV32EC_P2 is adaptable to various embedded applications. Enhancements include wait-for-interrupt commands for reduced power usage during inactivity and multiple timer interfaces. This versatility, along with integrated GNU and Eclipse tools, makes the RV32EC_P2 a prime choice for efficient, low-power technology integrations.
The RV32IC_P5 Processor Core from IQonIC Works is designed for medium-scale embedded applications requiring higher performance and enhanced processing capabilities. This 5-stage pipeline processor supports the RISC-V RV32I base instruction set, alongside standard extension instructions such as 'A' for atomic operations, boosting system efficiency. Its ability to run a mix of trusted firmware and user applications allows for diverse operational integration. Supporting both ASIC and FPGA design flows, the RV32IC_P5 incorporates advanced memory interfaces, offering optional instruction and write-back data caches for improved performance and adaptability. It features a tightly-coupled scratchpad memory architecture, ensuring efficient data handling and reduced latency. The processor's architecture also incorporates AHB-Lite interfaces and optional physical memory protections for robust security management. With a vectored interrupt system and support for platform-specific instruction extensions, the RV32IC_P5 provides tailored options for DSP operations. Its toolchain support includes GNU and Eclipse environments, affording developers a streamlined path from concept to execution. The RV32IC_P5 demonstrates a firm focus on power efficiency and enhanced processing capabilities, making it ideal for complex applications demanding reliable processing power and flexibility.
USB-C/PD IP from IQonIC Works encompasses design and manufacturing solutions for integrating USB-C and Power Delivery functionalities into IC/ASIC products. This IP is available as soft IP for digital blocks alongside analog IP schematics, firmware, and hard macros, offering comprehensive support for standalone devices or multi-die packaged solutions. The USB-C/PD IP is versatile, accommodating configurations such as source-only, sink-only, full dual-role port, and accessory support, including for VCONN-powered devices. Its flexible licensing options cater to project-specific needs, supporting both single and multi-technology frameworks. This adaptability ensures that USB-C/PD functions can be efficiently integrated into varying application contexts. By providing a detailed suite of deliverables, including synthesizable Verilog RTL code and full integration guides, IQonIC Works equips developers with the resources necessary for effective implementation. The IP also includes options for communication protocols like SPI and I2C, as well as support for power management, making it an all-encompassing solution for next-generation connectivity challenges.
IQonIC Works offers a comprehensive RISC-V Timer suite, designed to adhere to the standard machine timer specifications set by RISC-V. These timers are pivotal for applications demanding precise timing control, supporting configurations that either count processor clock cycles or operating in low-power environments. Variants include options without clock-domain crossing for straightforward implementations, and versions with it for power-sensitive systems. The RISC-V Timer integrates seamlessly within a variety of system architectures, offering both AHB and APB interface versions to cater to different bus configurations. This ensures wide compatibility and flexibility in deployment, making these timers ideal for both simple and complex embedded systems. In systems where power conservation is critical, the timers can synchronize with low-frequency oscillators, thereby optimizing energy efficiency. Additionally, these timers are equipped to handle multiple interrupt requests, providing fast, reliable interrupt response crucial for real-time applications. Developers can integrate them across various processor systems, supported by robust configuration options that enhance performance consistency and responsiveness in diverse environments. Overall, IQonIC Works' RISC-V Timers offer essential functionalities for precise and efficient embedded system management.
The RISC-V Platform-Level Interrupt Controller (PLIC) by IQonIC Works is a sophisticated, configurable interrupt manager designed to support systems with a vast array of interrupt sources. Adhering to RISC-V specifications, it ensures efficient delivery of interrupts to multiple processor targets, whether in single or multiprocessor architectures. Its capabilities extend to managing up to 1023 interrupt sources across varying priority levels and target configurations. PLIC offers exceptional flexibility through its AHB-Lite interfacing, allowing streamlined access for setting priorities, enables, and handling interrupt claims. Its asynchronous request handling and comprehensive security features ensure dependable and secure interrupt allocation, supporting both synchronous and asynchronous signals. The capability to enable interrupts for multiple targets facilitates efficient resource sharing. In complex systems, the PLIC provides seamless integration with shared bus structures, correlating interrupt requests with processor execution contexts effectively. This integration contributes to a reduction in response latency and boosts overall system reliability. By leveraging IQonIC Works' PLIC, developers can ensure high-performance interrupt management crucial for modern, versatile computing environments.
The Intelligent Sensor and Power Management Platform (ISP) by IQonIC Works is designed to meet the growing demand for efficient and smart sensor-based applications. It offers an extensive suite of design tools and pre-validated subsystems, facilitating rapid development while ensuring cost-effectiveness and adherence to project timelines typical of ASIC derivative projects. This platform is tailored to manage crucial design challenges like power optimization and sensor interfacing. It includes capabilities for power management and energy harvesting, essential for extending battery life or even eliminating battery use altogether. Additionally, it incorporates software programmable components for enhanced control and communication, making it adaptable to a wide variety of IoT applications. IQonIC's ISP supports a comprehensive range of integrated options, such as MCU cores and various I/O components, allowing for customizable solutions to meet specific project needs. With its virtual prototyping capabilities, the ISP accelerates development cycles and optimizes software and hardware integration, enabling quick adaptation to market demands while maintaining robust performance and efficiency.
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