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The RV32IC_P5 Processor Core by IQonIC Works caters to medium-scale embedded applications that require robust performance. Featuring a five-stage pipeline design, it supports complex instruction sets ideal for diverse application coding requirements, including both trusted firmware and user applications. This core utilizes the RISC-V RV32I instruction set and supports the 'A', 'M', and optional 'N' extensions for atomic operations and integer arithmetic. To optimize code execution, the RV32IC_P5 core incorporates features like branch prediction with configurable branch target buffer and return address stack. It supports machine-mode and user-mode privileged architectures with the option for memory protection management for secure application execution. The core aims to deliver high performance with low latency and reduced branching delays. This processor is adaptable for both ASIC and FPGA projects and includes AHB-Lite interfaces, enabling flexible memory management and I/O mapping. Its design is bolstered by a suite of development tools, including a robust virtual prototyping framework that facilitates integration and testing in diverse development environments.
The RV32EC_P2 Processor Core by IQonIC Works is engineered for small, low-power embedded applications, emphasizing dependable performance with its two-stage pipeline architecture. Compliant with the RISC-V RV32E base instruction set and User-Level ISA V2.2, it incorporates RVC compressed instructions for reduced code size. Optional 'M' standard extensions support integer multiplication and division, enhancing computational capabilities. This processor core is adaptable to both ASIC and FPGA design flows. It offers a simple machine-mode architecture with memory direct addressing, supporting 20 interrupts along with software and timer interrupts. Its clock-gating feature aids in reducing power consumption during idle states. Additionally, it supports tightly-coupled memory interfaces compatible with ASIC ROM and SRAM or FPGA block memories. The RV32EC_P2 core also integrates AHB-Lite or APB interfaces for expanded memory and I/O functionalities. Developers can utilize a diverse range of tools, including the GNU toolchain and the Eclipse IDE, for firmware development. This core is optimized for rapid implementation in trust-critical, embedded environments.
IQonIC Works' RISC-V PLIC is a highly flexible and configurable platform-level interrupt controller, designed to facilitate extensive management of interrupt sources in multidimensional system architectures. It conforms to RISC-V specifications, supporting a vast range of interrupt sources—from 31 up to 1023—and offering comprehensive control over priority and delivery. This controller is particularly effective for scalable applications, accommodating up to 32 target contexts. Each interrupt source can be configured for various signals, including synchronous or asynchronous requests and level or edge sensitivity, making it adaptable to intricate hardware requirements. The PLIC interfaces with systems via an AHB-Lite interface for robust register and control management. The RISC-V PLIC is a critical component in complex processor environments, efficiently orchestrating interrupt latency and response times. Its design supports the allocation of secure interrupts, enhancing the reliability and safety of data processing. This IP is suitable for high-performance applications needing efficient and scalable interrupt management across multiple processing units.
IQonIC Works' RISC-V Timer comprises a versatile suite of timers designed to adhere to the RISC-V machine timer standards. It is adaptable to various system requirements, offering configurations suitable for both power-conscious and high-frequency timekeeping needs. Core to its design are variants without clock-domain crossing (CDC) for straightforward cycle counts in processor-clock cycles. For low-power systems where the main clock can be powered down, the Timer IP provides versions utilizing a continuous clock for timing calculations, catering to energy-efficient applications. The architectural design facilitates integration in complex systems with its option for AHB or APB bus interfaces, making it highly compatible with diverse hardware configurations. The Timer IP ensures precise and reliable time management, essential for synchronization across different processes and hardware components. It plays a pivotal role in systems that require robust timer accuracy, supporting efficient time-triggered applications and contributing to the seamless execution of multitasking operations.
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