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The RISC-V Timer IP set provides a robust solution for timing in RISC-V based applications. It complies with the standard machine timer specifications of RISC-V, ensuring accuracy and reliability for both simple and complex timer operations. The IP suits applications where clock domain crossing is either essential or unnecessary, offering variants for high precision or simple timer needs, including configurations with AHB and APB bus interfaces for diverse integration environments. In low-power systems, it supports counting cycles from a low-frequency clock, maximizing efficiency when the main system clock is inactive. This configuration aids systems in maintaining energy efficiency without sacrificing performance during non-active phases. The timer interfaces with both AHB and APB setups, supporting integration in systems with complex or simplified bus structures. The flexibility offered in the IP design allows developers to incorporate timers that meet the particular needs of varied RISC-V applications, promoting customization and adaptability within their embedded environments. Delivered with comprehensive documentation and development support, the timer IP aligns with broader system design requirements, facilitating comprehensive time-management solutions across processor platforms.
The RV32EC_P2 is a 2-stage pipeline RISC-V processor core engineered to serve small, low-power embedded applications, focusing on executing secure and trusted firmware. It adheres strictly to the RISC-V RV32E base instruction set, with compliance to the RISC-V User-Level ISA V2.2, and supports an optional 'M' standard extension for arithmetic operations like integer multiplication and division. Its architecture includes a straightforward machine-mode with direct physical memory addressing, supporting 20 extended interrupts with vectored handling for rapid response. Designed for both ASIC and FPGA design processes, the processor can integrate application-specific instructions pertinent to DSP operations, featuring tightly-coupled memory interfaces for ROM and SRAM operations. The processor is complemented by machine-mode timers compatible with AHB and APB interfaces, enhancing its application breadth across differing performance environments. Furthermore, it employs a power-conserving clock gating mechanism during idle states to minimize power consumption. This processor core interacts seamlessly with memory blocks for code and I/O interfaces using AHB-Lite and APB interfaces. Its architecture ensures fast cycle instruction execution, with most completing in a single cycle, making it a suitable candidate for efficiency-driven applications. It is part of a broader suite equipped with development tools, encompassing a GNU tool chain and Eclipse IDE for firmware development, supported by ASTC's VLAB system-level design.
The RV32IC_P5 is an advanced 5-stage pipeline RISC-V processor core designed for medium-scale embedded systems requiring enhanced performance with cache memory capabilities. This core embraces a sophisticated architecture featuring a RISC-V RV32I base instruction set, compliant with User-Level ISA V2.2, and expands with 'A' extensions for atomic operations necessary in critical sections and multi-threaded environments. The inclusion of a predictive branch mechanism reduces latency, supported by branch prediction tools and configurable cache memory for minimizing response delays. This processor core offers comprehensive support for machine and user-mode operations, with optional PMP configurations for secure execution, managing memory access permissions across different execution contexts. Its flexible interrupt handling capabilities accommodate up to 1023 sources, extending support for complex, interrupt-laden environments. It interfaces with both tightly-coupled scratchpad memory and optional cache memories, contributing robustly to performance improvements for computational tasks. Analog interfaces via AHB-Lite offer memory extensions and controlled I/O operations, while the overall design benefits from compatibility with the GNU tool chain and Eclipse environment, promoting smooth firmware integration. ASTC’s VLAB tools further allow development across virtual environments, ensuring streamlined testing and validation processes.
The RISC-V Platform-Level Interrupt Controller (PLIC) IP stands as a versatile and configurable solution for managing extensive interrupt sources in systems utilizing RISC-V processors. It aligns with the RISC-V PLIC standard, ensuring a consistent integration experience across varied processor configurations. This controller manages a broad range of 31 to 1023 interrupt sources and supports multiple processor targets, with configurations allowing between 1 to 32 target hart contexts. Its structure enables meticulous control over interrupt request properties, including sensitivity and synchronicity, enhancing system responsiveness. The IP uses an AHB-Lite interface to configure priority settings and interrupt management, enhancing its applicability across diverse environments. Its design ensures secure allocation, suitable for both single and multiprocessor applications, supporting complex interrupt schemas across various execution levels. For single-processor setups, the PLIC connects efficiently to AHB matrices, collecting and managing interrupt requests from both AHB and APB devices. In tandem, it manages distributed interrupt requests across a multiprocessor system, ensuring that efficient priority handling and claims are made by the correct processor target, maintaining system-wide coordination and control.
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