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The AES IP Core by IP Cores, Inc. offers a sophisticated implementation of the Advanced Encryption Standard (AES) suitable for environments requiring secure data encryption and decryption. This ultra-compact core is compliant with NIST's AES standard and is suitable for applications needing high security. It processes 128-bit or 256-bit data blocks and supports various encryption modes such as ECB, CBC, CFB, OFB, and CTR, making it versatile for different cryptographic needs. Designed for both ASIC and FPGA platforms, this IP core is fully synchronous and available in source and netlist form for ease of integration. Notably, the core offers features like key expansion and supports data integrity protection and differential power analysis resistance, enhancing its security robustness. For efficient operation, it is available in various configurations with optional features like data masking to protect against side-channel attacks. The core is designed to support high throughput performance and is synthesized to achieve clock speeds exceeding 800 MHz, delivering up to 10 Gbps data throughput. This makes it an apt choice for applications in high-speed communication networks, secure data storage, and digital rights management systems.
The AES Key Wrap Core from IP Cores, Inc. implements the NIST standard AES key wrapping and unwrapping functionalities, ensuring secure key management in digital systems. This core is engineered to support both 128-bit and 256-bit Key Encryption Keys (KEK), permitting secure key exchange and storage practices compliant with AES key management standards. Compactly designed, the AKW1 core utilizes under 8,000 ASIC gates, making it ideal for integration into embedded systems where space is at a premium. The core does not require any external memory resources, adding to its adaptability and ease of incorporation into various hardware environments. Available as both source and netlist, the core also includes the AES key expansion function, supporting flow-through operations with both encryption (wrap) and decryption (unwrap) capabilities. Primarily, this core is suitable for applications requiring secure key wrapping according to the RFC 3394 specification and can be a critical component in systems handling sensitive key data across secure communications and data storage platforms. Its efficient design ensures high throughput, maintaining secure key processing without delay, and is tested with NIST-compliant test vectors to ensure fidelity and security compliance.
The DES/3DES Ultra-Compact Core offers a secure, efficient, and compact design implementing the Data Encryption Standard (DES) and Triple Data Encryption Algorithm (3DES) as per NIST specifications. Capable of processing 64-bit data blocks, it supports encryption and decryption using one, two, or three 56-bit keys, suitable for a variety of security applications. This IP core is remarkably small, utilizing only about 3,000 gates, which is perfect for constrained environments while still delivering up to 3 Gbps throughput at a 750 MHz clock rate in 90 nm technology. It can operate across several encryption modes including ECB, CBC, OFB, CFB, and CTR, providing flexibility depending on application requirements. Primarily used for mobile communications, secure financial transactions, and smart card applications, this core offers optional features such as parity checking and is available as synthesizable Verilog with comprehensive test benches for verification. Its compact design ensures it fits seamlessly into systems where space and power efficiency are crucial.
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