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SystemBIST is a revolutionary product within Intellitech’s IP portfolio, providing unparalleled capabilities for FPGA configuration and JTAG-based embedded testing. As a flexible plug-and-play device, SystemBIST allows the configuration of a wide range of IEEE 1532 or IEEE 1149.1 compliant FPGAs and CPLDs. This makes it highly versatile for design engineers looking to develop high-quality, self-testable products that can be reconfigured in the field, extending product life and adaptability. Built on patented architectures, SystemBIST simplifies typical configuration challenges by embedding built-in self-test (BIST) capabilities, thereby eliminating the need for complex software-driven BIT solutions. This device effectively compresses and stores test patterns and scripts within FLASH memory, allowing for comprehensive PCB testing wherever power is available. SystemBIST caters to a broad spectrum of applications, from normal operation reconfigurations to safe field updates, ensuring that the underlying firmware remains secure against potential threats like trojan bitstreams. Its user-friendly development tools facilitate rapid deployment and debugging, offering developers an efficient means of maintaining system integrity and performance over time.
The Fast Access Controller (FAC) is Intellitech's specialized solution designed for fast and efficient programming of on-board Flash memory, particularly beneficial in production environments. This pre-engineered IP is ideal for designers of processors, SoCs, and ASICs seeking enhanced test capabilities and performance in Flash programming. A key feature of the FAC is its ability to load a minimal bitstream that enables high-speed data transfer to Flash over the IEEE 1149.1 bus. This capability is particularly valuable in reducing the time and complexity associated with programming external memory components on PCBs, making it a preferred choice for environments requiring rapid throughput. By integrating FAC into a PCB design, engineers can respond to customer demands for improved Design-for-Test methodologies and seamless production support without incurring additional costs. FAC is seamlessly integrated with the Eclipse Test Development Environment, ensuring that it is fully supported in both lab and production line settings. This integration not only enables rapid test development and validation but also allows for consistent application across different stages of a product's lifecycle.
The Scan Ring Linker (SRL) is an innovative solution from Intellitech, designed to simplify the complexities of managing multiple scan chains within PCBs. This complete IP module can be effortlessly embedded into CPLDs, FPGAs, or ASICs, effectively linking various scan rings into a singular, high-speed test bus. By doing so, it allows for independent testing and configuration of devices situated on secondary scan chains, streamlined through the IEEE 1149.1 interface. The SRL module facilitates a reduction in design complexity and cost by unifying divergent scan paths, which traditionally require significant overhead to manage. Its implementation ensures that all scan chains operate cohesively, providing a singular route for both test and configuration data. This level of integration considerably enhances the efficiency and reliability of boundary-scan testing, offering an adaptable solution to manage diverse PCB architectures. SRL stands out by seamlessly integrating with the broader Eclipse Testing Environment, ensuring that all test and configuration protocols remain consistent across the PCB’s lifecycle. This underscores the module’s utility across a range of applications requiring precise, efficient JTAG test integration, ensuring that even the most complex systems maintain high reliability and performance.
The JTAG Test and Configuration product line is part of Intellitech's innovative offerings for IEEE 1149.1 boundary scan test and configuration. This toolset provides design and test engineers with a robust solution for in-system device configuration, debugging, and automated testing of PCBs and complex electronic systems. By utilizing the industry-standard JTAG protocol, the product line facilitates high fault coverage and quick test development, which is critical in reducing overall product development costs and time-to-market. This solution offers a seamless integration with the Eclipse Test Development Environment, enabling engineers to conduct interactive debugging and apply pre-validated test suites in both laboratory and production environments. With features like deterministic test patterns and pin-level diagnostics, engineers can identify and rectify issues swiftly, ensuring comprehensive coverage of digital interconnects. Moreover, the JTAG Test and Configuration suite supports extensive in-system programming and reconfiguration capabilities, making it an essential tool in maintaining firmware and software updates throughout the product lifecycle. This ensures that products remain adaptable to changing requirements and remain at peak performance.
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