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SystemBIST is an advanced product offering from Intellitech that provides a plug-and-play solution for flexible FPGA configuration and embedded JTAG testing. It stands out with its proprietary architecture that allows for efficient, codeless configuration of field-programmable gate arrays (FPGAs) as well as built-in system testing capabilities. SystemBIST is designed to be vendor-neutral, supporting any FPGA or CPLD compliant with the IEEE 1532 or IEEE 1149.1 standards. This design enables robust anti-tamper measures and enhances system reliability by embedding JTAG test patterns directly into PCBs.
The Scan Ring Linker (SRL) is a complete IP module that can seamlessly integrate into complex designs to simplify the development of 1149.1 (JTAG) test infrastructure. This module efficiently links numerous scan rings (secondary paths) into a consolidated high-speed test bus, thereby facilitating independent testing and configuration through a single JTAG interface. It enhances design flexibility and reduces costs while catering to designs that entail elaborate scan chains by negating the need for separate test setups per scan ring.
The Fast Access Controller (FAC) is a specialized solution developed by Intellitech, targeting efficient external flash programming in production environments. It is engineered to hasten on-board Flash memory programming, especially when configured with FPGAs, by utilizing a minimal bitstream through the 1149.1 bus. This IP is purpose-built for microcontroller, DSP, and CPU designers, aligning with the demands for enhanced design-for-test features and stronger programming performances in manufacturing processes.
Intellitech's JTAG Test and Configuration solution is a highly innovative software platform designed using the esteemed IEEE 1149.1 standards. This platform facilitates PCB and system testing via automated test program development, executing boundary-scan techniques that are essential in validating intricate PCBs and systems. Leveraging JTAG provides virtual access to test significant nets and pins, enabling automatic test pattern generation to ensure robust diagnostic and fault coverage.
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