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The DVB-S2X LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for better performance and efficiency as well as robust service availability.
The CCSDS AR4JA LDPC Encoder and Decoder FEC IP Core is a configurable design that allows runtime configuration for decoding different code rates (i.e., 1/2, 2/3, and 3/4). To obtain high throughput, two different levels of parallelism are carried out; 128 check nodes and 6 variable nodes which are processed at the same time. Pipeline architecture is followed which significantly speeds up the whole decoding process. Also, layered architecture is implemented which helps to enhance the speed of the decoding process. AR4JA LDPC decoder supports soft decision decoding and hard decision output. Additional features include: CCSDS AR4JA LDPC Code family is quasi-cyclic, irregular parity check matrix, run time configuration for more than one code rate (i.e., 1/2, 2/3, 3/4), configurable codeword size that supports 2K, 3K, and 4K information words, minimum sum algorithm, and layered decoding architecture.
The DVB-S2X Wideband LDPC Decoder is a powerful FEC core decoder for Digital Video Broadcasting via Satellite. It implements extensions to the DVB-S2 design for better performance and efficiency as well as robust service availability. Features include irregular parity check matrix, layered decoding, minimum sum algorithm, and soft decision decoding. The BCH decoder works on GF(2^m) where m=16 or 14 and corrects up to t errors, with t being 8, 10, or 12. It is ETSI EN 302 307-1 V1.4.1 (2014-11) compliant. Other key features include medium codeword length, extra code rates for finer gradation, support for 64, 128, 256 APSK, and operation in very low SNR environments down to -10dB with wideband support. This results in improved performance, efficiency with respect to Shannon’s limit, finer gradation of code rate and SNR, and enables very high data rates and maximum service availability at highest efficiency, along with cross-layer optimization. Deliverables include synthesizable Verilog, system model in Matlab, Verilog test benches, and documentation. A comprehensive DVB-S2X Wideband LDPC/BCH decoder datasheet is available under NDA.
The DVB-T2 Demodulator and LDPC/BCH Decoder is a comprehensive system designed for use with an RF tuner and an analog to digital converter. It features compliance with DVB-T2 EN302 755 V1.2.1, Rev.9 standards and supports flexible channel bandwidths ranging from 1.7 MHz to 10 MHz. The system boasts capabilities like IF input support, SISO operation, sampling frequency offset tracking and compensation, carrier frequency offset detection and correction, and support for BPSK, QPSK, and QAM constellations (16, 64, 256). It includes a layered Min-Sum LDPC decoder and a BCH decoder, with parallel and serial MPEG outputs. The demodulator operates with a single external clock and can be externally configured via an SPI port, enhancing its flexibility and integration into set-top boxes and digital TV receivers.
The Reed Solomon Encoder is fed with an input message of K information symbols, the Encoder appends 2T parity symbols to the input message in order to form the encoded codeword. The Reed Solomon Decoder receives an (N=K+2T) codeword, and it can locate and correct up to 8 possible symbol errors or up to 14 erasures. Both of the Encoder and the Decoder support any input timing pattern, in case of the Encoder; the output timing pattern will be the same as the input. In case of the Decoder; the output timing pattern is fully controlled in order to support any desired pattern by the user. The Reed Solomon Decoder keeps track of corrected errors. Input codewords with more than 8 errors are regarded as uncorrectable, and are flagged. The Implementation of Reed Solomon IP Core targets very low latency, high speed, and low gate count with a simple interface for easy integration on SoC applications.
On the transmitter side, the turbo -phi encoder architecture is based on a parallel concatenation of two double -binary Recursive Systematic Convolutional (RSC) encoders, fed by blocks of K bits (N=K/2). It is a 16-state double-binary turbo encoder. On the receiver side, the turbo decoder engine is built using two functioning soft-in/soft-out modules (SISO). The outputs of one SISO, after applying the scaling and interleaving are used by its dual SISO in the next half iteration. Both the turbo encoder and decoder are fully compliant with the DVB-RCS2, supporting all its code rates and block sizes. In order to achieve higher throughput, the turbo decoder uses parallel MAP decoders. The sliding window algorithm is used to reduce the internal memory sizes. Turbo decoder accepts input LLR’s and outputs the hard decision bits after completing the decoder iterations.
The DVB-C QAM demodulator is designed to be used with a cable tuner and an ADC. It features an internal state machine for operation control, configurable via the SPI interface. The IP supports QAM constellations from 16 to 256, using blind acquisition and decision-feedback mode for tracking. It also includes convolutional interleaving and Reed-Solomon error correction to address signal degradation due to impulse noise. The device offers both parallel and serial MPEG outputs and complies with DVB-C EN 300 429 and ITU-T J.83 Annex A & C standards.
The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
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The Forward Error Correction (FEC) sub-system is one of the essential basing blocks in any communication systems, so a powerful FEC code is needed. The New Radio (NR) FEC for the control channel is designed based on Polar codes, allowing close to the Shannon limit/Capacity operation. It features Polar code successive cancellation decoding, as needed for the 3GPP physical layer standard, with Parity Check bits that simplify the pruning of the search tree. The encoding of the NR Polar code is performed in GF(2), structured using static reliabilities from the ETSI standard. This IP Core supports a maximum code block length of 1024 bits and a minimum of 32 bits. It can be easily integrated with interleavers and Rate matching circuitry to support all rates required by 5G NR. Additional features include successive cancellation decoding with list decoding, soft decision decoding, high peak rates, low latency, and compliance with the 3GPP TS 38.212 V15.1.1 standard. The IP Core is suitable for applications such as 3GPP-LTE Rel. 15 control channels, 5G NR air interfaces, machine-to-machine communication, and high traffic IoT.
The 802.11n/ac/ax LDPC decoder is developed for high throughput WLAN applications. It features layered decoding, soft decision decoding, and is compliant with IEEE 802.11n/ac/ax standards. The decoder supports all LDPC code rates of ½, ⅔, ¾, and ⅚, as well as all LDPC codeword sizes of 648, 1296, and 1944 bits. This IP provides a high throughput design and allows for frame-to-frame on-the-fly configuration, offering configurable LDPC decoding iterations for a trade-off between throughput and error correction performance.
The MIMO MMSE Decoder is designed to decode signals in MIMO systems, employing QR Decomposition and a K-best Decoder. It supports various QAM modes and MIMO configurations, ensuring versatility for applications such as Wi-Fi, WiMAX, LTE, RFID, and DVB-NGH. Features include support for OFDM, configurable MIMO dimensions, and efficient memory usage through a sliding window algorithm.
The designed Single Carrier is a modulator-demodulator platform supporting QPSK constellation for IF and RF transmission. It features adjustable symbol rates from 2608 Baud to 7 M Baud and adjustable bandwidths from 3 KHz to 8 MHz. The system operates in various modes, including analog base band, IF, and RF, and supports sampling rates from 83.457 KHz to 56 MHz. The platform's IF frequency is adjustable between 53.651 KHz and 36 MHz. It includes a roll-off factor of 0.15, an oversampling factor of 32, and a pulse-shaping filter length of 257 taps. The product is suitable for application areas like public safety communication, transportation, utilities, and digital radio.
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