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The TCP Offload Engine (TOE) from easics is a comprehensive IP solution designed to offload the TCP/IP stack from a CPU onto hardware like FPGA or ASIC. This IP core enables efficient data handling and networking by managing TCP/IP processing directly in hardware, thereby liberating the CPU for pure application logic and improving overall system performance. Targeted to high-bandwidth applications, the TOE supports both 1Gbit/s and 10Gbit/s configurations, catering to various industrial networking needs. It boasts support for Ethernet, IP packets, ICMP for pings, and ARP packets, with the 10Gbit/s version also compatible with pause frames. The modular design includes interfaces for industry-standard (X)GMII communication and adaptable FIFO configurations, allowing users to tailor memory usage per application. This hardware-accelerated IP core significantly reduces latency and maximizes throughput, with the 10G TOE capable of achieving a round-trip time (RTT) as low as 1.3µs. Versatile application areas include industrial automation, machine vision systems, and real-time monitoring, addressing the need for high-performance data exchange and minimal system delays.
The nearbAI IP cores are cutting-edge solutions tailored for ultra-low power AI-enabled chips, designed to provide immediate visual and spatial feedback through efficient neural processing. Each core operates as a neural processing unit (NPU) and includes a neural network compiler, making it ideal for live sensory augmentation. It is well-suited for applications requiring real-time data processing, such as battery-powered mobile devices, XR, and IoT applications. These cores are optimized for minimal power consumption while balancing factors like area and latency, ensuring efficient performance across different use cases. They support seamless local processing, maintain high data security, and even offer optional cloud interoperability. nearbAI cores can independently handle data processing, eliminating the need for extensive signal transmission between the sensors and processing units. The architecture of nearbAI supports a broad spectrum of neural networks with zero-latency switching between them, enhancing overall computational efficiency. This includes features like real-time pattern recognition and multi-modal sensor fusion, which are crucial for immersive experiences and high-stakes applications such as face recognition and 3D spatial detection. Flexible and scalable across various silicon technologies from 40nm to 4nm, the nearbAI IP is also complemented by an optimizing compiler that allows for smooth integration and rapid prototyping efforts, thus accelerating time-to-market.
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