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Dyumnin Semiconductors' RISCV SoC is a powerful, 64-bit quad-core server-class processor tailored for demanding applications, integrating a multifaceted array of subsystems. Key features include an AI/ML subsystem equipped with a tensor flow unit for optimized AI operations, and a robust automotive subsystem supporting CAN, CAN-FD, and SafeSPI interfaces.\n\nAdditionally, it includes a multimedia subsystem comprising HDMI, Display Port, MIPI, camera subsystems, Gfx accelerators, and digital audio, offering comprehensive multimedia processing capabilities. The memory subsystem connects to various prevalent memory protocols like DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring vast compatibility.\n\nThe RISCV SoC's design is modular, allowing for customization to meet specific end-user applications, offering a flexible platform for creating SoC solutions with bespoke peripherals. It also doubles as a test chip available as an FPGA for evaluative purposes, making it ideal for efficient prototyping and development workflows.
RegSpec by Dyumnin is an innovative control configuration and status register generator designed to streamline the design process for complex systems. RegSpec supports a range of input data formats such as SystemRDL, IP-XACT, CSV, Excel, XML, or JSON. It can generate comprehensive output including Verilog RTL, System Verilog UVM, SystemC header files, and detailed documentation in HTML, PDF, RTF, Word, and Frame formats. This flexibility allows designers to address complex synchronization, interrupt, and pulse generation features with ease.\n\nFurthermore, RegSpec is equipped to handle advanced CCSR register design edge cases, making it the only tool of its kind that fully supports such comprehensive features industry-wide. It also simplifies the verification process by generating UVM-compatible code and RALF file formats, while also offering C/C++ header file generation for firmware and advanced system modeling.\n\nRegSpec enhances interoperability with other CSR tools by supporting the standard import/export of SystemRDL and IP-XACT formats, while also accommodating XML, CSV, and Excel custom formats. It also saves its data in a JSON format, facilitating easy integration with custom scripts. Its multifaceted capabilities make it a key asset for designers seeking efficient, comprehensive register specification solutions.
The Interconnect Generator from Dyumnin offers a versatile, protocol-agnostic interconnect solution that supports both AXI and OCP master/slaves. It produces interconnect structures in various forms, including simple, pipelined, and crossbar configurations. This flexibility allows the interconnect to adapt to atomic request-response behaviors to more intricate split transactions with independent address and data phases.\n\nThe built-in reorder buffer, featuring customizable depth, ensures efficient data delivery handling multiple outstanding requests and maintaining order. This robust design is vital for system architects looking to build high-performance systems that require reliable interconnect solutions with minimal latency and high data throughput.\n\nThrough its adaptable nature, the Interconnect Generator is well-suited for a variety of applications across different industries, offering a high degree of customization to meet specific design challenges and performance requirements.
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