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Cyclic Design

Cyclic Design, a leader in the semiconductor IP industry, focuses on developing and providing advanced error correction solutions specifically for NAND flash memory interfaces. Their unique approach integrates their error correction code (ECC) IP seamlessly with existing system architectures, simplifying the adaptation to newer flash memory technologies that demand more sophisticated ECC requirements. By providing easily integrable solutions, clients can preserve their current design frameworks and software environments while upgrading to more advanced ECC systems. With the trend towards smaller geometries in NAND flash, the necessity for enhanced error correction capabilities grows, impacting both single-level cell (SLC) and multi-level cell (MLC) devices. Cyclic Design offers its expertise to fill this critical gap, delivering cost-effective ECC solutions that can be adapted to the customer's unique application needs. This strategic support allows companies to concentrate their resources on application development rather than the intricacies of ECC technology development. Founded by a skilled hardware designer, Cyclic Design brings a wealth of experience and understanding to the complex domain of NAND flash controller architecture. They pride themselves on creating modular and easily customizable IP solutions, allowing clients to address specific application requirements. Whether clients require an off-the-shelf solution or a tailored IP configuration, Cyclic Design is equipped to meet these technical demands, ensuring optimal performance and integration within semiconductor systems. Read more

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4
IPs available

512B ECC Error Correction for NAND

Cyclic Design's G13 and G13X IPs are crafted for 512-byte correction blocks, suited for NAND devices with 2KB and 4KB pages. Transitioning from traditional single bit correction using Hamming codes, these IPs support higher bit corrections essential as NAND technologies advance. The G13 IP offers a modular, customizable drop-in upgrade enhancing existing controller architectures with minimal investment, ensuring compatibility with both existing hardware and software.

Cyclic Design
Cryptography Cores, Error Correction/Detection, Flash Controller, NVM Express, Processor Core Independent, SDRAM Controller
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2048B ECC Error Correction for High-Density NAND

The G15 IP is optimized for 2KB blocks, enhancing NAND controllers with a support system for higher ECC levels, simple integration across a variety of applications, and scalability for future technologies. Capable of reducing development costs while allowing customers to modify the source to fit specific requirements, it integrates seamlessly into established designs while also offering advanced ECC options.

Cyclic Design
Cryptography Cores, Error Correction/Detection, Flash Controller, NVM Express, Processor Core Independent, SDRAM Controller
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1024B ECC Error Correction for Advanced NAND

The G14 and G14X IP series optimizes for 1KB correction blocks, designed to transition with MLC flash using 8KB page sizes. The IP supports both current MLC needs and future SLC requirements, providing a bridge as technologies shift. Offering flexibility in block size from 2 to 1800 bytes and customizable for latency and bandwidth needs, this IP ensures robust error correction including ECC4 and ECC8, vital for leveraging new SLC flash generations.

Cyclic Design
Cryptography Cores, Error Correction/Detection, Flash Controller, NVM Express, Processor Core Independent, SDRAM Controller
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256B ECC Error Correction for MRAM

The G12 BCH IP is tailored for 256-byte correction blocks and supports up to 16 bits of error correction, suiting niche applications with smaller block sizes. This design supports dynamic block sizes ranging from 2 to 450 bytes and allows optimization by specifying a maximum ECC level via parameters. The IP supports various configurations and is available in Verilog source with SystemVerilog Assertions.

Cyclic Design
Cryptography Cores, Error Correction/Detection, Processor Core Independent
View Details
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