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Atomic Rules LLC

Atomic Rules LLC stands at the forefront of delivering mission-critical IP cores and solutions that cater to both datacenter and edge applications. Specializing in advanced interconnection networks and reconfigurable computing solutions, they apply scalable and rule-based methods to handle complex operations across heterogeneous processors. The company leverages the rapid advances in chip technology to substantially expand the performance capabilities of existing products. By transcending traditional RTL methodologies, Atomic Rules employs functional programming techniques to create solutions that are efficient, portable, and reusable. This expertise is complemented by their adept handling of Bluespec SystemVerilog, further enhancing the accuracy and scalability of their products. The company's approach to tackling processor interactions is innovative, avoiding the conventional limitations seen in complex systems. This is achieved through a combination of expert SoC/FPGA skills, which are rooted in traditional RTL/ESL design and verification, but also expand towards creating more advanced solutions. Atomic Rules embraces a vendor-agnostic philosophy, supporting both AMD/Xilinx and Intel FPGA platforms, where their IP cores can cater to diverse client needs worldwide. Atomic Rules' portfolio is rich with products that offer seamless integration and optimization for high-throughput applications. Their IP solutions are designed to reduce development timelines, cost, and power consumption while enhancing performance across various platforms. This commitment to excellence makes Atomic Rules a trusted partner for companies aiming for quick market entry with robust, enterprise-grade solutions. Located in Auburn, New Hampshire, Atomic Rules LLC has cultivated a loyal clientele across various industries by consistently delivering high-quality, reliable semiconductor IP solutions. Read more

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5
IPs available

TimeServoPTP

TimeServoPTP extends the remarkable features of the TimeServo timer by complying fully with the IEEE 1588v2 PTP standards. This implementation as an ordinary clock slave for FPGA improves operational precision with synchronization mechanisms that communicate effectively with external network time sources. Supporting both one-step and two-step synchronization, TimeServoPTP facilitates accurate delay requests and enables robust timekeeping in networked environments. This IP is especially vital for applications demanding precise time distribution and synchronization, making it indispensable for systems where timing integrity is critical.

Atomic Rules LLC
25 Views
AMBA AHB / APB/ AXI, Ethernet, IEEE1588, SDRAM Controller, Timer/Watchdog
View Details Datasheet

Arkville Data Mover

Arkville Data Mover facilitates seamless data transfer between FPGA logic and host memory, achieving rates of up to 480 Gbps. It serves as a high-performance conduit between a host's memory and FPGA fabric, optimizing CPU usage by minimizing unnecessary data transfers. This IP core supports industry-standard APIs and RTL interfaces, allowing software engineers and hardware engineers to effortlessly integrate it into their systems. Its design ensures enhanced data handling efficiency and lower latency, making it ideal for high-throughput applications in sophisticated FPGA deployments.

Atomic Rules LLC
23 Views
AMBA AHB / APB/ AXI, Ethernet, PCI
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UDP Offload Engine

The UDP Offload Engine is designed to optimize data throughput by supporting multiple Ethernet speeds up to 400 GbE. It offloads the UDP protocol stack to FPGA hardware, freeing CPU resources and increasing data transfer rates. This IP core includes features like checksum, segmentation, and reassembly, with added support for multicast selection via IGMPv2. The integration allows for seamless interoperability across different networking environments, offering high efficiency and capability to handle large UDP packets. It's ideally suited for network applications demanding high-speed data processing and minimal latency, ensuring compatibility with a variety of industry-standard FPGA Ethernet MACs.

Atomic Rules LLC
23 Views
Ethernet, Receiver/Transmitter, USB
View Details Datasheet

ARDSoC Embedded DPDK

ARDSoC is tailored for ARM-based SoCs and enables users to conserve ARM processor cycles by bypassing traditional Linux network stacks. It adopts DPDK technology for embedded systems, specifically designed to enhance the MPSoC PS/PL architecture by providing an embedded solution that reduces power consumption and latency while maintaining robust performance. ARDSoC allows for the execution of existing DPDK programs with minimal adjustment, thus reducing the overall cost of ownership and operational latency. Its features include sub-microsecond latency and zero-copy DPDK coherent memory structures, ensuring high throughput and minimal data loss. Ideal for embedded protocol bridges and cloud-edge devices, ARDSoC optimizes packet processing for various applications.

Atomic Rules LLC
20 Views
AMBA AHB / APB/ AXI, Audio Processor, CPU, Input/Output Controller
View Details Datasheet

TimeServo System Timer

The TimeServo system timer IP core offers sub-nanosecond resolution and sub-microsecond accuracy, perfect for FPGA applications needing precise timing mechanisms. It is specifically designed for line-rate independent packet timestamping, though its applications are broader, addressing high-resolution timing requirements. Featuring a PI-DPLL, TimeServo synchronizes with an external PPS signal to achieve exceptional syntonicity. Additionally, its IEEE-1588v2/PTP capabilities allow it to operate as a fully compliant ordinary slave device without host interaction, ensuring seamless timing operations across systems. TimeServo's configurability allows for flexible clock domains, making it adaptable to varied FPGA-based applications.

Atomic Rules LLC
20 Views
AMBA AHB / APB/ AXI, Timer/Watchdog
View Details Datasheet
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