ADICSYS

eFPGA IP

ADICSYS's eFPGA IP presents a versatile solution for integrating flexible logic within ASICs and SOCs. This soft FPGA IP, known as the Synthesizable Programmable Core (SPC), serves as an essential component for reducing risks related to design changes and errors in complex systems. By enabling corrections or modifications post-production, SPC considerably decreases time-to-market and mitigates bug-related risks, offering the flexibility to adapt and upgrade at the transistor or gate level. The eFPGA IP uses standard ASIC CAD tools and methods, ensuring no disruption to traditional design flows. With transparent models and ease of verification, it streamlines the design phase while retaining adaptability to project demands. This flexibility is further enhanced by the capability to synthesize the IP from existing standard cells, reducing physical design complexities. Designed with portability in mind, the eFPGA IP can be easily integrated into recent technology nodes, bridging the traditional custom cell design gap. Its scalable design accommodates varying needs without constraining project strategy, offering extensive usefulness in post-silicon processes and late-stage project decisions.