All IPs > Wireline Communication > Optical/Telecom
In the realm of wireline communication, Optical and Telecom semiconductor IPs play a pivotal role in ensuring robust connectivity and high-speed data transfer across global networks. As the demand for faster and more reliable communication channels grows, these semiconductor IPs provide the foundational technology for modern telecommunication systems and fiber optic networks.
Optical/Telecom semiconductor IPs are critical for enabling the efficient transmission and reception of data over optical fibers. These IPs include various components such as optical transceivers, modulators, and detectors, which convert electronic signals into optical signals and vice versa. This conversion is essential for high-speed data transmission over long distances, a crucial requirement for both enterprise and consumer telecommunications.
Beyond merely converting signals, Optical/Telecom semiconductor IPs must handle complex signal processing tasks to reduce errors, maximize bandwidth, and optimize data integrity. This includes forward error correction (FEC), signal modulation, and wavelength division multiplexing (WDM) technologies. Such capabilities are vital for sustaining the rapidly increasing data loads due to burgeoning internet usage, video streaming, and cloud computing services.
Products in this category of semiconductor IP range from highly sophisticated optical communication modules to integration-ready telecom processors. They are developed to support a broad array of applications, such as backbone internet infrastructures, 5G networks, data centers, and undersea cable systems. These cutting-edge solutions ensure that network providers can offer seamless and reliable service, empowering users with exceptional connectivity experiences. By leveraging advanced Optical/Telecom semiconductor IPs, industries can continue to innovate and meet the ever-evolving demands of a digitally connected world.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ArrayNav is an innovative GNSS solution that employs multiple antennas, enhancing sensitivity and accuracy to combat common issues like multipath interference and signal jamming. This technology is designed to increase the effectiveness of global positioning systems by using adaptive antenna systems, a concept borrowed from advanced wireless communications. ArrayNav provides up to 18dB gain in signal strength for fading channels and ensures robust performance even in complex environments like urban canyons. By identifying and nulling unwanted signals, it maintains the integrity of GNSS operations against spoofing and interference. This technology is vital for applications needing high precision under challenging signal conditions. With its sophisticated antenna diversity, ArrayNav is crafted to deliver sub-meter precision and swift signal acquisition. This makes it a valuable component for navigation in densely constructed urban landscapes or covered environments where satellite visibility might be obscured. ArrayNav's capability to handle multipath and interference issues effectively makes it a preferred choice for high-reliability navigation systems, contributing to both enhanced security and accuracy.
Rockley's Multi-Channel Silicon Photonic Chipset is designed as a next-generation solution for high-speed data transmission. This sophisticated chipset integrates hybrid III-V DFB lasers and electro-absorption modulators within a silicon photonic framework, providing 4x106 Gb/s 400 GBASE-DR4 data rates. Each channel achieves high modulation amplitude and low TDECQ penalty, delivering compliance with industry standards. This scalability ensures robust performance for data centers and high-bandwidth communication needs. The chipset exemplifies Rockley's expertise in combining optical components to craft preciseness and efficiency suited for heavy data-centric environments.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The SMS OC-3/12 Transceiver Core represents a pivotal advancement in SONET/SDH transceiver technology, designed to adhere to stringent jitter specifications using a novel deep sub-micron single poly CMOS design. The transceiver incorporates a fully integrated architecture, which features internal clock synthesis, precise clock recovery, wave shaping, and a low-jitter LVPECL interface. Its design complies with all relevant ANSI, Bellcore, and ITU jitter specifications, proving its applicability for use in complex multi-port customer SOC designs. This transceiver is adept at handling multiple integration scenarios on a single IC, making it suitable for sophisticated System-On-Chip applications. Advanced proprietary signal processing techniques embedded in the transceiver ensure effective clock recovery by providing on-chip noise filtering, a significant enhancement over existing solutions. As designed for multiple integration, it supports various selectable reference frequencies, boasting a customized CMOS architecture to precisely control jitter transfer, tolerance, and generation.
The EW6181 is an advanced multi-GNSS silicon designed for high sensitivity and low power consumption, a stand-out product in GPS and GNSS technology. It supports multiple global positioning systems like GPS L1, Glonass, BeiDou, Galileo, SBAS, WASS, and A-GNSS. This silicon includes an integrated RF frontend, a digital baseband for signal processing, and ARM MCU to efficiently run the necessary firmware. This chip is tuned for low energy use, incorporating a DC-DC converter along with high voltage and low voltage LDOs, which makes it ideal for battery-powered devices. Its size and energy efficiency make it a competitive module component that reduces the overall Bill of Materials (BoM) for manufacturers. The EW6181's architecture is optimized for cloud readiness, offering enhanced capabilities for applications needing intensified accuracy and power savings through cloud connectivity. A unique feature of the EW6181 is its implementation in a 2-antenna Evaluation Kit, showcasing its potential to improve device connectivity and performance with antenna diversity mode, perfect for rotating devices like action cameras and wearable tech. This diversity offers key advantages in both connectivity and user experience, emphasizing the EW6181 as a flexible, high-performing component in various technological ecosystems.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The iniHDLC controller from Inicore Inc. is specifically designed for high-speed data communication over serial lines, supporting the HDLC protocol to facilitate a broad spectrum of telecommunication applications. This controller is optimized for hardware efficiency and reliability, able to manage numerous channels simultaneously for expansive network deployments. It is engineered for seamless integration within ASIC and FPGA environments, thus catering to the needs of developers focused on creating scalable and robust telecommunication systems. The iniHDLC controller's architecture is established upon a structured synchronism that guarantees minimal latency and high transfer rates, offering an ideal balance between performance and resource allocation. With customizable features, it can be tailored to fit specific project purposes, making it a flexible choice for designers aiming to enhance data throughput and communication accuracy.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
This IP core implements the Serial Front Panel Data Port standard, facilitating high-speed, low-latency communication for applications such as defense, research, and medical imaging. It supports various link configurations and has been validated on prominent FPGA platforms.