All IPs > Wireline Communication > Optical/Telecom
In the realm of wireline communication, Optical and Telecom semiconductor IPs play a pivotal role in ensuring robust connectivity and high-speed data transfer across global networks. As the demand for faster and more reliable communication channels grows, these semiconductor IPs provide the foundational technology for modern telecommunication systems and fiber optic networks.
Optical/Telecom semiconductor IPs are critical for enabling the efficient transmission and reception of data over optical fibers. These IPs include various components such as optical transceivers, modulators, and detectors, which convert electronic signals into optical signals and vice versa. This conversion is essential for high-speed data transmission over long distances, a crucial requirement for both enterprise and consumer telecommunications.
Beyond merely converting signals, Optical/Telecom semiconductor IPs must handle complex signal processing tasks to reduce errors, maximize bandwidth, and optimize data integrity. This includes forward error correction (FEC), signal modulation, and wavelength division multiplexing (WDM) technologies. Such capabilities are vital for sustaining the rapidly increasing data loads due to burgeoning internet usage, video streaming, and cloud computing services.
Products in this category of semiconductor IP range from highly sophisticated optical communication modules to integration-ready telecom processors. They are developed to support a broad array of applications, such as backbone internet infrastructures, 5G networks, data centers, and undersea cable systems. These cutting-edge solutions ensure that network providers can offer seamless and reliable service, empowering users with exceptional connectivity experiences. By leveraging advanced Optical/Telecom semiconductor IPs, industries can continue to innovate and meet the ever-evolving demands of a digitally connected world.
The OC-3/12 Transceiver Core embodies a robust design catering to SONET/SDH requirements, particularly OC-3 and OC-12 data rates. This transceiver adopts an innovative architecture, leveraging submicron single poly CMOS processes to adhere to stringent jitter specifications. The design integrates sophisticated clock synthesis, recovery, and wave shaping features. It also utilizes advanced signal processing techniques that ensure immunity to external noises by providing on-chip filtering. Supporting high-frequency PLLs with integrated loop filters, this IP is well-suited for multi-port system-on-chip (SoC) applications that demand versatility and interoperability with various existing solutions.
The EW6181 GPS and GNSS Silicon is designed to offer superior performance with minimal power consumption. This silicon solution integrates multi-GNSS capabilities, including support for GPS L1, Glonass, BeiDou, and Galileo signals. It incorporates patented algorithms that ensure a compact design with exceptional sensitivity and accuracy, all while consuming little power. The chip includes a robust RF front-end, a digital baseband processor for signal processing tasks, and an ARM MCU for running firmware that supports extensive interfaces for varied applications. With built-in power management features like DC-DC converters and LDOs, the EW6181 silicon is particularly suitable for battery-operated devices that demand low BoM costs. Additionally, it includes antenna diversity capabilities, highlighted with a two-antenna implementation to enhance connectivity, making it ideal for devices subject to frequent orientation changes, such as wearable tech and action cameras. The EW6181 is cloud-ready, allowing it to operate in a connected environment to optimize power usage further and enhance accuracy and sensitivity. When used with EtherWhere's AccuWhere cloud service, the silicon can significantly reduce device-side computations, leading to longer battery life and more frequent location updates, tailored for modern navigation and asset tracking applications.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The SpaceWire Node by SoC-e provides a reliable platform for high-speed data transfer across space and satellite networks. This node is fully compliant with the ECSS-E-ST-50-12C space standard, ensuring it meets rigorous industry requirements for space communications. SpaceWire Nodes are integral to satellite systems, facilitating real-time communication between different modules within spacecraft. By providing communication speeds up to 200 Mbps, these nodes enhance data throughput without compromising on reliability or data integrity. With built-in AXI4-Lite management interfaces and statistic registers, the SpaceWire Node supports efficient data handling and monitoring, making it a critical component for robust aerospace networking solutions. It offers seamless interoperability with existing space communication protocols and systems, facilitating expansive networks of connected satellite nodes.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
ArrayNav is an innovative GNSS solution that applies multiple antennas to significantly improve signal sensitivity and accuracy. This advanced technology is an adaptation from the communication sector’s use of MIMO, tailored to address GNSS challenges like multipath errors and potential signal jamming. By employing a diversified antenna setup, ArrayNav enhances signal gain and diversity, achieving higher accuracy, especially in environments prone to signal degradation such as urban canyons. The multi-antenna approach allows for distinct identification and suppression of interfering signals, including those used for spoofing or jamming, by analyzing their unique signatures. The system effectively places null signals in the direction of such disturbances, maintaining the reliability and precision of positioning data. This makes ArrayNav particularly beneficial for applications reliant on sub-meter accuracy and quick acquisition. ArrayNav’s patented capabilities ensure robust GNSS performance, even in constrained environments, by boosting channel gain by 6 to 18 dB. This gain significantly improves operational efficacy in various applications, from automotive advanced driver-assist systems (ADAS) to personal navigation devices, ensuring dependable operation no matter the surroundings.
The Multi-Channel Silicon Photonic Chipset is an advanced solution designed for high-speed data transmission with enhanced performance characteristics. This chipset employs a unique hybrid integration of III-V Distributed Feedback (DFB) lasers and electro-absorption modulators, tailored to meet the stringent demands of modern communication standards, especially for data rates up to 400 Gbps. Each channel within the chipset achieves high extinction ratios and optimal optical modulation amplitude (OMA), ensuring low Transmission Dispersion Eye Closure Quotation (TDECQ) penalties. Adhering fully to IEEE standards, it supports extensive data transmission over vast networks, demonstrating the robustness and flexibility needed for both telecommunication and data center applications. This chipset is notable not only for its high data throughput capabilities but also for its ability to maintain performance consistency across multiple channels simultaneously. Deployed within systems requiring efficient and reliable optical communications, the Multi-Channel Silicon Photonic Chipset supports the growing needs of high-bandwidth applications, playing a crucial role in evolving network architectures.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.