All IPs > Wireline Communication > Fibre Channel
Fibre Channel semiconductor IPs are crucial components in the infrastructure of high-speed data transfer systems tailored to enterprise storage networking. Known for their reliability and high performance, these semiconductor IPs enable efficient data communication essential for critical data center environments. Fibre Channel technology is a key driver in maintaining seamless connectivity and data flow across enterprise storage networks, ensuring that shared storage resources are accessible, robust, and efficient.
In the realm of wireline communication, Fibre Channel is often chosen for its ability to handle substantial amounts of data traffic with low latency, making it an indispensable technology in settings that require rapid storage and retrieval of information. This technology significantly boosts data handling capabilities and is particularly efficient in managing complex storage area networks (SANs). Moreover, the inherent scalability of Fibre Channel IPs offers enterprises the flexibility to expand and adapt their storage solutions as their data management needs evolve.
Products in this category of semiconductor IP range from basic cores designed for integration into larger system solutions to more advanced IP modules that provide comprehensive functionalities necessary for Fibre Channel implementation. These may include transceiver modules, protocol engines, and physical layer interfaces, all meticulously designed to adhere to industry standards and interoperability requirements. By using Fibre Channel IPs, developers can ensure that their products support high-speed data processing, offering an edge in competitive markets where performance and reliability are paramount.
The adoption of Fibre Channel semiconductor IPs in enterprise networks translates into higher efficiency and enhanced capability to support applications that require substantial bandwidth, such as virtualization and large transactional databases. As data demands continue to grow, leveraging Fibre Channel technology becomes even more critical in the strategic planning of network and storage architecture, providing foundational support for future technological advancements in data management systems.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The iCan PicoPop® System on Module (SOM) is a high-performance miniaturized module designed to meet the advanced signal processing demands of modern avionics. Built on the Zynq UltraScale+ MPSoC from Xilinx, it provides unparalleled computational power ideal for complex computation tasks. This SOM is perfectly suited for embedded applications within aerospace sectors, offering flexibility and performance critical for video processing and other data-intensive tasks. The compactness of the PicoPop® does not detract from its capabilities, allowing it to fit seamlessly into tight spaces while providing robust functionality. The versatility and scalability of the iCan PicoPop® make it an attractive option for developers seeking high-data throughput and power efficiency, supporting enhanced performance in avionics applications. By leveraging cutting-edge technology, this module elevates the standard for embedded electronic solutions in aviation.
Ethernet Solutions by PRSsemicon are crafted to enable high-speed communication across various platforms and structures. These solutions are designed to keep pace with evolving Ethernet specifications, ensuring seamless integration into new and existing networking systems. Providing support for a wide range of Ethernet speeds—from 1G to 800G—these solutions accommodate diverse networking needs, providing robust and reliable communication pathways for data centers and enterprise environments. The inclusion of MAC controllers, PCS, and switch functionalities underscores their versatility. Ethernet Solutions ensure optimal data flow and connectivity, making them ideal for applications needing high bandwidth and low latency. Leveraging Interlaken and CPRI/eCPRI protocols, system designers can create efficient, high-performance networks suited for modern communication challenges.
The 56G SerDes Solution is engineered to support high-speed data communication needs, featuring both NRZ and PAM4 modulation techniques to achieve rates up to 56Gbps per lane. It is compliant with varied communication protocols and incorporates advanced error correction and built-in self-test (BIST) capabilities. This solution is well-suited for optical and copper-based technologies, proving instrumental in applications requiring robust data integrity and signal optimization over large distances. Developed with advanced FinFET technology, it integrates seamlessly into high-performance computing platforms.