All IPs > Wireline Communication > Error Correction/Detection
In the realm of wireline communication, ensuring the integrity and reliability of data transmission is a critical concern. This is where Error Correction and Detection semiconductor IPs play a pivotal role. These IPs are designed to identify and rectify errors that occur during data transmission, thus enhancing the overall performance and reliability of wireline communication systems. Whether it involves correcting single-bit errors or detecting complex data discrepancies, these IPs are essential for maintaining the fidelity of data transmission.
Error Correction and Detection IPs utilize various sophisticated algorithms and techniques such as Reed-Solomon, Hamming Code, and Cyclic Redundancy Check (CRC). These technologies work by adding redundancy to the data being transmitted, allowing the receiver to detect errors and, in many cases, automatically correct them. This process not only protects data integrity but also ensures higher quality of service, reducing the need for retransmissions and improving network efficiency.
These semiconductor IP blocks are implemented in a wide array of applications including broadband networks, data centers, and telecommunication systems where uninterrupted and accurate data transmission is paramount. For engineers and developers, leveraging these IPs can significantly accelerate the development process of wireline systems by providing ready-to-integrate solutions that uphold communication standards.
In this category, you will find a vast selection of Error Correction and Detection semiconductor IPs suited for various applications. These IPs are available from leading suppliers, offering solutions that support multiple protocols and data rates. With these IPs, developers can ensure their wireline communication products are robust, reliable, and capable of delivering the highest levels of performance needed in today's data-driven world.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The PolarFire FPGA Family by Microsemi is engineered to deliver cost-effectiveness alongside exceptional power efficiency, positioning itself as the optimal choice for mid-range FPGA applications. Crafted to offer transceivers ranging from 250 Mbps to a robust 12.7 Gbps, these FPGAs cater to diverse bandwidth requirements. With logic elements spanning 100K to 500K and incorporating up to 33 Mbits of RAM, the PolarFire series seamlessly addresses demanding processing needs while ensuring secure and reliable performance. At the heart of its design philosophy is a focus on best-in-class security features combined with high reliability, making it particularly relevant for industries like automotive, industrial, and communication infrastructures where failure is not an option. It supports applications that require low power consumption without sacrificing performance, which is increasingly important in today's energy-conscious environments. These FPGAs find their versatility in a range of applications, from driving advancements in ADAS in the automotive industry to supporting broadband and 5G mobile infrastructures in telecommunications. The family also extends its use cases to data center technologies, highlighting its adaptability and efficiency in both digital and analog processing fields. With such a broad spectrum of applicability, the PolarFire FPGA Family stands as a shining example in Microsemi's product arsenal, delivering solutions tuned for innovation and performance.
Creonic offers a diverse array of miscellaneous FEC (Forward Error Correction) and DSP (Digital Signal Processing) IP cores, catering to various telecommunications and broadcast standards. This collection of IP cores includes highly specialized solutions like ultrafast BCH decoders and FFT/IFFT processors, which are critical for managing high-throughput data streams and maintaining signal fidelity. These IP cores embody the latest in processing technology, delivering precise error correction and signal transformation functions that are essential in complex communication networks. Their integration capabilities are made easy with detailed hardware specifications and software models, designed for flexibility across different platforms and applications. The rigorous development process guarantees that each core adheres to market standards, optimizing performance and ensuring operational reliability. Creonic's portfolio of miscellaneous FEC and DSP cores stands out for its innovative contributions to digital communications, providing unique solutions that meet the sophisticated requirements of modern connectivity.
Creonic's Turbo encoders and decoders provide powerful forward error correction techniques applicable in wireless communication systems, including 4G LTE and DVB-RCS2. Known for the efficiency in managing bandwidth and minimizing data loss, these IP cores are designed to boost communication integrity and performance. Leveraging sophisticated iterative algorithms, Turbo encoders and decoders execute precise error detection and correction with high data throughput. They are crafted to integrate seamlessly into various hardware platforms, with detailed hardware models and software reference models available for easy incorporation into any system. This versatility ensures that Creonic's Turbo solutions are suitable for both new and existing infrastructures. Quality assurance remains a cornerstone for these products, with each IP core undergoing extensive validation to meet demanding specifications. By addressing critical needs in modern communication systems, Creonic’s Turbo offerings continue to be a preferred choice for engineers and developers striving for reliability and efficiency.
Polar encoders and decoders by Creonic serve as vital components in enhancing data integrity for next-generation communication frameworks such as 5G. These IP cores are designed to deliver superior coding efficiency and robust performance in varied network conditions, supporting high-speed data transmissions while maintaining low latency. The technology stands out for its innovative use of polar codes, noted for their capacity to achieve channel capacities effectively. Creonic's Polar solutions include hardware and software models tailored for straightforward integration into diverse computational environments. They provide excellent adaptability and scalability across multiple hardware systems, making them ideal for cutting-edge digital communication networks. Backing their robust technological framework, Creonic ensures that each product adheres to strict industry standards through comprehensive testing and quality assurance. The result is a set of highly reliable Polar encoders and decoders designed to enhance the performance and efficiency of advanced communication systems.
Secantec's BCH Error Correcting Code offers a zero-latency solution designed for markets that demand high-fidelity data transmission and storage. Adopting a similar asynchronous and clock-free architecture to its other IP offerings, the BCH code performs operations purely through combinatorial logic, ensuring rapid encoding and decoding. This IP is especially suitable for environments where storage space is at a premium, as it requires no additional memory elements. It handles bit-level Galois Field operations effectively, making it an excellent choice for systems needing precise error control with minimal hardware overhead. Applications of the BCH ECC span across SSD controllers, optical communications, and any field that requires robust data integrity assurance amidst high-speed transfers. The IP's configurability allows it to tailor its error correction capabilities to meet specific industry needs, maintaining a balance between performance and resource conservation.
The 5G NR LDPC Decoder from Mobiveil provides advanced error correction capabilities vital for the next generation of wireless communications. Utilizing the Min-Sum algorithm, it offers programmable bit width options and an iteration termination feature based on a concurrent parity check engine. It efficiently manages redundant transmissions, enhancing performance specifically for 5G applications.
Roa Logic's 8b/10 Decoder module provides a complete implementation of the 8b10b coding scheme developed by Widmer and Franaszek, ensuring reliable error correction and data integrity in high-speed communication systems. This module identifies and processes special comma characters and the K28.5 control character, key components of the 8b/10b coding scheme. Ideal for digital systems where data integrity and error correction are paramount, the 8b/10 Decoder acts as a critical interface in the transmission of encoded digital signals. Its robust design effectively guarantees the data is transmitted accurately, reducing error rates and ensuring robust communication channels between devices. The implementation of this decoding scheme is essential for systems that require high reliability in data transmission, such as storage solutions, network interfaces, and other communication devices. It offers the assurance of data accuracy, facilitating complex digital communications with its advanced error-handling features.
The Error Correction IP from CoMira Solutions integrates robust forward error correction capabilities into network interfaces, effectively mitigating data integrity issues over lossy communication channels. As network speeds continue to rise, maintaining reliable data transfer has become more challenging due to physical layer constraints. CoMira’s FEC IP employs Reed Solomon and Firecode algorithms to enhance data recovery capabilities within Ethernet and other communication protocols. The IP supports both standard compliant configurations and customizable options for aligning with specific application requirements.
The Reed Solomon Error Correcting Code ECC provided by Secantec is ideal for high-speed, high-reliability data communications. This error correction code leverages a low-power, asynchronous design with no storage or clock requirements, making it efficient in terms of power usage and speed. It is designed to address both symbol errors and detect multiple uncorrectable symbol errors. This IP is fully configurable, able to handle a variety of error scenarios by adjusting its Galois Field operations according to different bit-widths and polynomial degrees. With separate encoders for each 't' value and a shared decoder for multiple error scenarios, the code provides a flexible yet robust approach for numerous applications. Applications for this technology are broad and include SSD controllers, space communications, optical systems, and high-speed communications. It is particularly beneficial in scenarios that demand rigorous error detection and correction in data storage systems as well as dynamic fault prevention in ASIC and FPGA designs.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
LDPC (Low-Density Parity-Check) encoders and decoders from Creonic are designed to enhance data transmission reliability in complex communication systems. These IP cores support various standards, including DVB-S2X, 5G-NR, and IEEE 802.11, offering exceptional error correction capabilities essential for high-speed data transfer. Utilizing advanced algorithms, Creonic's LDPC solutions deliver robust performance while minimizing complexity and power consumption. The LDPC encoders and decoders embody state-of-the-art hardware models and bit-accurate software reference models for seamless integration into existing systems. The hardware models are compatible with FPGA platforms from leading manufacturers, ensuring adaptability across different technological environments. Comprehensive test environments accompany the IP cores, facilitating smooth deployment and validation. Creonic’s commitment to quality is evident in the rigorous testing processes each IP core undergoes, guaranteeing compliance with stringent industry standards. The LDPC solutions are available for download from secured servers, reflecting Creonic's focus on security and accessibility for their global clientele.
The Reed Solomon Erasure Code by Secantec is a highly efficient solution designed for RAID and other storage applications, where the location of errors is known, but not the original data. This code is notable for its asynchronous and combinatorial gate-based operation, eliminating the need for clocks and storage elements like RAMs or Flip-Flops. It features a zero-latency encoding and decoding process, enabling it to swiftly recover erasures with minimal power consumption. The erasure code is configurable, with a symbol 'm' bit size suitable for Galois Field operations, and it can manage up to a maximum set of erasure positions. The design includes a sophisticated error correction capability, adaptable to application-specific requirements. Programmability extends to the number of error symbols correctable 't' and the number of symbols by which the code is shortened. This IP finds applications in data centers as a Data Processing Unit (DPU) for error correction, making it indispensable for environments requiring high fault tolerance and reliability. Its flexible design ensures that it can operate across different metrics of 'm', 't', and shortened code settings, optimized to meet performance and power efficiency benchmarks.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The 100 Gbps Polar Encoder and Decoder from IPrium is a high-speed solution designed to meet the needs of ultra-fast data transmission networks. Polar coding, known for its capacity-achieving attributes, ensures that data can be transmitted reliably even near the channel capacity limit. This encoder and decoder pair excels in providing comprehensive error correction capabilities while accommodating substantial data rates, essential for cutting-edge telecommunication networks and data centers. By implementing sophisticated polar codes, these cores manage to minimize error rates, enhancing overall communication fidelity. With applications spanning from 5G networks to data-intensive server environments, the 100 Gbps Polar Encoder and Decoder is a versatile tool for future-proofing network infrastructure. By utilizing this technology, IPrium combines high throughput with reliable error correction, catering to the evolving demands of modern digital communication frameworks.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
Cyclic Design's 512B Error Correction block is specifically tailored for NAND applications, providing robust support especially for NAND devices utilizing page sizes of either 2KB or 4KB. Historically, NAND technology has evolved from requiring minimal error correction to now managing more complex ECC requirements, driven by SLC NAND's transition to tighter geometries. The 512B ECC solution is vital for maintaining system reliability and functionality, offering adaptability with dynamically variable block sizes from 2 to 900 bytes, allowing optimization based on the specific ECC levels required. Enhanced by SystemVerilog Assertions, the design is adept at seamlessly integrating into existing controller architectures, thus minimizing the need for extensive redesigns and helping customers extend their existing solutions with minimal additional investment.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The Convolutional Encoder and Viterbi Decoder core is a transformative IP solution, catering to custom polynomial requirements across various applications. This IP core is vital in telecommunications, providing error correction capabilities which are critical in transmitting information across noisy communication channels. By enhancing data integrity and reducing the likelihood of transmission errors, the encoder and decoder significantly bolster system performance.
IP-Maker's BCH Encoder/Decoder IP core is designed to enhance the reliability and lifespan of NAND Flash-based storage by correcting errors in data writes. Incorporating the BCH algorithm, this core supports up to 76 error-bits per block, ensuring data integrity during storage reads and writes. This capability is crucial for maintaining performance and accuracy in data-intensive applications. The core's customization options enable optimization for different use scenarios, balancing between latency and gate count. In FPGA and ASIC designs, the IP is highly configurable, allowing specifications adjustments such as block size and data throughput. This makes it adaptable for various application scales, from small IoT devices to large data centers. Delivered as Verilog RTL with synthesis scripts and technical documentation, the BCH core simplifies development and integration processes. Fully tested in both simulated and hardware environments, it brings great reliability to storage solutions, reducing time-to-market and ensuring a smooth development cycle for OEMs.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The SOQPSK-TG LDPC Modulator by IPrium offers superior modulation capabilities, integrating Selectable Offset Quadrature Phase-Shift Keying with Turbo-LDPC coding. This combination is especially beneficial for aerospace telemetry where high efficiency and robustness are required for data transmission over long distances. This sophisticated modulator supports reliable data modulation, essential for maintaining the integrity of data in critical communication paths such as those between spacecraft and ground stations. Its design focuses on achieving high spectral efficiency and power efficiency, optimizing frequency utilization while minimizing power consumption. Spacecraft communications benefit greatly from this modulator due to its error correction performance, contributing to mission safety and success. IPrium's dedication to high-performance standards ensures that this product not only meets but exceeds industry expectations for aerospace communication systems.
The 1024B Error Correction technology from Cyclic Design accommodates evolving NAND requirements, specifically catering to NAND devices employing larger page sizes like 8KB. Designed with flexibility in mind, this ECC module supports both 512B and 1024B correction blocks, providing a future-proof solution for SLC and adaptable functionality for MLC flash applications. With dynamically adjustable block sizes between 2 and 1800 bytes, users can calibrate it for an optimal balance of performance and area efficiency. This feature set extends the lifespan and reliability of NAND flashes while ensuring thorough data integrity. The ability to handle varying levels of error correction without extensive rewrites or infrastructure overhauls allows it to integrate smoothly into existing ecosystems.
The 2048B Error Correction solution by Cyclic Design is the company's most advanced ECC offering, optimized to support larger correction blocks essential for high-capacity NAND technologies. Ideal for flash devices with 8KB page sizes, this solution supports correction blocks from 2 to 3600 bytes, designed to tolerate a wide array of ECC levels. Enhanced features include customizable integration for single or multiple channel configurations and options for ECC levels extending up to 96 bits by request, all delivered in an efficiently integrated Verilog source format. The sophisticated error correction capabilities of the 2048B ECC ensure data accuracy and system robustness, making it a strategic choice for high-performance NAND environments where data integrity is crucial.
Corigine's Ternary Content Addressable Memory (TCAM) is designed to substantially improve the efficiency and capability of network devices like routers and switches. Powered by their proprietary Questflo algorithm, this TCAM provides enhanced performance metrics with four times the capacity and three times the search efficiency compared to conventional solutions.<br> <br> This TCAM solution is notable for its fixed latency and high performance, allowing for up to four parallel searches at a maximum capacity of 160 Mb. With the ability to handle up to 4 million IP routes or 512 thousand rules, the Corigine TCAM is crucial for high-speed operations in networking environments.<br> <br> Optimized for use in IP classification, packet forwarding, and security in routers, this high-flexibility TCAM supports various key generation tables and mixing modes. Its cutting-edge architecture guarantees a robust throughput of one search cycle per operation, which is vital for applications that require high-end speed and capacity without sacrificing energy efficiency.
Creonic's demodulation IP cores are central to efficient signal processing in communication systems, addressing the needs of both conventional standards like DVB-S2 and more recent versions such as DVB-S2X. These IP cores decode complex modulated signals robustly, ensuring high-rate data transmission accuracy crucial for applications like satellite communications. The demodulators leverage advanced algorithms to adaptively process signals with minimal distortion and noise, thus maintaining data integrity across long distances and varying conditions. Compatibility with multiple digital modulation techniques is a notable feature, making these cores versatile and highly applicable to diverse communication protocols. Testing and validation at multiple levels are conducted to ensure these cores meet the rigorous demands of modern communication environments. Creonic's dedication to quality and innovation is reflected in their demodulation solutions, making them a trusted choice for reliable, high-performance signal processing.
The IEEE Floating Point Multiplier/Adder IP core facilitates complex mathematical operations by executing multiplication and addition in IEEE floating-point format with high precision. Targeting applications that require intensive computation, particularly in DSP and high-speed calculation environments, this core efficiently processes large datasets. It supports rapid numerical computation without sacrificing accuracy, making it indispensable for scientific and engineering tasks where accurate floating-point calculations are pivotal.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The Interlaken PHY Solution provides an efficient interface for high-bandwidth data streams, targeting the needs of networking and communications where low latency and high throughput are critical. This solution is suitable for large data center applications, where it mitigates congestion by supporting scalable networking infrastructures. The Interlaken protocol blends data transfer efficiency with robust error correction, allowing seamless data flow even as network scales increase. It supports multiple lanes and channels, enabling parallel data transactions that boost performance. This IP core is configurable to fit diverse requirements, making it adaptable for various industrial and commercial applications. By implementing the Interlaken protocol, organizations benefit from reduced power consumption and increased operational efficiency, essential traits in today's energy-conscious ecosystems.
Creonic's modulation IP cores are crafted to optimize data transmission through sophisticated signal processing. These cores support various specifications, including DVB-S2X, providing efficient modulation capabilities that enhance signal robustness and transmission reliability, essential for wireless communication technologies. Leveraging state-of-the-art algorithms, these modulation cores ensure effective transformation of digital data into signals that can be accurately transmitted through different media channels. The compatibility with a range of hardware architectures underscores their adaptability, which is further facilitated through comprehensive software and hardware models for seamless integration. As with all Creonic products, the modulation cores are subjected to stringent quality checks to assure performance and compliance with global standards. This dedication to excellence ensures Creonic's modulation cores are an exemplary choice for engineers looking to boost efficiency and integrity in data communication systems.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The PCE03D turbo encoder is a sophisticated device designed for DVB-RCS and IEEE 802.16 WiMAX applications, utilizing an eight-state configuration. It is optimized to provide high-speed encoding performance, essential for modern wireless communication systems. The encoder supports robust signal processing, ensuring data integrity and transmission efficiency across various network environments.
This PCD03VH turbo decoder supports 3GPP LTE and 3GPP2 1xEV-DO networks with its eight-state high-speed configuration. It is engineered to minimize latency through ping-pong input and output memory configurations. This feature allows for effective parallel processing, making it extremely efficient for LTE and advanced CDMA applications where rapid response and system flexibility are critical. The decoder's architecture is built for robust performance in demanding communication situations.
Designed for IEEE 802.16 WiMAX systems, the PCD03W4 turbo decoder features an eight-state duobinary setup. With its four parallel MAP decoders, it achieves high-speed performance necessary for modern broadband wireless access networks. The decoder's architecture is built to maximize data throughput while maintaining reliability and efficiency. Its duobinary configuration aids in enhancing data integrity, supporting seamless integration into existing network infrastructure.
The PCD04I turbo decoder is intended for use in Inmarsat communication systems. Its design includes a sixteen-state turbo decoder and boasts optional Viterbi decoding with capabilities extending to 64 or 256 states. This feature-rich decoder enhances performance by ensuring efficient error correction and data processing. Its integration options enable seamless compatibility with various communication platforms, making it an ideal solution for satellite communication applications.
RIFTEK's Speed and Length Sensors are designed for precise, contactless monitoring of moving materials, such as fibers, steel, and textiles, enabling accurate control over production processes. These sensors utilize advanced optical techniques to measure both speed and length, ensuring that manufacturing operations maintain quality and efficiency. The ISD-5 series, based on Laser Doppler Interferometry, excels in industrial environments, offering high accuracy for speed measurements across a wide range. This series supports harsh industrial standards with reliable operational metrics, providing speed and distance data essential for process optimization in metallurgy and cable industries. Conversely, the ISD-3 series employs Raster Spatial Filtration, a technique well-suited for automotive and rail applications. It provides highly dependable readings across varying surfaces and conditions, ensuring performance even under rapid operational changes. These sensors serve as integral components in maintaining rigorous quality standards and operational efficiency, underscoring their importance in automated production environments.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The PCD03D turbo decoder is known for its eight-state duobinary design, making it suitable for both DVB-RCS and IEEE 802.16 WiMAX applications. It boasts an optional 64-state Viterbi decoder, enhancing its decoding capabilities. Designed with a focus on high-speed execution, this decoder is ideal for meeting the rigorous demands of modern wireless communication systems. Its versatility is further heightened by the support for multiple concurrent MAP decoders, ensuring robust data processing across numerous platforms.
Small World Communications' PCD03L8 turbo decoder offers robust performance for 3GPP LTE systems, utilizing an eight-state design and parallel MAP decoders. Its architecture supports high-speed operations with options for 1, 2, 4, or 8 parallel decoders to enhance data throughput. The sophistication of this decoder lies in its ability to efficiently manage complex data streams, making it ideal for LTE networks where speed and reliability are paramount.
Specially tailored for 3GPP UMTS/LTE and 3GPP2 systems, the PCD03V turbo decoder excels with its eight-state configuration. It includes an optional multi-state Viterbi decoder capability, supporting up to 256 states for enhanced decoding accuracy. By addressing the complex demands of both UMTS and advanced CDMA networks, this decoder is an essential component in maintaining superior signal clarity and data efficiency. Its adaptability to different communication standards makes it a critical asset for telecommunication applications.
The PCD03T is designed for TETRA-TEDS communication systems, featuring an eight-state turbo decoder with optional Viterbi decoding capabilities. This product is crafted to tackle the challenges of error correction in critical communication infrastructures, ensuring data integrity and performance. With the ability to integrate seamlessly into existing systems, it supports a range of states, enhancing its versatility and functionality within diverse digital environments.
The PCE04I Inmarsat Turbo Encoder is a specialized 16 state turbo encoder. It features unique capabilities that enable it to adapt to varying technological demands. Known for its robust encoding performance, it is designed to handle communication tasks efficiently, ensuring high-speed and reliable data processing. The encoder is built to be versatile, catering to different environments where turbo encoding is vital for optimal performance.
The DVB-C demodulator is designed to handle cable video and broadband data transmission effectively. Integrating forward error correction (FEC), this core is instrumental for facilitating reliable communication in cable systems. It ensures accurate signal processing, even in complex environments characteristic of modern cable networks, where high bandwidth and bi-directional communication channels are prevalent. Commsonic's DVB-C demodulator addresses the challenges posed by compressed digital video delivery, broadband, and voice-over-IP services. This core's implementation supports various DVB decoding functions, enabling efficient data handling and high-speed cable modem functionality. Through its robust design, it ensures high-speed data services are reliably delivered to end users. The core's adaptability makes it suitable for deployment in many intricate scenarios, such as head-end digital video services and broadband data systems. By supporting multiple modulation schemes and delivering optimized performance, the demodulator upholds the complex requirements of modern cable communications, facilitating seamless data and video transmission services.