All IPs > Wireline Communication
Wireline Communication semiconductor IPs are critical components in the semiconductor industry, playing a vital role in enabling efficient data transmission across fixed networks. They are designed to optimize the performance of data transfer over physical media like copper cables, fiber optics, or hybrid systems. Given the growing demand for faster and more reliable data transmission, these IPs are indispensable in the development of network infrastructure and communication devices.
Products within this category cover a wide array of technologies essential for different communication protocols. For instance, Ethernet IPs are fundamental for creating network interfaces capable of high-speed data exchange, contributing to the performance of local and wide-area networks. The Fibre Channel IPs are specifically tailored for storage area networks, providing high-speed, lossless data transmission which is crucial for data-intensive applications in enterprise environments.
Additionally, this category includes Error Correction/Detection IPs, critical for maintaining data integrity during transmission by identifying and rectifying errors without needing retransmission. Our portfolio also comprises IPs for Modulation/Demodulation which play a key role in preparing data for transmission and ensuring it is correctly interpreted upon receipt. Other pivotal subcategories include ATM/Utopia, which aid in asynchronous transfer mode communications, and CEI, which contribute to high-speed chip-to-chip and board-to-board communications.
Overall, Wireline Communication semiconductor IPs facilitate the development of robust and efficient communication solutions across various industries. Whether for building telecommunication infrastructure or advancing next-generation networking devices, these IPs are central to achieving high performance, scalability, and reliability in wireline communication networks.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
KPIT offers a comprehensive solution for Autonomous Driving and Advanced Driver Assistance Systems. This suite facilitates the widespread adoption of Level 3 and above autonomy in vehicles, providing high safety standards through robust testing and validation frameworks. The integration of AI-driven decision-making extends beyond perception to enhance the intelligence of autonomous systems. With a commitment to addressing existing challenges such as localization issues, AI limitations, and validation fragmentation, KPIT empowers automakers to produce vehicles that are both highly autonomous and reliable.
The Connected Vehicle Solutions by KPIT focus on integrating in-vehicle systems with the broader connected world, transforming the cockpit experience. Utilizing high-resolution displays, augmented reality, and AI-driven personalization, these solutions improve productivity, safety, and user engagement. The company's advancements in over-the-air updates facilitate seamless vehicle interactions and connectivity, ushering in new revenue streams for OEMs while overcoming the challenges of system integration and market competitiveness.
KPIT's propulsion technologies cover both traditional internal combustion engines and modern electric powertrains. By focusing on reducing the total cost of ownership for new energy vehicles, KPIT helps OEMs streamline development cycles and enhance vehicle quality. The company's platform supports agile software updates and sustains efforts on sustainable practices by increasing offerings in zero-emission vehicles (ZEVs) and exploring alternative fuels like hydrogen. With solutions spanning engine subsystems, transmission, and driveline optimization, KPIT addresses the intricate balance needed between legacy and emerging automotive platforms.
Specially optimized for high-performance computing environments, the Ultra-Low Latency 10G Ethernet MAC IP delivers unparalleled speed and efficiency within FPGA designs. Crafted to accommodate high data throughput, this IP core excels in applications demanding high-speed data connectivity with stringent latency requirements. Harnessing cutting-edge technology, the Ethernet MAC design minimizes latency significantly, facilitating smooth and rapid data transmission across network layers. Its architecture supports high data throughput while maintaining efficiency within the FPGA, ensuring competitive performance in various network settings. Engineers can benefit from the Ultra-Low Latency 10G Ethernet MAC's versatile licensing, allowing for integration in diverse project specifications and budget parameters. By utilizing this IP core, systems not only achieve optimized speed but also enhance their reliability and responsiveness in handling data operations.
The NaviSoC by ChipCraft is a sophisticated GNSS receiver system integrated with an application processor on a single piece of silicon. Known for its compact design, the NaviSoC provides exceptional performance in terms of precision, reliability, and security, complemented with low power consumption. This well-rounded GNSS solution is customizable to meet diverse application needs, making it suitable for IoT, Lane-level Navigation, UAV, and more. Designed to handle a wide range of GNSS applications, the NaviSoC is well-suited for scenarios that demand high accuracy and efficiency. Its architecture supports applications such as asset tracking, smart agriculture, and time synchronization while maintaining stringent security protocols. The flexibility in its design allows for adaptation and scalability depending on specific user requirements. The NaviSoC continuously aims to advance GNSS technology by delivering a holistic integration of processing capabilities. It stands as a testament to ChipCraft's innovative strides in creating dynamic, high-performance semiconductor solutions that excel in global positioning and navigation. The module's efficiency and adaptability offer a robust foundation for future GNSS system developments.
The UDP Offload Engine (UOE) by Intilop is a specialized component designed to enhance the throughput of networks handling extensive amounts of UDP traffic. Offering ultra-low latency, this engine significantly mitigates the processing demands on CPUs by offloading the processing tasks associated with UDP protocol layers. The UOE integrates a suite of functions that permit faster data transmission and reception, crucial for real-time applications such as video streaming and Voice over IP (VoIP), where uninterrupted and swift data flow is critical. By eliminating the bottleneck traditionally caused by CPU-bound UDP packet processing, the UOE ensures that systems can achieve higher data rates and improved response times without overburdening the CPU. Its capacity to handle numerous concurrent UDP sessions without sacrificing speed makes it ideal for deployment in environments requiring constant high-performance networking, such as media servers and VoIP systems. Emphasizing both hardware efficiency and software compatibility, this engine exemplifies Intilop's commitment to delivering top-tier networking solutions.
The CT25205 integrates several building blocks of the IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. Designed with Verilog HDL, this digital core is optimized for implementation on both standard cells and FPGA architectures, ensuring seamless compatibility with IEEE Ethernet MAC interfaces through MII. The core's standout feature is the integrated Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer, which allows existing MACs to leverage PLCA benefits without additional hardware modifications. A key aspect of this design is its connectivity to an OPEN Alliance 10BASE-T1S PMD Interface, streamlining integration into Zonal Gateways and MCUs. Paired with Canova Tech's complementary IPs, such as the CT25208 MAC controller, CT25205 forms the backbone of cutting-edge communication systems in industries requiring efficient data exchange. The CT25205 supports a wide array of industrial applications due to its robustness and capability to enhance the existing communication frameworks. It is particularly well-suited for automotive and industrial environments where reliable and durable Ethernet solutions are crucial.
The 10G Ethernet MAC and PCS solution provides ultra-low latency Ethernet connectivity for FPGAs, specifically catering to applications requiring high-speed data transfer. Supporting throughput rates up to 10Gbps with minimal FPGA resource usage, this IP block is designed to integrate seamlessly with existing FPGA infrastructures, enhancing both performance and efficiency. The MAC/PCS integrates all necessary functionalities, reducing the need for additional components and ensuring a compact implementation. Chevin Technology's expertise allows for the offering of Ethernet IP solutions that are compliant with industry standards such as IEEE 802.3. The MAC/PCS leverages technologies that provide both ease of integration and scalability, which are pivotal for applications anticipating future growth or changes in data demands. In this way, the MAC/PCS maintains flexibility while ensuring reliable network communication. Focused on delivering quality performance, this MAC/PCS suit offers measures to minimize delay and jitter, crucial for applications where timing and reliability are paramount. It also includes advanced capabilities such as VLAN tagging and QoS support, enabling enhanced data traffic management and prioritization, which are vital in sophisticated network environments.
The H-Series PHY supports the latest in high-speed memory interfaces, specifically engineered for comprehensive compatibility with a range of memory standards. By generating extensive support ecosystems including Design Acceleration Kits, this PHY aims to streamline integration and enhance performance for high-demand applications. With significant emphasis on minimizing die size, while optimizing both performance and latency, this PHY is particularly useful for graphics and compute-intensive operations where speed and reliability are paramount.
Wasiela's DVB-S2-LDPC-BCH provides a sophisticated forward error correction system designed for digital video broadcasting applications, particularly suited for satellite transmission. This product combines low-density parity-check (LDPC) codes with Bose Chaudhuri Hocquenghem (BCH) codes to achieve quasi error-free operation, operating effectively close to the Shannon limit.<br><br>The implementation boasts an irregular parity check matrix and layered decoding to increase decoding efficiency. The minimum sum algorithm is utilized for optimal performance with soft decision decoding capabilities that allow for higher error correction. This product also complies with ETSI EN 302 307-1 V1.4.1 standards, ensuring high quality and reliability in digital transmission systems.<br><br>Additional functionalities include a BCH decoder adept at correcting multiple errors per codeword, making this solution an ideal choice for ensuring data integrity in demanding satellite communication conditions. Wasiela offers this IP complete with synthesizeable Verilog code, a system model in Matlab, and thorough documentation, ensuring a smooth integration process for any application.
The CXL 3.1 Switch is a sophisticated piece of technology designed to enable comprehensive connectivity and interoperability across various high-performance computing devices. By supporting the latest CXL 3.1 standards, this switch provides multi-level switching capabilities, enabling efficient resource management and data processing in large-scale server environments. It ensures seamless integration between differing devices, from GPUs to memory expanders, managing complex data traffic with optimized latency and bandwidth. This switch is crucial for cloud and data center applications, providing a backbone for systems requiring significant scalability. With features supporting multi-device connectivity and port-based routing, the CXL 3.1 Switch facilitates memory sharing and data coherence across diverse hardware, enhancing overall system efficiency. Its role in forming CXL-enabled AI clusters makes it a cornerstone for the next generation of AI-driven services, allowing vast data resource pools to be dynamically allocated where needed. The innovative architecture of the CXL 3.1 Switch integrates advanced communication protocols to handle large data volumes effectively. It provides unmatched latency performance that elevates computing speeds and minimizes bottlenecks. The adaptation of this technology within AI clusters highlights its potential in accelerating AI inference and training tasks, making it an indispensable tool for modern computational needs.
Intilop's 10G TCP Offload Engine (TOE) is engineered to advance the efficiency of data center networks by minimizing the processing burden on CPU resources. This TOE is designed to facilitate high-speed communication between servers and networking hardware, delivering exceptional performance with very low latency results. The integration of this engine into network architectures allows for the acceleration of TCP/IP packet processing, effectively freeing up significant CPU cycles that can be redirected towards application-centric tasks. This results in improved server performance and reduced power consumption, making it an environmentally friendlier option compared to conventional software-based TCP/IP stacks. This product is tailored to meet the needs of enterprise-grade applications that demand reliable performance and stringent timing requirements, such as network-attached storage systems and high-frequency trading environments. By leveraging FPGA-based design, the 10G TOE offers unparalleled customization and adaptability to evolving network conditions and requirements.
eSi-Comms represents EnSilica’s suite of communication IP blocks, designed to enhance modern communication systems through flexible, parameterized IP. These IPs are optimized for a range of air interface standards, including 4G, 5G, Wi-Fi, and DVB, providing a robust framework for both custom and standardized wireless designs.\n\nThe flexibility of eSi-Comms IP allows it to be configured for various interfacing standards, supporting high-level synchronization, equalization, and modulation techniques. The suite includes advanced DSP algorithms and control loops that ensure reliable communication links, vital for applications like wireless sensors and cellular networks.\n\nEnSilica also supports software-defined radio (SDR) applications by offering hardware accelerators compatible with processor cores like ARM, enhancing processing power while maintaining flexibility. This adaptability makes eSi-Comms IP a valuable asset in developing efficient, high-performance communication solutions that can quickly adapt to changing technological demands.
The PolarFire FPGA Family is designed to deliver cost-efficient and ultra-low power solutions across a spectrum of mid-range applications. It is ideal for a variety of markets that include industrial automation, communications, and automotive sectors. These FPGAs are equipped with transceivers that range from 250 Mbps to 12.7 Gbps, which enables flexibility in handling diverse data throughput requirements efficiently. With capacities ranging from 100K to 500K Logic Elements (LEs) and up to 33 Mbits of RAM, the PolarFire FPGAs provide the perfect balance of power efficiency and performance. These characteristics make them suitable for use in applications that demand strong computational power and data processing while maintaining energy consumption at minimal levels. Additionally, the PolarFire FPGA Family is known for integrating best-in-class security features, offering exceptional reliability which is crucial for critical applications. The architecture is built to facilitate easy incorporation into various infrastructure setups, enhancing scalability and adaptability for future technological advancements. This flexibility ensures that the PolarFire FPGAs remain at the forefront of the semiconductor industry, providing solutions that meet the evolving needs of customers worldwide.
A cutting-edge Ethernet Chiplet supporting speeds up to 400G, designed for high-bandwidth networking applications. This chiplet utilizes ultra-low latency features to ensure rapid data transmission in data centers and enterprise networks, optimized for future-proof networking standards.
The D2200 PCIe SSD is a high-performance storage solution designed for data centers and enterprise applications. With its advanced PCIe interface, the D2200 delivers superior speed and efficiency, making it ideal for heavy data processing and storage needs. This SSD is crafted to offer high sustained performance, ensuring smooth and fast data throughput for critical operations. Employing cutting-edge technology, the D2200 caters to environments requiring high reliability and large-scale data handling capabilities. Its architecture is tailored to reduce latency and maximize data pipeline efficiency, supporting robust business applications and persistent data storage functions seamlessly. In essence, the D2200 PCIe SSD is engineered for those seeking reliable and efficient data management solutions that do not compromise on speed or performance. True to Swissbit's standard, the D2200 stands as a testament to their dedication to delivering high-quality storage solutions to meet dynamic market demands.
nxLink Network Infrastructure is crafted to optimize wireless network management and address latency challenges. Employing FPGA technology, it offers advanced processing capabilities that enhance network stability and performance, crucial for investment banks and market data providers. The suite incorporates features like fair bandwidth allocation, link redundancy, and fiber arbitration, ensuring reliable data transmission even under adverse conditions. nxLink is tailored for diverse networking requirements, providing scalable options that can be adapted to different infrastructural needs, thus making it an invaluable asset for maintaining competitive edge in fast-paced trading environments.
The Reed Solomon Error Correcting Code ECC targets environments where error minimization during high-speed data processing is paramount. Its design capitalizes on a zero-latency, asynchronous processing model that negates the need for clocks and iterative data storage, using basic combinatorial logic to streamline error correction. This error correction code stands out due to its adjustable parameters, including the symbol size and the count of correctable error symbols, enabling operators to modify the code for optimal performance based on specific requirements. This flexibility extends to its coding structure, which uses minimal clock cycles for execution, thus fast-tracking error detection and recovery processes. It is ideally suited for an array of applications such as digital storage systems, communication networks, and wherever data robustness is critically assessed. The IP’s reliability is further enhanced through a verified and lint-clean RTL, tailored to meet diverse error correction needs efficiently and effectively.
Secure-IC's Secure Protocol Engines provide high-performance IP blocks aimed at offloading network and security processing tasks. These engines are designed to efficiently accelerate cryptographic operations within both FPGA and ASIC environments. They allow for seamless integration into existing security architectures, facilitating enhanced data protection and processing speed, which are essential in modern high-performance computing scenarios.
The CT25203 serves as a critical part of Canova Tech's Ethernet solutions, providing an analog front-end compliant with the IEEE 802.3cg 10BASE-T1S standard. By using this IP, device designers can achieve outstanding electromagnetic compatibility performance crucial for modern communication systems' stability. Supporting a high-voltage process technology, CT25203 is optimized for compact devices with an 8-pin package, ideal for industrial and automotive environments that require dependable connectivity and robust communication links. Its architecture ensures seamless communication over the 3-pin OPEN Alliance interface with host devices like MCUs and Ethernet switches. These features allow it to meet the rigorous demands of industries requiring compact and efficient solutions, resulting in reliable and efficient performance that integrates seamlessly with other Canova Tech IP offerings, thereby simplifying design and reducing time-to-market.
The ePHY-5616 is engineered for high-performance applications requiring efficient data control and operations, capable of supporting data rates ranging from 1Gbps to 56Gbps. This versatile architecture is adaptable to various applications, offering configurable bandwidth to meet diverse connectivity needs. Leveraging a 16/12nm node process technology, it delivers optimized power efficiency and data integration solutions. Designed to manage a wide insertion loss range, the ePHY-5616 boasts a scalable approach to data handling. It incorporates advanced clock data recovery and reliability mechanics ensuring minimal downtime and exceptional data signal integrity. This makes it a standout choice for enterprise networking, data centers, 5G applications, and other sectors reliant on sustained data throughput and proficient error correction. Utilizing a programmable DSP-based architecture, the ePHY-5616 is crafted to meet extensive application requirements. It uses proprietary algorithms to simplify integration efforts and accelerate system deployment. Supporting Direct Attached Cable and Optical Drive, it is highly suitable for dynamic, state-of-the-art networking applications demanding high data transmission fidelity and reliability.
TimeServoPTP extends the remarkable features of the TimeServo timer by complying fully with the IEEE 1588v2 PTP standards. This implementation as an ordinary clock slave for FPGA improves operational precision with synchronization mechanisms that communicate effectively with external network time sources. Supporting both one-step and two-step synchronization, TimeServoPTP facilitates accurate delay requests and enables robust timekeeping in networked environments. This IP is especially vital for applications demanding precise time distribution and synchronization, making it indispensable for systems where timing integrity is critical.
Trion FPGAs by Efinix are engineered to meet the demanding needs of the fast-paced edge computing and IoT markets. These FPGAs feature Efinix's innovative Quantum® compute fabric, providing a compact yet powerful processing platform. Particularly suitable for general-purpose applications, Trion devices cover a range of logic densities to suit various needs, from mobile and IoT to consumer-oriented and industrial applications. Built on a 40 nm process node, Trion FPGAs incorporate critical functionalities such as GPIO, PLLs, MIPI interfaces, and DDR controllers, establishing a versatile base for numerous potential implementations. These features allow developers to address complex compute tasks efficiently, making Trion FPGAs ideal for scenarios where space is at a premium and performance cannot be compromised. Trion FPGAs are designed for development speed and simplicity, supported by their small package sizes and efficient power consumption. This makes them particularly appropriate for handheld devices and application sectors such as med-tech and smart home technology. With ready capabilities for image enhancement, feature extraction, and real-time data processing, Trion FPGAs facilitate the rapid deployment of smart solutions. Besides their technical robustness, Trion devices offer a strategic advantage with their long-term lifecycle support until at least 2045, aligning with the extended production needs typical in industrial fields. This, coupled with their seamless configuration and migration features, sets Trion FPGAs apart as a top choice for integrated and edge applications.
The 100G UDP Offload Engine from XtremeSilica is designed to handle UDP network protocol tasks, enhancing overall system performance by reducing the processing burden on central processing units. It provides streamlined packet processing facilities that significantly speed up data communication. Deployed in environments requiring fast, reliable data transmission such as streaming services, this engine excels in handling large-scale data traffic efficiently. Its offloading capabilities optimize the networking load, making it ideal for applications needing high packet throughput and low latency. It supports versatile network protocols and operations, ensuring flexible integration into existing systems. This technology contributes to smoother, more efficient operations by optimizing data flow and resource management within extensive network infrastructures.
Flexibilis Ethernet Switch (FES) is a triple-speed Ethernet Layer 2 switch IP designed for industrial and commercial applications requiring robust and fast networking capabilities. FES integrates precision time functionality through IEEE 1588v2 compliant implementations, providing essential support for quality time synchronization in extensive networks. With the ability to provide gigabit forwarding per port, the FES ensures high-speed data transfers across numerous network interfaces efficiently. Standard compliance with IEEE 801.3x and compatible Media Access Control allows FES to robustly manage Ethernet frames while maintaining optimal performance. FES prioritizes traffic using effective packet prioritization techniques, ensuring more critical data streams maintain low latency and reliability. This Ethernet switch IP core's modular design accommodates various network topologies and interface standards, enhancing its versatility in complex systems. Users can select from different port configurations, scaling from small networks up to larger connected systems, reinforcing its application scope in diverse environments such as industrial networks and large data centers.
The HOTLink II Product Suite is specifically designed to enhance and support optical communication within advanced avionics systems. It stands as a pivotal element for systems requiring robust high-speed data transmission, such as graphics generation and flight simulation. The product suite offers engineers a reliable framework to develop and optimize communication channels within their systems, addressing the need for precise data flow in demanding operational environments. This suite's capabilities extend to simplifying design processes by integrating essential tools that facilitate the development of complex communication systems. Such systems are vital for ensuring seamless data transmission in avionics, where precision and reliability are crucial. The HOTLink II Product Suite empowers developers to create highly efficient optical interfaces that meet the challenges of modern aerospace and defense applications. In addition to its core functions, the suite offers comprehensive resources that aid in enhancing the overall performance of optical data links. It provides engineers with the flexibility to adapt the technology for use across various platforms, ensuring consistency and reliability of data flow, which is essential for maintaining the integrity of flight-critical systems.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The Polar encoding and decoding IP, compliant with 3GPP standards, offers comprehensive support for various uplink and downlink channels in 5G NR. Utilizing advanced decoding techniques, it provides unparalleled error correction with scalable parameters for parallelism and latency optimization. The Polar solution by AccelerComm is a versatile and powerful option for deploying efficient communication systems, supporting FPGA and ASIC processes, and offering flexibility in system design and implementation, significantly contributing to high error correction performance.
Topaz FPGAs from Efinix are designed for volume applications where performance and cost-effectiveness are paramount. Built on their distinctive Quantum® compute fabric, Topaz devices offer an efficient architecture that balances logic resource availability with power minimization. Suitable for a plethora of applications from machine vision to wireless communication, these FPGAs are characterized by their robust protocol support, including PCIe Gen3, MIPI D-PHY, and various Ethernet configurations. One of the standout features of Topaz FPGAs is their flexibility. These devices can be effortlessly adapted into systems requiring seamless high-speed data management and integration. This adaptability is further enhanced by the extensive logic resource options, which allow increased innovation and the ability to add new features without extensive redesigns. Topaz FPGAs also offer product longevity, thriving in industries where extended lifecycle support is necessary. Efinix ensures ongoing support until at least 2045, making these FPGAs a reliable choice for projects aiming for enduring market presence. Among the key sectors benefiting from Topaz's flexibility are medical imaging and industrial control, where precision and reliability are critical. Moreover, Efinix facilitates migration from Topaz to Titanium for projects requiring enhanced performance, ensuring scalability and minimizing redesign efforts. With varying BGA packages available, Topaz FPGAs provide comprehensive solutions that cater to both the technological needs and strategic goals of enterprises.
The IFC_1410 is an Intelligent FMC Carrier AMC designed to deliver high-performance processing capabilities within the compact MTCA.4 form factor. Built around NXP QorIQ T Series processors and Xilinx FPGA devices, including the Artix-7 and Kintex UltraScale, this product offers a robust platform for implementing advanced control systems, primarily in high-energy physics and communication applications. The emphasis of this platform is on providing a versatile environment that can cater to rigorous processing and data handling demands in critical fields. This solution is engineered to support a wide variety of high-speed data acquisition and control tasks, with a design aimed at streamlining integration with existing systems. It provides an excellent basis for enhancing data throughput and computational efficiency in mission-critical deployments. The versatile capabilities of the IFC_1410 make it a cornerstone product in IOxOS Technologies' line-up, positioning it as an ideal choice for enterprises seeking to extend the boundaries of their current data acquisition and control frameworks.
The 100 Gbps Polar Encoder and Decoder from IPrium is a high-speed solution designed to meet the needs of ultra-fast data transmission networks. Polar coding, known for its capacity-achieving attributes, ensures that data can be transmitted reliably even near the channel capacity limit. This encoder and decoder pair excels in providing comprehensive error correction capabilities while accommodating substantial data rates, essential for cutting-edge telecommunication networks and data centers. By implementing sophisticated polar codes, these cores manage to minimize error rates, enhancing overall communication fidelity. With applications spanning from 5G networks to data-intensive server environments, the 100 Gbps Polar Encoder and Decoder is a versatile tool for future-proofing network infrastructure. By utilizing this technology, IPrium combines high throughput with reliable error correction, catering to the evolving demands of modern digital communication frameworks.
The Arria 10 System on Module (SoM) is designed with a focus on embedded and automotive vision applications, leveraging the robust capabilities of the Arria 10 SoC devices. Packed in a compact form factor of 8 cm by 6.5 cm, this module incorporates a multitude of interfaces, offering immense flexibility and a wide array of functionalities suitable for high-performance tasks. This SoM integrates an Altera Arria 10 FPGA with 160 to 480 KLEs along with a Cortex A9 Dual Core CPU, ensuring efficient computational performance. It features a sophisticated power management system and support for dual DDR4 memory interfaces, optimizing power distribution and memory efficiency for safety-critical applications which demand precision and reliability. The Arria 10 SoM is crafted to maximize data throughput, with capabilities such as PCIe Gen3 x8 and 10/40 GBit/s Ethernet interfaces, alongside dedicated clocking arrangements for minimized jitter. Supporting high-speed data transmissions via multiple LVDS lanes and USB interfaces, it's engineered to handle demanding operations in sophisticated systems requiring rapid processing speeds and expansive interfacing.
Algo-Logic's FPGA Tick-To-Trade platform focuses on optimizing the critical path in high-frequency trading by incorporating trading algorithms into FPGA-based systems for rapid execution. The solution significantly enhances the performance of order management systems by reducing the time between receiving and executing trading data, termed as 'Tick-To-Trade.' This reduction in latency is especially beneficial for proprietary trading firms and market makers who thrive on the speed of trade execution. This platform capitalizes on the speed advantage inherent in FPGA technology, combined with Algo-Logic’s proprietary logic designs aimed at providing deterministic performance. By minimizing variables such as jitter and latency, the Tick-To-Trade solution ensures that trading algorithms can execute trades as quickly as the market environment allows. Supported across multiple FPGA platforms from industry giants like Cisco and Xilinx, Algo-Logic’s solution integrates seamlessly into existing infrastructures, allowing clients to leverage ultra-low latency networking capabilities without overhauling their current systems. The emphasis on adaptability and robustness makes it a preferred choice for institutions investing in high-frequency trading architectures.
Polar Encoders/Decoders from Creonic are designed with the latest communication standards in mind, delivering exceptional performance in error correction through polar coding techniques. Originally developed for 5G systems, polar coding offers strong error correction capabilities with high efficiency, making these cores critical for next-generation communication systems. These encoders/decoders provide a consistent performance boost by efficiently utilizing channel capacity, which is particularly beneficial in high-throughput scenarios such as wireless backhaul and cellular networks. Creonic’s implementation focuses on minimizing complexity while maximizing speed, ensuring the cores can handle demanding communication tasks without excessive processing overhead. The Polar Encoders/Decoders IP cores are packed with a rich set of features that include adjustable code rates and length, providing adaptability to various requirements. With comprehensive support for both FPGA and ASIC deployments, they offer a robust, flexible solution for those looking to enhance their existing digital communication frameworks.
The SafeIP™ TriplePHY is a versatile communication technology structured to propel industrial safety into the future. Offering advanced safety features for IEEE 802.3 communications, this product is developed for sectors that require impeccable operational safety, such as drone technology, rail, and automated industrial processes. With seamless failover capabilities, it ensures that safety-critical systems remain operational even in the event of a primary system failure. Built on the robust GlobalFoundries 22FDX platform, SafeIP™ TriplePHY delivers superior performance with minimized power usage and high computational efficiency. This makes it particularly suited for new-generation communication systems requiring minimal signal latency and high data throughput without sacrificing energy management. Siliconally's innovations elevate the TriplePHY, integrating patented features that facilitate rapid error detection and response time management, key factors in enhancing industrial process safety and reliability. With its distinct engineering and unmatched safety protocols, it caters to a broad spectrum of industrial applications, promising improved risk mitigation and operational continuity under varied conditions.
Turbo Encoders/Decoders by Creonic represent key components for achieving effective forward error correction in communication systems. Utilizing turbo coding, these IP cores enhance data throughput by rapidly encoding and decoding signals, ensuring minimal error propagation and optimal data integrity. Widely used in standards like DVB-RCS2 and LTE, Turbo coding provides excellent performance gains in error correction. These cores are specifically designed to handle large volumes of data with high efficiency, allowing technologies like 4G and upcoming 5G networks to deliver their promised speeds reliably. Creonic’s Turbo Encoders/Decoders support a range of code rates, making them adaptable for various transmission conditions and enabling dynamic applications across different communication landscapes. Importantly, they incorporate advanced algorithmic techniques to accelerate processing speeds and reduce latency – essential qualities for real-time applications. Supported with a suite of testing environments and simulation models, these IP cores ensure straightforward integration into user hardware, providing considerable flexibility for both FPGA and ASIC implementation scenarios.
The 10G TCP Offload Engine + MAC + PCIe + Host IF Ultra-Low Latency from Intilop is a state-of-the-art solution designed to empower networking systems with incredible speeds and lower latencies. This product integrates a TCP Offload Engine (TOE) with a Media Access Control (MAC) interface and PCI Express (PCIe) connectivity, offering ultra-low latency performance. It features advanced technologies that diminish the CPU's workload by handling TCP/IP networking tasks, which traditionally would require significant processing capacity from the host system. This allows the system's CPU to focus on executing application tasks, thus optimizing the overall system performance. With its ultra-low latency capability, this engine is ideal for applications requiring rapid data processing and transmission, such as financial trading platforms and sophisticated cloud computing solutions. The component achieves these remarkable feats by offloading the full TCP stack implementation from the host CPU, ensuring seamless data throughput at high speeds while maintaining data integrity and session stability.
The 60GHz Wireless Solution by CLOP Technologies employs the IEEE 802.11ad WiFi standard, also known as the Wireless Gigabit Alliance MAC/PHY specification, to deliver high-speed data transfer. With peak data rates reaching up to 4.6Gbps, it is perfect for complex applications like real-time, uncompressed HD video streaming and high-speed file transfer, improving today’s WiFi speeds tenfold. A key feature of this technology is its support for 802.11ad IP networking, facilitating IP-based tasks such as peer-to-peer communication and router/access point functionalities. It also includes a USB 3.0 host interface for easy connection to hosts and compensates for RF impairments, ensuring robust performance even at high data operations. This product is engineered to handle the substantial data demands of modern IoT devices and provide a competitive advantage through its enhanced wireless data technology. Functioning in the 57GHz to 66GHz frequency band, it uses modulation modes like BPSK, QPSK, and 16QAM. Its FEC coding rates include LDPC 1/2, 5/8, 3/4, and 13/16, with AES-128 hardware security and IEEE 802.11e Real Time QoS to ensure a quality, secured wireless experience.
The 8b/10 Decoder by Roa Logic is a comprehensive implementation of the 8b10b encoding scheme devised by Widmer and Franaszek. It efficiently detects special comma sequences and automatically recognizes K28.5, ensuring reliable data transmission by mitigating transmission discrepancies and bit errors within digital communication systems.
ArrayNav is an innovative GNSS solution that employs multiple antennas, enhancing sensitivity and accuracy to combat common issues like multipath interference and signal jamming. This technology is designed to increase the effectiveness of global positioning systems by using adaptive antenna systems, a concept borrowed from advanced wireless communications. ArrayNav provides up to 18dB gain in signal strength for fading channels and ensures robust performance even in complex environments like urban canyons. By identifying and nulling unwanted signals, it maintains the integrity of GNSS operations against spoofing and interference. This technology is vital for applications needing high precision under challenging signal conditions. With its sophisticated antenna diversity, ArrayNav is crafted to deliver sub-meter precision and swift signal acquisition. This makes it a valuable component for navigation in densely constructed urban landscapes or covered environments where satellite visibility might be obscured. ArrayNav's capability to handle multipath and interference issues effectively makes it a preferred choice for high-reliability navigation systems, contributing to both enhanced security and accuracy.
The BCH Error Correcting Code ECC is crafted to provide paramount error correction capabilities, ideal for applications demanding high data fidelity and error resilience. This code is quintessentially designed to operate asynchronously with zero latency, optimized for minimal power use and gate count. It eliminates the necessity for synchronous logic by adopting a purely combinatorial gate-driven process. The BCH Code supports a variety of environments through configurable parameters, such as symbol size and error symbol corrigibility, thereby offering a flexible use-case across multiple domains. This IP is particularly beneficial in high-performance computing and communication systems, ensuring data integrity in storage devices like SSD controllers and high-speed interface applications. Its capacity to handle several error types without requiring sequential logic resources enhances its applicability in modern integrated circuits, where space and power constraints are pivotal.
The Cortus NB-IoT C200 is a sophisticated narrowband-IoT solution integrated with Bluetooth Low Energy capabilities, designed to meet the needs of smart IoT systems. This IP enables seamless connectivity in sub-GHz unlicensed ISM bands, offering robust performance for remote and wireless communication. Ideally suited for smart metering and industrial IoT applications, this IP delivers reliable, low-power wireless connectivity essential for long-distance communication without sacrificing battery life. Built with the latest advancements in wireless technology, the NB-IoT C200 provides comprehensive support for various IoT standards, ensuring broad compatibility and adoption across multiple platforms. Its low-data-rate, extensive coverage, and reduced power consumption features make it an optimal choice for portable devices and remote sensors that rely on uninterrupted connections. With its capacity to handle significant data processing at reduced bandwidths, the NB-IoT C200 is in line with the demands of modern IoT ecosystems. This model is particularly adept at maintaining efficient operations in dense urban environments, thanks to its noise-immune and highly stable connection protocols.
The ePHY-11207 stands out as a high-capacity communication solution, specifically tailored to support expansive data throughput and advanced processing capabilities. This SerDes solution is ideal for applications requiring 1Gbps to 112Gbps data transmission rates, crafted using a 7nm process node, fostering exceptional performance amid exponential data growth demands. Developed for comprehensive reach and reliability, the ePHY-11207 employs advanced DSP techniques to fortify its data handling and minimize bit error rates, significantly improving performance in environments like data centers, and optical and AI applications. This capability also includes facilitating direct optical data drives, anchoring its utility in settings where seamless, high-speed communication is paramount. The IP integrates robust clock data recovery and adaptable protocols facilitating enterprise growth and innovation in 5G and other telecommunication technologies. With a focus on balancing high-torque operations with energy efficiency, the ePHY-11207 supports complex operational demands while maintaining system cost-effectiveness and high throughput suitability.
Designed for efficient low-density parity-check decoding, Mobiveil's 5G NR LDPC Decoder IP implements an optimized version of the Min-Sum algorithm. This design provides flexibility with programmable bit widths and supports early termination features, enhancing decoding speeds. It is particularly adept in 5G communications, allowing for real-time iterative correction and improving overall transmission reliability in high-performance wireless applications.
Rockley's Multi-Channel Silicon Photonic Chipset is designed as a next-generation solution for high-speed data transmission. This sophisticated chipset integrates hybrid III-V DFB lasers and electro-absorption modulators within a silicon photonic framework, providing 4x106 Gb/s 400 GBASE-DR4 data rates. Each channel achieves high modulation amplitude and low TDECQ penalty, delivering compliance with industry standards. This scalability ensures robust performance for data centers and high-bandwidth communication needs. The chipset exemplifies Rockley's expertise in combining optical components to craft preciseness and efficiency suited for heavy data-centric environments.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Time-Triggered Ethernet (TTEthernet) represents a cutting-edge networking solution, engineered for applications requiring deterministic real-time communication. By implementing time scheduling methods, TTEthernet ensures high precision and fault-tolerant communication over Ethernet, catering to the needs of cyber-physical systems across aerospace, automotive, and industrial sectors. The protocol is distinguished by its capability to handle safety and high availability requirements directly at the network level, thus bypassing application layers. This level of assurance is attained through a robust system of redundancy management and fault-tolerant clock synchronization, as standardized in SAE AS6802.\n\nThe protocol promotes a standardized approach to network design, facilitating seamless integration with a wide array of Ethernet components and maintaining compatibility with IEEE 802.3 standards. This feature is crucial for simplifying the complexities of high-availability and fault-tolerant systems. By allowing for precise scheduling and replicated packet transmission, TTEthernet significantly enhances network reliability. In cases of network faults, this feature ensures that communication is maintained without interruption, supporting fail-operational safety systems.\n\nAdditionally, TTEthernet is scalable from smaller networks to expansive systems, maintaining optimal safety, performance, and security levels. The platform's ability to partition traffic classes permits the convergence of different protocols within a single network, enhancing its adaptability and application range. As a result, TTEthernet underpins numerous critical applications by ensuring both real-time responsiveness and robust data handling capabilities, ultimately reducing time-to-market for integrated solutions.
The Advanced Flexibilis Ethernet Controller (AFEC) brings triple-speed Ethernet processing to programmable hardware environments, supporting traditional copper and modern fiber optics connections. This IP block, which functions much like a Network Interface Controller, achieves a significant efficiency by pairing DMA transfer capabilities with both receive and transmit data, thus reducing CPU load efficiently. AFEC incorporates standard MII/GMII interfaces for seamless connectivity to Ethernet PHY devices, facilitating high-speed data transfers without overwhelming moderate-caliber processors. By accommodating features like automatic CRC computation, comprehensive DMA control, and precise time stamping consistent with IEEE 1588 standards, AFEC ensures a cohesive integration into any Ethernet-based infrastructure. The AFEC's high configurability and tested Ethernet capabilities make it an excellent choice for applications spanning from telecommunications to utilities. AFEC's use of FPGA resources is optimized to minimize footprint while maximizing performance, ensuring that hardware constraints do not impede the integration of this powerful controller within complex network topologies.
The Bluetooth Digital Clock - Levo Series is a state-of-the-art timekeeping solution that incorporates Bluetooth technology to ensure precise and reliable synchronization in diverse settings. Designed for seamless connectivity and ease of use, this digital clock series enables hassle-free integration with wireless systems, making it a go-to choice for environments where cabling is impractical or undesirable.\n\nWith a sleek and modern design, the Levo Series brings not only efficiency but also aesthetic appeal to any space. It is engineered to provide accurate time display and synchronization over Bluetooth connections, thereby offering a wireless alternative to traditional clock setups. This series effectively eliminates the complexity of network wiring, contributing to cleaner installations and more flexibility in clock placement.\n\nIdeal for institutions like schools, healthcare facilities, and office buildings, the Bluetooth Digital Clock - Levo Series offers features like easy setup, maintenance-free operation, and compatibility with various Bluetooth-enabled devices. By choosing this product, organizations benefit from a state-of-the-art solution that aligns with modern wireless communication standards, facilitating better time management and system integration.