All IPs > Wireless Communication > Digital Video Broadcast
The Digital Video Broadcast (DVB) semiconductor IP category comprises an array of IP cores specifically tailored to facilitate reliable and efficient video broadcasting over wireless communication networks. As the demand for high-quality video content continues to rise, the need for robust broadcasting solutions that can handle diverse environments and large audiences becomes crucial. Our collection includes IPs that cater to emerging and established digital broadcasting standards, ensuring versatility and compliance with international specifications.
These semiconductor IPs empower developers to integrate advanced video broadcast capabilities into their next-generation wireless communication products, such as set-top boxes, digital televisions, and mobile broadcasting devices. By leveraging state-of-the-art modulation and error correction techniques, our DVB semiconductor IP offerings streamline the delivery of high-definition and standard-definition video content over various frequencies and platforms. This inclusivity is crucial for manufacturers aiming to capture a broad market share across different regions and user bases.
Moreover, our DVB semiconductor IP solutions are designed with scalability and adaptability in mind. They enable easy integration into diverse broadcasting systems, supporting functionalities such as video encoding, multiplexing, and transmission over wireless channels. This adaptability not only shortens the development cycle but also ensures that the products remain future-proof, allowing manufacturers to deliver cutting-edge features to end-users without extensive redesigns.
Whether you are developing a niche video broadcasting application or a mainstream media distribution product, our Digital Video Broadcast semiconductor IPs provide the essential building blocks needed to ensure high performance, reliability, and compatibility. With a focus on innovation and efficiency, these IPs help you meet the stringent requirements of modern wireless broadcast environments, paving the way for the next wave of digital media consumption experiences.
The NaviSoC by ChipCraft is a sophisticated GNSS receiver system integrated with an application processor on a single piece of silicon. Known for its compact design, the NaviSoC provides exceptional performance in terms of precision, reliability, and security, complemented with low power consumption. This well-rounded GNSS solution is customizable to meet diverse application needs, making it suitable for IoT, Lane-level Navigation, UAV, and more. Designed to handle a wide range of GNSS applications, the NaviSoC is well-suited for scenarios that demand high accuracy and efficiency. Its architecture supports applications such as asset tracking, smart agriculture, and time synchronization while maintaining stringent security protocols. The flexibility in its design allows for adaptation and scalability depending on specific user requirements. The NaviSoC continuously aims to advance GNSS technology by delivering a holistic integration of processing capabilities. It stands as a testament to ChipCraft's innovative strides in creating dynamic, high-performance semiconductor solutions that excel in global positioning and navigation. The module's efficiency and adaptability offer a robust foundation for future GNSS system developments.
Imec's Hyperspectral Imaging System leverages its advanced semiconductor technology to push the boundaries of on-chip spectral imaging. Designed for high-performance applications, this imaging system allows for detailed Earth observation and a variety of other uses. The system encompasses unique innovations in sensor technology, enabling a broad spectrum of light capture that extends beyond traditional imaging limits. By merging this with an enhanced imaging processor, the Hyperspectral Imaging System offers even more refined and precise data capture. This system is tailored for industries where precision and reliability are paramount, such as agriculture, mining, and environmental monitoring. Imec has engineered this technology to not only capture visible light but also the infrared spectrum, maximizing the information the device can collect. The compact, efficient setup makes it feasible for integration into broader systems or standalone applications. By ensuring impeccable spectral resolution and operational efficiency, the Hyperspectral Imaging System stands out as a versatile solution for demanding imaging requirements. Imec's continual research and development in this domain ensure that this imaging technology evolves alongside the emergent needs of diversified industries.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The Neuropixels Probe represents a significant breakthrough in the field of neuroscience research, offering unprecedented resolution and data gathering capabilities. Designed by Imec for use in in vivo studies, this probe enables researchers to acquire signals from thousands of neurons simultaneously, providing invaluable insights into brain function and neurology. With its high-density electrode array, the Neuropixels Probe delivers precise neural recordings, capturing a vast range of neuronal activity across different brain regions. This enables a deep and comprehensive understanding of neural pathways and functions, pivotal for advancing neurological and psychiatric research. Imec's world-leading semiconductor expertise ensures the Neuropixels Probe is equipped with the latest advancements in microfabrication technology, making it highly compatible with current laboratory equipment and methods. This innovation facilitates seamless integration with existing setups while opening new vistas for exploration in neuroscience.
The HDR Core is engineered to deliver enhanced dynamic range image processing by amalgamating multiple exposures to preserve image details in both bright and dim environments. It has the ability to support 120dB HDR through the integration of sensors like IMX585 and OV10640, among others. This core applies motion compensation alongside detection algorithms to mitigate ghosting effects in HDR imaging. It operates by effectively combining staggered based, dual conversion gain, and split pixel HDR sensor techniques to achieve realistic image outputs with preserved local contrast. The core adapts through frame-based HDR processing even when used with non-HDR sensors, demonstrating flexibility across various imaging conditions. Tone mapping is utilized within the HDR Core to adjust the high dynamic range image to fit the display capabilities of devices, ensuring color accuracy and local contrast are maintained without introducing noise, even in low light conditions. This makes the core highly valuable in applications where image quality and accuracy are paramount.
Creonic's demodulation IP cores are central to efficient signal processing in communication systems, addressing the needs of both conventional standards like DVB-S2 and more recent versions such as DVB-S2X. These IP cores decode complex modulated signals robustly, ensuring high-rate data transmission accuracy crucial for applications like satellite communications. The demodulators leverage advanced algorithms to adaptively process signals with minimal distortion and noise, thus maintaining data integrity across long distances and varying conditions. Compatibility with multiple digital modulation techniques is a notable feature, making these cores versatile and highly applicable to diverse communication protocols. Testing and validation at multiple levels are conducted to ensure these cores meet the rigorous demands of modern communication environments. Creonic's dedication to quality and innovation is reflected in their demodulation solutions, making them a trusted choice for reliable, high-performance signal processing.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
Lekha Wireless offers a complete suite of WiMAX Software Stacks compliant with the IEEE 802.16e standard, suitable for both Mobile Station (MS) and Base Station (BS) deployment over SDR platforms. These stacks provide critical support for both PHY and MAC layers, available for licensing as platform-independent ANSI C code, or tailored for Intel-based DSP SoCs. The stacks have been implemented in diverse network configurations, interacting fluidly with third-party solutions and having undergone rigorous compatibility and certification processes. They are designed to support a range of applications including rural broadband, smart grid communications, and AeroMACS for airport management systems. By offering flexibility and proven interoperability, the WiMAX stacks facilitate the deployment of networks in challenging environments, ensuring reliable communication in industries like oil and gas and renewable energy. Lekha's extensive experience in WiMAX technology guarantees a high level of support for customers seeking certification and seamless deployment.
Creonic's modulation IP cores are crafted to optimize data transmission through sophisticated signal processing. These cores support various specifications, including DVB-S2X, providing efficient modulation capabilities that enhance signal robustness and transmission reliability, essential for wireless communication technologies. Leveraging state-of-the-art algorithms, these modulation cores ensure effective transformation of digital data into signals that can be accurately transmitted through different media channels. The compatibility with a range of hardware architectures underscores their adaptability, which is further facilitated through comprehensive software and hardware models for seamless integration. As with all Creonic products, the modulation cores are subjected to stringent quality checks to assure performance and compliance with global standards. This dedication to excellence ensures Creonic's modulation cores are an exemplary choice for engineers looking to boost efficiency and integrity in data communication systems.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The CT20603 is an advanced embedded USB2 (eUSB2) repeater from Canova Tech, pivotal for systems requiring high-speed connectivity between modern SoCs and traditional USB devices. Its dual-role capability enables it to function in Host, Peripheral, or Dual Role Repeater modes, facilitating communication with devices that lack native 3.3V support. Engineered for innovation, the CT20603 handles packet forwarding between eDP/eDN and DP/DP interfaces with precise timing, maintaining compliance with eUSB2 and USB2.0 standards. This ensures compatibility and efficient data transfer even with the latest technology nodes, like 5nm and 3nm. This repeater enhances the integration of USB technologies in contemporary electronic systems, providing flexibility and performance without compromising on size or power demands. By supporting eUSB2, the CT20603 becomes essential for developers looking to bridge new and established connectivity paradigms.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.