All IPs > Wireless Communication > Digital Video Broadcast
The Digital Video Broadcast (DVB) semiconductor IP category comprises an array of IP cores specifically tailored to facilitate reliable and efficient video broadcasting over wireless communication networks. As the demand for high-quality video content continues to rise, the need for robust broadcasting solutions that can handle diverse environments and large audiences becomes crucial. Our collection includes IPs that cater to emerging and established digital broadcasting standards, ensuring versatility and compliance with international specifications.
These semiconductor IPs empower developers to integrate advanced video broadcast capabilities into their next-generation wireless communication products, such as set-top boxes, digital televisions, and mobile broadcasting devices. By leveraging state-of-the-art modulation and error correction techniques, our DVB semiconductor IP offerings streamline the delivery of high-definition and standard-definition video content over various frequencies and platforms. This inclusivity is crucial for manufacturers aiming to capture a broad market share across different regions and user bases.
Moreover, our DVB semiconductor IP solutions are designed with scalability and adaptability in mind. They enable easy integration into diverse broadcasting systems, supporting functionalities such as video encoding, multiplexing, and transmission over wireless channels. This adaptability not only shortens the development cycle but also ensures that the products remain future-proof, allowing manufacturers to deliver cutting-edge features to end-users without extensive redesigns.
Whether you are developing a niche video broadcasting application or a mainstream media distribution product, our Digital Video Broadcast semiconductor IPs provide the essential building blocks needed to ensure high performance, reliability, and compatibility. With a focus on innovation and efficiency, these IPs help you meet the stringent requirements of modern wireless broadcast environments, paving the way for the next wave of digital media consumption experiences.
The NaviSoC by ChipCraft is a sophisticated GNSS receiver system integrated with an application processor on a single piece of silicon. Known for its compact design, the NaviSoC provides exceptional performance in terms of precision, reliability, and security, complemented with low power consumption. This well-rounded GNSS solution is customizable to meet diverse application needs, making it suitable for IoT, Lane-level Navigation, UAV, and more. Designed to handle a wide range of GNSS applications, the NaviSoC is well-suited for scenarios that demand high accuracy and efficiency. Its architecture supports applications such as asset tracking, smart agriculture, and time synchronization while maintaining stringent security protocols. The flexibility in its design allows for adaptation and scalability depending on specific user requirements. The NaviSoC continuously aims to advance GNSS technology by delivering a holistic integration of processing capabilities. It stands as a testament to ChipCraft's innovative strides in creating dynamic, high-performance semiconductor solutions that excel in global positioning and navigation. The module's efficiency and adaptability offer a robust foundation for future GNSS system developments.
Wasiela's DVB-S2-LDPC-BCH provides a sophisticated forward error correction system designed for digital video broadcasting applications, particularly suited for satellite transmission. This product combines low-density parity-check (LDPC) codes with Bose Chaudhuri Hocquenghem (BCH) codes to achieve quasi error-free operation, operating effectively close to the Shannon limit.<br><br>The implementation boasts an irregular parity check matrix and layered decoding to increase decoding efficiency. The minimum sum algorithm is utilized for optimal performance with soft decision decoding capabilities that allow for higher error correction. This product also complies with ETSI EN 302 307-1 V1.4.1 standards, ensuring high quality and reliability in digital transmission systems.<br><br>Additional functionalities include a BCH decoder adept at correcting multiple errors per codeword, making this solution an ideal choice for ensuring data integrity in demanding satellite communication conditions. Wasiela offers this IP complete with synthesizeable Verilog code, a system model in Matlab, and thorough documentation, ensuring a smooth integration process for any application.
The Matchstiq™ X40 is a high-performance software-defined radio (SDR) engineered with a low size, weight, and power (SWaP) design. This SDR is optimized for edge computing, particularly suited for artificial intelligence (AI) and machine learning (ML) applications. It integrates a robust RF front end with multi-channel digital transceivers, providing access to frequencies up to 18GHz and a bandwidth of 450MHz. It features a Nvidia Orin NX 16G for advanced data processing and an AMD Zynq Ultrascale+ FPGA for signal integration. The small form factor, with precise dimensions and modest weight, offers advantages in space-constrained deployments such as unmanned aerial systems (UxS) and ALE payloads. The Matchstiq™ X40 facilitates superior performance in frequency agility, ideal for spectrum management and complex signal detection tasks. The SDR's architecture supports numerous interface options including USB 3.0 and 1 GbE networking, complemented by serial port connectivity. This device is designed to leverage the libsidekiq API for seamless API integration, making it an indispensable tool for rapid prototyping, testing, and field deployment.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The Hyperspectral Imaging System from IMEC offers an advanced portable solution for comprehensive spectral analysis. By employing cutting-edge sensor technology combined with powerful optics, it captures a broad spectrum of light. This system is instrumental in industries ranging from agriculture to healthcare. It provides precise imaging capabilities, enabling users to confidently conduct critical assessments such as plant health monitoring, mineral detection, or even advanced medical diagnostics. Hyperspectral technology bridges the gap between large-scale economic efficiency and intricate analysis, paving the way for new applications across fields by offering unprecedented spectral resolution.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Decoder is expertly crafted for decoding tasks in high-speed data networks, particularly those using satellite and broadband wireless communication standards. This 8 state Duobinary Turbo Decoder features an optional 64 state Viterbi decoder, highlighting its capacity for intricate data throughput and error correction. Functional in a multitude of data environments, this decoder can handle a variety of signal paths, ensuring robust data recovery and integrity. Its architecture is especially suited for dynamic network conditions, offering adaptability and reliability-critical factors in maintaining service quality in challenging communication scenarios. This Decoder is ideal for systems operating under diverse protocols, ensuring seamless interoperability and efficient error detection and correction. By optimizing data processing technologies, it supports high-speed data exchanges across broader channels, catering to the growing demand for superior network performance in modern telecommunication infrastructures.
Neuropixels is a groundbreaking fully integrated digital neural probe designed for advanced in vivo neuroscience research in smaller animals. These probes deliver unparalleled precision by capturing detailed electrical signals from the brain, allowing researchers to monitor hundreds of neural activities simultaneously. With its compact design, the Neuropixels probe includes arrays of densely packed electrodes that provide comprehensive insights into neural structures and functions. Favored by neuroscientists globally, Neuropixels promises to unveil complex brain dynamics, thereby enhancing our understanding of neurobiological processes.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Encoder provides a sophisticated solution for broadband wireless access systems. Featuring an 8 state configuration, it ensures robust data encoding processes suited for high-capacity networks. This encoder is pivotal in enhancing error control and efficiency across satellite and wireless communication systems, where maintaining high uptime and performance is vital. This encoder is optimized to integrate with DVB-RCS systems, allowing for standardized communication across varied platforms. Its design not only enhances signal integrity but also supports extensive customizations, accommodating specific project requirements and streamlining deployment processes in complex environments. The turbo encoder is also compatible with IEEE 802.16 WiMAX, making it a versatile choice for companies developing wireless infrastructure. By offering unparalleled data processing speeds and reliability, this encoder plays a critical role in modern telecommunication setups. It leverages cutting-edge technology to minimize latency and maximize throughput, addressing the rigorous demands of cutting-edge wireless networks.
The HDR Core is engineered to deliver enhanced dynamic range image processing by amalgamating multiple exposures to preserve image details in both bright and dim environments. It has the ability to support 120dB HDR through the integration of sensors like IMX585 and OV10640, among others. This core applies motion compensation alongside detection algorithms to mitigate ghosting effects in HDR imaging. It operates by effectively combining staggered based, dual conversion gain, and split pixel HDR sensor techniques to achieve realistic image outputs with preserved local contrast. The core adapts through frame-based HDR processing even when used with non-HDR sensors, demonstrating flexibility across various imaging conditions. Tone mapping is utilized within the HDR Core to adjust the high dynamic range image to fit the display capabilities of devices, ensuring color accuracy and local contrast are maintained without introducing noise, even in low light conditions. This makes the core highly valuable in applications where image quality and accuracy are paramount.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The ISDB-T 1-Segment Tuner by RF Integration is designed for seamless integration into digital television and mobile broadcasting applications. This tuner supports the ISDB-T (Integrated Services Digital Broadcasting - Terrestrial) standard, particularly focusing on the 1-segment broadcasting which is prevalent in mobile TV applications. It provides reliable tuning, demodulating the complex signals required for high-quality digital broadcasts. The product ensures compatibility with a range of ISDB standards, making it a versatile component for global broadcasting systems. Notably, it delivers robust performance even in challenging environments such as moving vehicles or dense urban areas, where signal reception can be difficult. The tuner's architecture is optimized for low power consumption and minimized footprint, which is crucial for portable and handheld device integration. It offers a compelling solution for device manufacturers focused on delivering superior multimedia experiences through mobile platforms, ensuring smooth video quality and uninterrupted service.
Lekha Wireless offers a complete suite of WiMAX Software Stacks compliant with the IEEE 802.16e standard, suitable for both Mobile Station (MS) and Base Station (BS) deployment over SDR platforms. These stacks provide critical support for both PHY and MAC layers, available for licensing as platform-independent ANSI C code, or tailored for Intel-based DSP SoCs. The stacks have been implemented in diverse network configurations, interacting fluidly with third-party solutions and having undergone rigorous compatibility and certification processes. They are designed to support a range of applications including rural broadband, smart grid communications, and AeroMACS for airport management systems. By offering flexibility and proven interoperability, the WiMAX stacks facilitate the deployment of networks in challenging environments, ensuring reliable communication in industries like oil and gas and renewable energy. Lekha's extensive experience in WiMAX technology guarantees a high level of support for customers seeking certification and seamless deployment.
The CT20603 is an advanced embedded USB2 (eUSB2) repeater from Canova Tech, pivotal for systems requiring high-speed connectivity between modern SoCs and traditional USB devices. Its dual-role capability enables it to function in Host, Peripheral, or Dual Role Repeater modes, facilitating communication with devices that lack native 3.3V support. Engineered for innovation, the CT20603 handles packet forwarding between eDP/eDN and DP/DP interfaces with precise timing, maintaining compliance with eUSB2 and USB2.0 standards. This ensures compatibility and efficient data transfer even with the latest technology nodes, like 5nm and 3nm. This repeater enhances the integration of USB technologies in contemporary electronic systems, providing flexibility and performance without compromising on size or power demands. By supporting eUSB2, the CT20603 becomes essential for developers looking to bridge new and established connectivity paradigms.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
Tailored for high-speed data networks, the IEEE 802.16 WiMAX Turbo Decoder operates with an 8 state Duobinary Turbo Decoder design, incorporating 4 parallel MAP decoders. This configuration offers exceptional data processing speeds critical for expansive broadband networks. The decoder is adept at managing complex data environments, adapting to various network conditions and maintaining high performance and minimal error rates. Its capabilities support robust signal recovery and data integrity, essential for modern communication infrastructures. Ideal for broadband wireless applications, this decoder supports high data throughput and efficient error correction, catering to the demanding expectations of today's network architectures. It serves as a pivotal tool for maximizing network capabilities and ensuring consistent service delivery across wide-ranging operating conditions.
The Inmarsat Turbo Decoder is tailored for satellite communication networks, delivering reliable and high-speed data processing capabilities. It leverages a 16 state turbo decoding framework, supporting advanced error correction and data integrity essential for aerospace and satellite communication applications. The decoder includes optional 64 or 256 state Viterbi decoders, further refining data processing accuracy and efficiency. This sophisticated decoding structure supports seamless communication across satellite networks, optimizing data throughput and maintaining service quality. Ideal for use in Inmarsat systems, this decoder provides robust performance under challenging conditions, ensuring sustained data integrity and reliability. It is a vital component for satellite service providers seeking to enhance their communication infrastructure with cutting-edge technology.
The Inmarsat Turbo Encoder is designed for high-speed satellite communication systems, enabling robust data transmission with enhanced error correction capabilities. It operates with a 16 state configuration, which is a significant improvement for achieving reliable communication over long distances. The Turbo Encoder is built to seamlessly integrate with Inmarsat platforms, optimizing for efficiency and performance. The encoder's specialized architecture supports a variety of configurations, making it suitable for applications that require dynamic adaptation to different channel conditions. This flexibility is crucial for maintaining high data integrity and throughput in the ever-changing satellite communication landscape. Furthermore, the encoder's modular design allows for tailored solutions, meeting specific needs of advanced telecommunication infrastructures. In addition to its standard functionalities, the Inmarsat Turbo Encoder can be enhanced with optional features such as pseudo-randomisers and input memory adaptation, which further extends its application range. By focusing on scalability and durability, this encoder provides a competitive edge in the field of satellite communications.
The DVB-S2 LDPC-BCH block is a powerful FEC (Forward Error Correction) subsystem for Digital Video Broadcasting via Satellite. In Digital video broadcasting for digital transmission for satellite applications, a powerful FEC sub-system is needed. FEC is based on LDPC (Low-Density Parity Check) codes concatenated with BCH (Bose Chaudhuri Hocquenghem) codes, allowing Quasi Error Free operation close to the Shannon limit.
The CCSDS Turbo Encoder with Sync Marker offers enhanced encoding capabilities for space communications, featuring a 16 state configuration coupled with a sync marker for improved data synchronization and reliability. This encoder is specially crafted for aerospace applications where precise data transmission is paramount. Beyond its core functionality, the encoder includes optional features like a pseudo-randomiser and input memory, augmenting its adaptability across diverse satellite and space-based systems. This ensures that communication remains robust and error-free, even under challenging extraterritorial conditions. A critical element in satellite communications, the CCSDS Turbo Encoder with Sync Marker supports the stringent requirements of space missions, providing high-quality encoding solutions that ensure data streams remain undisturbed and accurately synchronized throughout transmission.
The CCSDS Turbo Encoder is designed for use in space communication systems, providing a 16 state encoding solution that enhances data integrity and transmission reliability critical in space-based operations. This encoder incorporates a compact and efficient architecture, tailored to the demanding requirements of satellite communication environments. It supports advanced data correction and synchronization, ensuring that data remains intact even over vast distances. The optional pseudo-randomiser and input memory feature further improve encoding efficiencies, making the CCSDS Turbo Encoder a versatile solution for satellite operators. Ideal for deployment in CCSDS communication systems, this encoder is a crucial component for achieving reliable satellite communication, characterized by high-performance data encoding and reduced error rates. It enables satellite services to operate seamlessly while maintaining superior communication quality.