All IPs > Wireless Communication > 802.16 / WiMAX
The 802.16/WiMAX category in our semiconductor IP catalog offers cutting-edge solutions tailored for robust wireless communication. WiMAX (Worldwide Interoperability for Microwave Access) is a technology based on the IEEE 802.16 standard designed to provide high-speed broadband access over a large area. Semiconductor IPs in this category are essential for developing systems that need to ensure reliable, high-bandwidth connectivity, making them ideal for both urban and rural settings where traditional broadband may not reach.
802.16/WiMAX semiconductor IPs are instrumental in the creation of efficient and scalable networks. They facilitate the transmission of data over long distances without the need for physical cabling, which is particularly advantageous in regions with challenging terrain or sparse infrastructure. This technology supports a range of applications including mobile backhaul, fixed wireless access, and even vehicular network connectivity. Products in this category include baseband processors, radio frequency transceivers, and complete system-on-chip (SoC) solutions that ensure seamless integration with existing communication frameworks.
Developing 802.16/WiMAX solutions involves adopting advanced modulation technologies and multiple input multiple output (MIMO) capabilities, which help in maximizing throughput and spectrum efficiency. The semiconductor IPs available in this category are designed to meet industry standards for performance and reliability, thereby enabling manufacturers to create devices that deliver consistent service quality in various environmental conditions. These IPs are crucial for companies aiming to broaden their market reach by providing high-speed internet access to underserved and unconnected areas globally.
In summary, the 802.16/WiMAX semiconductor IPs category is a vital component for developers looking to harness the potential of broadband wireless technology. By integrating these IPs into their products, companies can offer scalable and efficient connectivity solutions that cater to a wide array of use cases. Whether it's for urban connectivity improvement or expanding access in remote locations, the solutions offered in this category are key to overcoming the digital divide and driving future innovations in wireless technology.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The Ncore Cache Coherent Interconnect is designed to address the challenges of multicore ASICs by ensuring efficient inter-core communication and synchronization within SoCs. It provides a high-bandwidth interconnect fabric, supporting multiple protocols and a range of processor designs, including Arm and RISC-V architectures. This coherent interconnect leverages system scalability and integration ease, meeting the rigorous demands of safety-critical environments like those in automotive applications. Ncore is engineered to reduce complexity and optimize power usage while maintaining high-performance standards, ultimately enhancing reliability in complex multi-core system designs.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
TurboConcept's TC1000/2000/3000 series is an array of meticulously designed LDPC and Turbo Product codes intended to enhance data communication systems with superior error correction capabilities. These IP cores are engineered to support high throughput and low latency, crucial for advanced data communication applications. The series is versatile and accommodates a wide range of coding options, offering flexibility and adaptability in different technological environments. It is highly effective for use in applications ranging from broadband wireless to satellite communications, where data integrity and performance consistency are paramount. The inherent flexibility in their implementation allows easy adaptation to the evolving demands of digital communication networks.
The 5G LDPC IP core from TurboConcept is engineered to meet the stringent demands of modern wireless communications. It provides robust error correction capabilities pivotal for next-generation 5G networks. This IP core is crafted to handle the increased data bandwidth of 5G, ensuring reliable and efficient data transmission. It is tailored for 5G NR (New Radio) systems, delivering enhanced spectral efficiency and higher throughput. With its advanced implementation for both FPGA and ASIC, the 5G LDPC core supports rapid error correction which is critical for maintaining high data rates and low latency in various communication environments.
TurboConcept's 4G multi-mode CTC decoder is a versatile IP core designed to meet the broad requirements of 4G mobile networks. It expertly handles various code rates and block sizes, making it a flexible solution for communication systems that demand reliable error correction under multiple modulation schemes. The decoder’s architecture supports high-speed data processing, essential for the fast-paced operations typical in 4G environments. Additionally, it is equipped to provide seamless transition and compatibility with legacy systems, ensuring network consistency and reliability.
TurboConcept's 5G Polar encoder/decoder core serves as a cornerstone for secure and reliable communication in 5G networks. This IP solution plays a crucial role in data transmission security, employing polar coding techniques known for their capacity-approaching error correction performance. The 5G Polar core is optimized for use in 5G NR systems, offering superior performance in handling varying channel conditions. By providing robust performance under adverse conditions, it ensures that data integrity is maintained without sacrificing speed or efficiency. Designed for both FPGA and ASIC platforms, it guarantees flexibility in deployment, catering to diverse hardware requirements.
The transceiver is designed to be used together with an RF tuner, and ADC/DAC converters. The system has internal state machine to control the operation, and can be externally configured via the SPI interface. This design is a Mobile WiMAX baseband transceiver core for both Base station and Mobile station, supplied as a portable and synthesizable Verilog-2001 IP. The system was designed to be used in conjunction with a standard RF tuner. The operation of the transceiver is automated by a master finite state machine.
Designed for comprehensive adherence to IEEE 802.16e standards, Wasiela's PHY Transceivers integrate seamlessly with RF tuners, leveraging internal state machines to control diverse signal processing tasks. These transceivers are crafted for robust performance in complex network environments, supporting essential wireless connectivity applications.
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