All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
CoreVCO is a high-performance, radiation-hardened VCO solution offering excellent phase noise characteristics. Engineered for demanding environments such as space and military applications, CoreVCO includes dual VCOs with wide frequency coverage ranging from 0.7 to 6.6 GHz. Its robust design ensures stability and reliability in high-radiation settings. CoreVCO's architecture integrates unique SiGe technology, providing superb intrinsic noise resistance and wide frequency fidelity. The solution is characterized by an integrated bandgap reference, LDOs, and a smart output power adjustment feature, enhancing its usability in various applications. This VCO solution supports digital calibration to counter process and temperature variations, demonstrating adaptive performance across a range of temperature and voltage conditions. CoreVCO is packaged compactly, making it a valuable component in compact designs needing efficient frequency synthesis.
ADAS and Autonomous Driving technology by KPIT focuses on advancing L3+ autonomy, providing scalable and safe autonomous mobility solutions. This technology addresses fundamental challenges such as consumer safety, localized infrastructure dependencies, and comprehensive validation approaches. With the ever-evolving landscape of autonomous driving, ensuring robust AI solutions beyond mere perception is crucial for elevating autonomy levels in vehicles. By integrating innovative technology and adhering to regulatory standards, KPIT empowers automakers to offer safe and reliable autonomous vehicles that meet consumer trust and performance expectations.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The NaviSoC by ChipCraft is a sophisticated GNSS receiver system integrated with an application processor on a single piece of silicon. Known for its compact design, the NaviSoC provides exceptional performance in terms of precision, reliability, and security, complemented with low power consumption. This well-rounded GNSS solution is customizable to meet diverse application needs, making it suitable for IoT, Lane-level Navigation, UAV, and more. Designed to handle a wide range of GNSS applications, the NaviSoC is well-suited for scenarios that demand high accuracy and efficiency. Its architecture supports applications such as asset tracking, smart agriculture, and time synchronization while maintaining stringent security protocols. The flexibility in its design allows for adaptation and scalability depending on specific user requirements. The NaviSoC continuously aims to advance GNSS technology by delivering a holistic integration of processing capabilities. It stands as a testament to ChipCraft's innovative strides in creating dynamic, high-performance semiconductor solutions that excel in global positioning and navigation. The module's efficiency and adaptability offer a robust foundation for future GNSS system developments.
The ORC3990 is a sophisticated System on Chip (SoC) solution designed for low-power sensor-to-satellite communication within the LEO satellite spectrum. Utilizing Totum's DMSS technology, it achieves superior doppler performance, facilitating robust connectivity for IoT devices. The integration of an RF transceiver, power amplifiers, ARM CPUs, and memory components makes it a highly versatile module. Leveraging advanced power management technology, this SoC supports a battery life that exceeds ten years, even within industrial temperature ranges from -40 to +85°C. It's optimized for usage with Totum's global LEO satellite network, ensuring substantial indoor signal coverage without the need for additional GNSS components. Efficiency is a key feature, with the chip operating in the 2.4 GHz ISM band, providing unparalleled connectivity regardless of location. Compact in design, comparable in size to a business card, and designed for easy mounting, the ORC3990 offers sought-after versatility for IoT applications. The ability to function with excellent TCO in terms of cost compared to terrestrial IoT solutions makes it a valuable asset for any IoT deployment focused on sustainability and longevity.
The Automotive AI Inference SoC by Cortus is a cutting-edge chip designed to revolutionize image processing and artificial intelligence applications in advanced driver-assistance systems (ADAS). Leveraging RISC-V expertise, this SoC is engineered for low power and high performance, particularly suited to the rigorous demands of autonomous driving and smart city infrastructures. Built to support Level 2 to Level 4 autonomous driving standards, this AI Inference SoC features powerful processing capabilities, enabling complex image processing algorithms akin to those used in advanced visual recognition tasks. Designed for mid to high-end automotive markets, it offers adaptability and precision, key to enhancing the safety and efficiency of driver support systems. The chip's architecture allows it to handle a tremendous amount of data throughput, crucial for real-time decision-making required in dynamic automotive environments. With its advanced processing efficiency and low power consumption, the Automotive AI Inference SoC stands as a pivotal component in the evolution of intelligent transportation systems.
Creonic offers a diverse array of miscellaneous FEC (Forward Error Correction) and DSP (Digital Signal Processing) IP cores, catering to various telecommunications and broadcast standards. This collection of IP cores includes highly specialized solutions like ultrafast BCH decoders and FFT/IFFT processors, which are critical for managing high-throughput data streams and maintaining signal fidelity. These IP cores embody the latest in processing technology, delivering precise error correction and signal transformation functions that are essential in complex communication networks. Their integration capabilities are made easy with detailed hardware specifications and software models, designed for flexibility across different platforms and applications. The rigorous development process guarantees that each core adheres to market standards, optimizing performance and ensuring operational reliability. Creonic's portfolio of miscellaneous FEC and DSP cores stands out for its innovative contributions to digital communications, providing unique solutions that meet the sophisticated requirements of modern connectivity.
The 802.11 LDPC solution by Wasiela is designed to offer high throughput with on-the-fly frame-to-frame configuration. It allows for flexible LDPC decoding iterations, balancing throughput with error correction performance according to specific requirements. This ensures optimal bit-error-rate and packet-error-rate performance, crucial for maintaining the integrity of wireless communications. With specifications aligning perfectly with industry standards, this product is vital for delivering reliable and efficient connectivity.
The CANmodule-IIIx is an enhanced version of the traditional CAN controller, featuring an extensive set of 32 receive and 32 transmit buffers. This setup is particularly beneficial for applications demanding high-capacity data management and robust error handling. The module’s structure supports mailboxes with a prioritized arbitration mechanism, offering flexibility for advanced application-specific configurations.<br/><br/>Compliant with the CAN 2.0A/B standards and designed in an HDL that is adaptable to both FPGA and ASIC technologies, the CANmodule-IIIx includes on-chip SRAM to facilitate efficient data handling. It integrates seamlessly into ARM-based SoCs through its AMBA 3 Advanced Peripheral Bus, providing a high-performance, fully synchronous system interface.<br/><br/>Key features include single-shot transmissions, automatic RTR interrupt handling, and sophisticated message filtering capabilities that encompass ID, IDE, RTR, and initial data bytes. Outstanding for areas like aerospace and industrial automation, the CANmodule-IIIx ensures data integrity and responsiveness via its programmable interrupt controller and comprehensive test modes.
The eSi-Comms IP offers parameterizable and configurable solutions for modern air interface standards, such as Wi-Fi, LTE, and DVB. It features advanced DSP algorithms for synchronization, equalization, and modulation, thereby enhancing the robustness of communication links. Suitable for wireless sensor networks, remote metering, and broadcast applications, eSi-Comms delivers efficient transceiver designs optimized for power and area. Supported by C, SystemC, CUDA, and MATLAB libraries, it facilitates swift development and integration into existing systems, ensuring a reduced time-to-market and minimized risk.
This ISM Band RF IP provides a comprehensive solution designed for integration into BLE applications, offering a robust platform with GF 22FDX process node capabilities. Its components include an advanced RF transceiver and digital power amplifier, achieving a peak power output of +23 dBm. The IP optimizes signal strength and minimizes space requirements with an integrated balun and matching network. Designed for versatility, the ISM Band RF IP is adaptable across different process nodes, making it a flexible choice for customers seeking to develop sophisticated RF ICs. The transceiver is in line with modern communication standards and is particularly useful for applications in low-power communication environments. This flexibility allows for the development of cost-effective, high-performing merchant market ICs. Orca Systems ensures that their IP can be efficiently licensed and integrated into various systems, promoting a streamlined and effective path to market for BLE developers. The focus on reduced power consumption and enhanced signal capabilities underscores the value of this IP in expanding and enhancing wireless communication methodologies.
Creonic's Turbo encoders and decoders provide powerful forward error correction techniques applicable in wireless communication systems, including 4G LTE and DVB-RCS2. Known for the efficiency in managing bandwidth and minimizing data loss, these IP cores are designed to boost communication integrity and performance. Leveraging sophisticated iterative algorithms, Turbo encoders and decoders execute precise error detection and correction with high data throughput. They are crafted to integrate seamlessly into various hardware platforms, with detailed hardware models and software reference models available for easy incorporation into any system. This versatility ensures that Creonic's Turbo solutions are suitable for both new and existing infrastructures. Quality assurance remains a cornerstone for these products, with each IP core undergoing extensive validation to meet demanding specifications. By addressing critical needs in modern communication systems, Creonic’s Turbo offerings continue to be a preferred choice for engineers and developers striving for reliability and efficiency.
The CANmodule-III is a sophisticated controller core that introduces a mailbox approach to CAN data handling. Conforming to the ISO 11898-1 standard, it boasts 16 receive buffers, each with a dedicated message filter, and 8 transmit buffers, featuring a prioritization system. This structure caters to advanced higher-layer protocols, making it ideal for applications requiring nuanced data management such as those in industrial automation or automotive communications.<br/><br/>Designed in a technology-independent HDL, it is compatible with both FPGA and ASIC platforms, leveraging on-chip SRAM for optimized performance. The integration with ARM-based SoC environments is facilitated by an AMBA 3 Advanced Peripheral Bus interface. This fully synchronous zero wait-state bus interface supports seamless connections to other system buses, thus enabling high throughput and low latency communications.<br/><br/>The CANmodule-III's robust architecture includes features like single-shot transmission, automatic RTR response management, and a comprehensive error capture system. The full suite of debugging capabilities includes loops and listen-only mode, ensuring that developers can maintain control over communication channels throughout the product lifecycle.
The TW330 IP offers cutting-edge image warping capabilities through GPU technologies, designed to transform and correct image distortions in real-time. This technology is tailored for high-resolution outputs, supporting resolutions up to 16K x 16K. It is ideal for applications such as head-up displays in automotive systems, VR/AR devices, and projectors, providing accurate image processing for demanding visual environments.
The XCM_64X64_A provides a sophisticated architecture featuring 128 ADC 2-bit 1GSps with VGA front ends, designed for cross-correlation applications in NASA projects. Utilizing 45nm IBM SOI CMOS technology, it achieves ultra-low power consumption of approximately 0.5W for the entire array. The structure is geared towards synthetic radar receivers, radiometers, and spectrometers, operating at bandwidths from 10MHz to 500MHz. It integrates seamlessly into systems requiring precise data acquisition and processing, ideal for advanced research and observational instruments. With a focus on low power and high data throughput, the XCM_64X64_A addresses the challenges faced in high-energy physics and observational technology arenas. Its efficient power usage and robust design ensure long-term performance and reliability in demanding applications.
Polar encoders and decoders by Creonic serve as vital components in enhancing data integrity for next-generation communication frameworks such as 5G. These IP cores are designed to deliver superior coding efficiency and robust performance in varied network conditions, supporting high-speed data transmissions while maintaining low latency. The technology stands out for its innovative use of polar codes, noted for their capacity to achieve channel capacities effectively. Creonic's Polar solutions include hardware and software models tailored for straightforward integration into diverse computational environments. They provide excellent adaptability and scalability across multiple hardware systems, making them ideal for cutting-edge digital communication networks. Backing their robust technological framework, Creonic ensures that each product adheres to strict industry standards through comprehensive testing and quality assurance. The result is a set of highly reliable Polar encoders and decoders designed to enhance the performance and efficiency of advanced communication systems.
The CANmodule-IIx is a FIFO-based CAN controller designed for streamlined integration within FPGA and ASIC systems. This IP core complies fully with the CAN 2.0A/B standard and supports ISO 11898-1 compliance, making it a reliable choice for various communication needs in automotive and industrial applications.<br/><br/>Incorporating advanced message filtering, the CANmodule-IIx is equipped with three fully programmable filters, alongside a 32-message receive FIFO and a 16-message transmit FIFO. This allows the module to efficiently process and prioritize a wide range of messages, bolstered by a high-priority transmit buffer that can bypass the traditional FIFO path for critical communications.<br/><br/>Integration into ARM-based SoCs is facilitated via its AMBA APB interface, allowing seamless connectivity within complex system architectures. The CANmodule-IIx's design supports testing and debugging capabilities, including loopback modes and a dedicated SRAM-based message buffer, ensuring reliability and ease of use across its deployment.
The 5G NR LDPC Decoder from Mobiveil provides advanced error correction capabilities vital for the next generation of wireless communications. Utilizing the Min-Sum algorithm, it offers programmable bit width options and an iteration termination feature based on a concurrent parity check engine. It efficiently manages redundant transmissions, enhancing performance specifically for 5G applications.
The XCM_64X64 represents a complete cross-correlator solution with 64x64 channels, designed to cater to NASA's high-end synthetic radar receivers. Executed using IBM's 45nm SOI CMOS technology, this correlator emphasizes energy efficiency with a total power consumption of approximately 1.5W. It is engineered to support advanced radiometric and spectroscopic applications, with bandwidth capabilities ranging from 10MHz to 500MHz. The array's infrastructure supports precise signal analyses, making it ideal for use in scientific and exploratory sectors. Designed for optimum power-to-performance ratios, the XCM_64X64 excels in environments that demand high data integrity and reliable processing under stringent operational conditions. It is a vital component for synthetic aperture radar systems and other complex observational tools.
The mmWave PLL by CoreHW is an advanced phase-locked loop suited for high-frequency applications ranging from 19 GHz to 81 GHz. This technology serves critical functions in modern wireless communication networks and radar systems, with applications spanning from 5G transceivers to automotive radar solutions. CoreHW's mmWave PLL features integrated frequency multipliers converting VCO output into radar frequency bands. With a chirp bandwidth of 1 GHz at VCO and scalable options, it's designed for enhanced precision in frequency synthesis and minimal noise output, crucial for broadband systems. Built for versatility, the PLL incorporates an integrated bandgap, LDOs, and digital calibration for process variations. This results in a robust PLL solution that addresses the complex demands of wireless infrastructure and mobile communications, ensuring reliable signal integrity and performance across diverse environments.
The LTE Lite solution is a versatile PHY product tailored to support a wide range of channel bandwidths and modulation schemes. Compliant with CAT 0/1 PHY specifications, it offers features such as IF input support, time tracking, and frequency correction for enhanced communication clarity and reliability. Designed for synthesizable Verilog-2001, the system integrates easily with external tuners and ADCs, making it a foundational component in efficient LTE communication setups.
The Cortus NB-IoT C200 is a sophisticated narrowband-IoT solution integrated with Bluetooth Low Energy capabilities, designed to meet the needs of smart IoT systems. This IP enables seamless connectivity in sub-GHz unlicensed ISM bands, offering robust performance for remote and wireless communication. Ideally suited for smart metering and industrial IoT applications, this IP delivers reliable, low-power wireless connectivity essential for long-distance communication without sacrificing battery life. Built with the latest advancements in wireless technology, the NB-IoT C200 provides comprehensive support for various IoT standards, ensuring broad compatibility and adoption across multiple platforms. Its low-data-rate, extensive coverage, and reduced power consumption features make it an optimal choice for portable devices and remote sensors that rely on uninterrupted connections. With its capacity to handle significant data processing at reduced bandwidths, the NB-IoT C200 is in line with the demands of modern IoT ecosystems. This model is particularly adept at maintaining efficient operations in dense urban environments, thanks to its noise-immune and highly stable connection protocols.
RF Integration's 802.11 Transceiver Core is engineered to provide high efficiency and performance for wireless communication applications. It supports various 802.11 standards, allowing for versatile integration into modern wireless network environments. This transceiver core is designed to facilitate seamless connectivity and data transfer, crucial for enabling robust Wi-Fi communication. The core incorporates sophisticated signal modulation and demodulation techniques to ensure optimal wireless performance. It is crafted to operate effectively across multiple bands, providing high data throughput and expanded wireless range. By integrating this core, devices can achieve reliable wireless connectivity, making it an ideal choice for consumer electronics, mobile devices, and other networked systems. Advanced power management features are embedded within the core's design, aimed at minimizing energy consumption and extending device battery life. Such efficiency makes it particularly suited for portable and mobile communications technology, highlighting its role in enhancing the user experience for connected wireless environments.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
AccelerComm's Software-Defined High PHY is an adaptable O-RAN solution, optimized for the ARM processor architecture. This High PHY solution can operate with or without hardware acceleration, tailored to meet various capacity and power specifications. Developed to complement ASIC/SoC products, it supports a wide range of platforms, enhancing performance flexibility and integration simplicity. This solution is particularly beneficial in environments where dynamic computing capabilities are required and is pivotal in ensuring effective network scaling and performance delivery.
The RWM6050 Baseband Modem represents a leap in cost-effectiveness and power efficiency for applications requiring high bandwidth and capacity in mmWave technology. Designed in partnership with Renesas, this modem can effectively pair with mmWave RF chipsets to fulfill various access and backhaul market needs. With a flexible channel structure and modulation coding, it ensures scalability for multi-gigabit data transmission. The modem's platform is designed for high configurability, and includes subsystems for beamforming and digital signal processing. It stands out for its real-time programmable scheduler and integrated network synchronization, boosting throughput for numerous demanding applications. The RWM6050 combines power with efficiency, facilitating seamless and substantial data flow over several hundred meters with dual modem support providing redundancy and resilience.
Great River Technology's HOTLink II Product Suite is designed to support high-speed serial communication applications. This suite focuses on enabling reliable and efficient data transmission across various mission-critical platforms. It leverages technologies well-suited for environments demanding robustness and precision, such as infrared sensors and optical camera systems. The HOTLink II suite aids engineers in interfacing and implementing solutions that require high-throughput and low-latency performance characteristics. This suite, continuing to support existing FC-AV applications, ensures these systems can handle new challenges in fast-paced aerospace and defense sectors. The suite’s design tools and components are optimized for seamless integration into existing systems, facilitating the transition from legacy to cutting-edge technologies.
Imec's Hyperspectral Imaging System leverages its advanced semiconductor technology to push the boundaries of on-chip spectral imaging. Designed for high-performance applications, this imaging system allows for detailed Earth observation and a variety of other uses. The system encompasses unique innovations in sensor technology, enabling a broad spectrum of light capture that extends beyond traditional imaging limits. By merging this with an enhanced imaging processor, the Hyperspectral Imaging System offers even more refined and precise data capture. This system is tailored for industries where precision and reliability are paramount, such as agriculture, mining, and environmental monitoring. Imec has engineered this technology to not only capture visible light but also the infrared spectrum, maximizing the information the device can collect. The compact, efficient setup makes it feasible for integration into broader systems or standalone applications. By ensuring impeccable spectral resolution and operational efficiency, the Hyperspectral Imaging System stands out as a versatile solution for demanding imaging requirements. Imec's continual research and development in this domain ensure that this imaging technology evolves alongside the emergent needs of diversified industries.
LDPC (Low-Density Parity-Check) encoders and decoders from Creonic are designed to enhance data transmission reliability in complex communication systems. These IP cores support various standards, including DVB-S2X, 5G-NR, and IEEE 802.11, offering exceptional error correction capabilities essential for high-speed data transfer. Utilizing advanced algorithms, Creonic's LDPC solutions deliver robust performance while minimizing complexity and power consumption. The LDPC encoders and decoders embody state-of-the-art hardware models and bit-accurate software reference models for seamless integration into existing systems. The hardware models are compatible with FPGA platforms from leading manufacturers, ensuring adaptability across different technological environments. Comprehensive test environments accompany the IP cores, facilitating smooth deployment and validation. Creonic’s commitment to quality is evident in the rigorous testing processes each IP core undergoes, guaranteeing compliance with stringent industry standards. The LDPC solutions are available for download from secured servers, reflecting Creonic's focus on security and accessibility for their global clientele.
The TW220/240 IP enables efficient distortion correction, scaling, and rotation for image processing applications, geared for embedded systems needing robust transformation capabilities. It supports outputs up to 4K x 4K resolutions, optimizing image quality for video outputs across cameras and automotive systems. This solution is perfect for applications requiring real-time image adaptations.
The VoSPI Rx for FLIR Lepton IR Sensor by BitSim NOW is tailored for capturing and managing infrared sensor data effectively. Designed to work with Xilinx-7 platforms, this IP is aimed at applications requiring precise thermal imaging and data processing. It optimizes the data acquisition process by ensuring successful and efficient data reception from infrared sensors, crucial in fields like surveillance, medical imaging, and industrial automation. This receiver is an essential component for those looking to integrate advanced thermal sensing capabilities into their technology solutions, offering robust performance and reliability.
The EW6181 GPS and GNSS Silicon is designed to offer superior performance with minimal power consumption. This silicon solution integrates multi-GNSS capabilities, including support for GPS L1, Glonass, BeiDou, and Galileo signals. It incorporates patented algorithms that ensure a compact design with exceptional sensitivity and accuracy, all while consuming little power. The chip includes a robust RF front-end, a digital baseband processor for signal processing tasks, and an ARM MCU for running firmware that supports extensive interfaces for varied applications. With built-in power management features like DC-DC converters and LDOs, the EW6181 silicon is particularly suitable for battery-operated devices that demand low BoM costs. Additionally, it includes antenna diversity capabilities, highlighted with a two-antenna implementation to enhance connectivity, making it ideal for devices subject to frequent orientation changes, such as wearable tech and action cameras. The EW6181 is cloud-ready, allowing it to operate in a connected environment to optimize power usage further and enhance accuracy and sensitivity. When used with EtherWhere's AccuWhere cloud service, the silicon can significantly reduce device-side computations, leading to longer battery life and more frequent location updates, tailored for modern navigation and asset tracking applications.
The PUSCH Equalizer by AccelerComm is a cutting-edge solution aimed at improving spectral efficiency in 5G NR networks, particularly those involving multiple antenna configurations. It addresses the challenges of noise and interference using advanced equalization algorithms, which are efficiently implemented as hardware accelerations. This product integrates with the PUSCH Decoder, enhancing performance and cost-efficiency by incorporating demodulation and decoding capabilities. Compliant with 3GPP standards, the PUSCH Equalizer offers superior uplink performance, optimized for both FPGA and ASIC platforms, and contributes to faster market deployment for network operators.
The Waves Dragonfly platform is a sophisticated IP solution designed to integrate full NB-IoT and GNSS support into smart IoT devices. It provides extensive features that cater to the needs of the cellular IoT market, offering embedded GPS capabilities for precise geolocation and tracking. With a robust, flexible architecture, this platform can support multiple standards for wide application in various IoT projects.
The DCAN XL is an innovative CAN bus controller IP core that marks a significant advancement in automotive network communication. This core supports a wide spectrum of communication protocols, effectively bridging the gap between established technologies like CAN FD and high-speed protocols akin to 100Mbit Ethernet. With data rates peaking at 20 Mbit/s, the DCAN XL IP core transforms conventional automotive communications into a much more robust and faster solution. One of the standout features of the DCAN XL core is its dual-transceiver capability, incorporating both standard CAN transceivers for bit rates under 10Mbps and CAN SIC XL transceivers for higher bit rates, thereby ensuring comprehensive support for varied network conditions. This makes it particularly suitable for integration within automotive networks that require adaptability across different communication speeds and protocols, allowing seamless transition and interaction among various system components. The DCAN XL is not just about high speed and versatility; it also emphasizes compatibility, conforming fully to the ISO 11898-1:2015 standard. This assures seamless integration with existing network architecture, providing manufacturers with a reliable solution for advanced automotive applications. Its design fosters efficient and error-free communication across various networks, positioning it as a critical component for next-generation automotive technologies.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The PentaG RAN platform is designed for emerging 5G network infrastructure, providing a comprehensive baseband solution for 5G RAN ASICs and Open RAN systems. It is recognized for industry-leading performance and scalability, tailored to meet the rigorous demands of modern communications networks. The platform supports a variety of network configurations and use cases, ensuring the facilitation of seamless communication in both urban and rural settings.
The Ubi.cloud solution by Ubiscale is a groundbreaking software innovation designed for IoT tracking devices. This solution significantly reduces the power consumption and costs associated with typical GPS and Wi-Fi processing in IoT trackers by shifting these processes to the cloud. As a result, it supports the seamless implementation of geolocation services across diverse environments. The Ubi.cloud platform is versatile, offering high precision and low power options that make it ideal for tracking applications in both indoor and outdoor settings. This solution's architecture enables significant savings by reducing the time and power needed for GPS cold-starts and native Wi-Fi sniffing. Another advantage of the Ubi.cloud solution is its compatibility with a range of low-power wide-area networks (LPWANs) like Sigfox, LoRa, and NB-IoT. This allows for a wide application across different IoT ecosystems. It efficiently handles real-time geolocation data with minimal energy use, which is essential for devices that require prolonged battery life, such as asset trackers and wearables. Moreover, Ubi.cloud offers flexible business models, including pay-as-you-go and lifetime licenses, ensuring that it meets varied market needs. Its API services work seamlessly with the embedded technologies of UbiGNSS and UbiWIFI, providing robust solutions that cater to specific tracking requirements with programmable accuracy and compact data payloads.
The WDR Core provides an advanced approach to wide dynamic range imaging by controlling image tone curves automatically based on scene analysis. This core is adept at ensuring that both shadows and highlights are appropriately compensated, thus maintaining image contrast and true color fidelity without the reliance on frame memory. Automatic adjustments extend the dynamic range of captured images, providing detailed correction in overexposed and underexposed areas. This capability is vital for environments with variable lighting conditions where traditional gamma corrections might introduce inaccuracies or unnatural visual effects. The core focuses on enhancing the user experience by delivering detailed and balanced images across diverse scenarios. Its versatility is particularly useful in applications like surveillance, where clarity across a range of light levels is critical, and in consumer electronics that require high-quality imaging in varying illumination.
The hellaPHY Positioning Solution is renowned for its exceptional capabilities in cellular positioning, particularly within massive IoT environments. It leverages the strength of 5G networks to provide scalable, low-cost, positioning services with high precision. PHY Wireless has engineered it to require significantly less data than other solutions, thanks to its unique algorithmic approaches. This reduces network interactions and enhances spectral efficiency, making it an enticing option for operators and developers alike. One of the key components of this solution is its ability to function indoors and outdoors with near GNSS accuracy. By employing edge computing, the position calculations are done locally on devices, protecting user privacy and maintaining tight security on location data. The software’s minimal footprint allows for integration into existing infrastructure, offering backward compatibility and ensuring future readiness. hellaPHY stands out in the realm of positioning technology by achieving unparalleled accuracy, thanks to its efficient data utilization. It supports efficient location tracking in challenging environments, such as urban areas, where traditional GPS might falter. Furthermore, the technology offers the flexibility of over-the-air updates, keeping network utility optimal and guardband costs low through advanced spectral efficiency.
IRIS is a precision-engineered tool tailored for RF and analog IC simulation. Its primary purpose is to provide designers with accurate and fast electromagnetic simulations that are essential for crafting high-performance RF circuits and analog designs. With the growing demand for advanced radio frequency applications, IRIS serves as a vital resource for engineers aiming to push the boundaries of innovation. The tool boasts high fidelity in simulating RF and analog behaviors, catering to the need for precise modeling in frequency-dependent environments. IRIS allows engineers to evaluate various scenarios, ensuring device robustness and reliability when deployed in real-world applications. This foresight is particularly beneficial in rapidly evolving industries where technological superiority is a cornerstone of success. By facilitating comprehensive assessments, IRIS ensures that potential performance issues are identified and rectified early in the design process, thus securing a smoother path to production. The tool's efficient simulations make it indispensable for developers focused on cutting-edge RF and analog designs.
Dyumnin Semiconductors' RISCV SoC is a powerful, 64-bit quad-core server-class processor tailored for demanding applications, integrating a multifaceted array of subsystems. Key features include an AI/ML subsystem equipped with a tensor flow unit for optimized AI operations, and a robust automotive subsystem supporting CAN, CAN-FD, and SafeSPI interfaces.\n\nAdditionally, it includes a multimedia subsystem comprising HDMI, Display Port, MIPI, camera subsystems, Gfx accelerators, and digital audio, offering comprehensive multimedia processing capabilities. The memory subsystem connects to various prevalent memory protocols like DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring vast compatibility.\n\nThe RISCV SoC's design is modular, allowing for customization to meet specific end-user applications, offering a flexible platform for creating SoC solutions with bespoke peripherals. It also doubles as a test chip available as an FPGA for evaluative purposes, making it ideal for efficient prototyping and development workflows.
The 60GHz Wireless Solution by CLOP Technologies employs the IEEE 802.11ad WiFi standard, also known as the Wireless Gigabit Alliance MAC/PHY specification, to deliver high-speed data transfer. With peak data rates reaching up to 4.6Gbps, it is perfect for complex applications like real-time, uncompressed HD video streaming and high-speed file transfer, improving today’s WiFi speeds tenfold. A key feature of this technology is its support for 802.11ad IP networking, facilitating IP-based tasks such as peer-to-peer communication and router/access point functionalities. It also includes a USB 3.0 host interface for easy connection to hosts and compensates for RF impairments, ensuring robust performance even at high data operations. This product is engineered to handle the substantial data demands of modern IoT devices and provide a competitive advantage through its enhanced wireless data technology. Functioning in the 57GHz to 66GHz frequency band, it uses modulation modes like BPSK, QPSK, and 16QAM. Its FEC coding rates include LDPC 1/2, 5/8, 3/4, and 13/16, with AES-128 hardware security and IEEE 802.11e Real Time QoS to ensure a quality, secured wireless experience.
ASPER is NOVELIC's advanced 79GHz short-range radar sensor, crafted to supersede traditional ultrasonic systems. It offers a 180-degree field of view, enabling a 360-degree awareness for vehicles with just four modules. This sensor is pivotal for applications like park assist, collision warning, and blind spot detection. By operating in challenging conditions without performance degradation, it ensures the safety and efficiency of automotive systems.
The Bluetooth LE Audio Solutions offered by Packetcraft represent a full spectrum approach to enable seamless migration and integration into Bluetooth LE Audio standards. This comprehensive offering includes a range of host, controller, and LC3 codec functions designed to optimize and facilitate the deployment of these audio technologies. The solution provides support for Auracast broadcast audio, which significantly enhances the potential for audio sharing and TWS stereo setups, delivering unprecedented flexibility for diverse product applications. The integration of these technologies into popular chipsets ensures that companies can leverage Packetcraft's solutions for easy and efficient product development in the wireless audio landscape. Designed to drive innovation and uphold superior audio quality, these solutions encapsulate Packetcraft's dedication to forward-thinking technical advancements in the field of wireless communications. Companies can achieve a competitive edge in the market by adopting these flexible and compatible solutions, which are already configured for several leading semiconductor platforms. This adaptability enables a smoother transition to the new Bluetooth audio standards, ensuring companies are well-equipped to address specific market needs and consumer expectations. Moreover, Packetcraft’s Bluetooth LE Audio Solutions are fortified with ongoing maintenance and expert support, empowering consumer electronics, industrial, and automotive sectors with robust, market-ready implementations. This comprehensive strategy allows companies to remain on the cutting edge of audio technology and to quickly tailor their offerings to resonate with emerging consumer demands.
The Digital Radio (GDR) from GIRD Systems is a highly adaptable, reconfigurable multi-channel Software Defined Radio (SDR) equipped with robust high-speed signal processing capabilities. At its core, the GDR features a single board module easily customizable to cater to diverse requirements for both either embedded and standalone systems. Covering an extensive frequency range, the GDR can be set up to function with one or two separate transceivers, whether full or half duplex. Its flexible architecture allows operation in either a single channel or multiple-input, multiple-output (MIMO) configurations, accommodating a wide array of use cases. The SDR’s underlying flexibility not only makes it suitable for a broad range of applications but also ensures it can be tailored to suit specific operational needs effectively. By supporting both standalone and embedded configurations, the GDR enhances communication reliability in dynamic environments. Ideal for deployment in congested and contested settings, the GDR's capability to adapt quickly to evolving requirements makes it a valuable tool for advanced signal processing and digital communication tasks. Its modular design focuses on minimizing overheads while maintaining high performance, thereby offering cost-effective solutions with minimal design compromise.
The GNSS VHDL Library is a high-performance, sophisticated library developed to streamline the integration of satellite navigation capabilities within digital hardware systems. Tailored for flexibility and adaptability, this library facilitates various GNSS systems, including GPS, GLONASS, and Galileo. Its design enables effective signal processing and navigation solutions through dedicated VHDL modules. A notable aspect of the GNSS VHDL Library is its compatibility with multiple hardware platforms and architectures, which include SPARC V8 and RISC-V systems. It encompasses modules like fast search engines, Viterbi decoders, and self-test units, allowing developers to customize and refine their application according to specific needs. The library supports a range of configurations: it can be tailored to manage different numbers of channels, frequencies, and system modules as specified by user requirements. By implementing a single, comprehensive configuration file, it minimizes the need for repetitive customization across different systems, which can significantly decrease development times and costs.
The Neuropixels Probe represents a significant breakthrough in the field of neuroscience research, offering unprecedented resolution and data gathering capabilities. Designed by Imec for use in in vivo studies, this probe enables researchers to acquire signals from thousands of neurons simultaneously, providing invaluable insights into brain function and neurology. With its high-density electrode array, the Neuropixels Probe delivers precise neural recordings, capturing a vast range of neuronal activity across different brain regions. This enables a deep and comprehensive understanding of neural pathways and functions, pivotal for advancing neurological and psychiatric research. Imec's world-leading semiconductor expertise ensures the Neuropixels Probe is equipped with the latest advancements in microfabrication technology, making it highly compatible with current laboratory equipment and methods. This innovation facilitates seamless integration with existing setups while opening new vistas for exploration in neuroscience.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.