All IPs > Wireless Communication
The Wireless Communication category at Silicon Hub encompasses a diverse array of semiconductor IPs designed to facilitate seamless wireless connectivity in today's rapidly evolving technological landscape. As the demand for higher data rates and uninterrupted connectivity grows, these IPs play a vital role in enabling devices to communicate efficiently across various protocols and standards. This category includes highly specialized IPs that support the implementation and enhancement of wireless communication technologies in a variety of applications ranging from consumer electronics to industrial systems.
Within this category, semiconductor IPs cover a wide spectrum of wireless standards and protocols. This includes evolving mobile communication standards like 3GPP-5G and LTE, which are essential for cellular networks' operation and are pivotal in the deployment of the latest 5G networks. For localized wireless communication, standards such as 802.11 (commonly referred to as Wi-Fi), Bluetooth, NFC, and Wireless USB are covered, facilitating device interconnectivity and data exchange in numerous consumer electronics, IoT devices, and more. Industrial and professional applications may utilize IPs related to standards like WiMAX (802.16), CPRI, OBSAI, which are crucial for network infrastructure and robust communication systems.
In addition to these, the Wireless Communication category includes IPs for satellite navigation systems like GPS, ensuring accurate geolocation services essential for navigation devices in both personal and commercial use. Standards like UWB (Ultra-Wideband) offer high-speed data transmission over short ranges, beneficial for applications demanding rapid short-range communication. Furthermore, for high-definition broadcasting, IPs supporting Digital Video Broadcast standards offer necessary capabilities to meet market demands for clear and reliable video content transmission.
This extensive category of semiconductor IPs under Wireless Communication not only provides the architectural needs for state-of-the-art communication devices but also accommodates future technological advancements. By integrating these IPs, semiconductor product designers and engineers can efficiently develop solutions tailored for enhanced connectivity, ensuring their products remain at the forefront of technological innovation and meet the ever-growing expectations of modern consumers for instant and reliable wireless communication. Whether you are developing next-gen smartphones, IoT solutions, or advanced networking systems, these IPs are critical components in achieving superior performance and connectivity.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
CoreVCO represents CoreHW's commitment to delivering innovative wideband voltage-controlled oscillator (VCO) solutions, particularly suited for extremely demanding environments. Constructed utilizing robust SiGe technologies, the CoreVCO incorporates dual radiation-hardened VCOs, catering effectively to applications requiring minimal phase noise and resilient performance. The VCO operates over wide frequency ranges—0.7 GHz to 6.6 GHz—utilizing two distinct oscillator designs (VCOPMOS and VCOBJT). Its ability to maintain low phase noise under harsh conditions makes it ideal for critical applications like military communication systems and space exploration. The design's intrinsic radiation hardness ensures operational continuity where reliability is paramount. CoreHW's CoreVCO incorporates a host of integrated features such as bandgap references, low-dropout regulators, and SPI interfaces for precise control and tuning. With its small form factor, it serves as an efficient solution for a range of high-reliability wireless and communication systems, offering consistent performance across various operating conditions.
KPIT offers a comprehensive solution for Autonomous Driving and Advanced Driver Assistance Systems. This suite facilitates the widespread adoption of Level 3 and above autonomy in vehicles, providing high safety standards through robust testing and validation frameworks. The integration of AI-driven decision-making extends beyond perception to enhance the intelligence of autonomous systems. With a commitment to addressing existing challenges such as localization issues, AI limitations, and validation fragmentation, KPIT empowers automakers to produce vehicles that are both highly autonomous and reliable.
KPIT's digital solutions harness cloud and edge analytics to modernize vehicle data management, optimizing efficiency and security in connected mobility. With a focus on overcoming data overload and ensuring compliance with regulatory standards, these solutions enable secure and scalable cloud environments for vehicle connectivity. The edge computing aspect enhances system responsiveness by processing data within vehicles, promoting innovation and dynamic feature development.
KPIT's propulsion technologies cover both traditional internal combustion engines and modern electric powertrains. By focusing on reducing the total cost of ownership for new energy vehicles, KPIT helps OEMs streamline development cycles and enhance vehicle quality. The company's platform supports agile software updates and sustains efforts on sustainable practices by increasing offerings in zero-emission vehicles (ZEVs) and exploring alternative fuels like hydrogen. With solutions spanning engine subsystems, transmission, and driveline optimization, KPIT addresses the intricate balance needed between legacy and emerging automotive platforms.
The ORC3990 is a sophisticated System on Chip (SoC) solution designed for low-power sensor-to-satellite communication within the LEO satellite spectrum. Utilizing Totum's DMSS technology, it achieves superior doppler performance, facilitating robust connectivity for IoT devices. The integration of an RF transceiver, power amplifiers, ARM CPUs, and memory components makes it a highly versatile module. Leveraging advanced power management technology, this SoC supports a battery life that exceeds ten years, even within industrial temperature ranges from -40 to +85°C. It's optimized for usage with Totum's global LEO satellite network, ensuring substantial indoor signal coverage without the need for additional GNSS components. Efficiency is a key feature, with the chip operating in the 2.4 GHz ISM band, providing unparalleled connectivity regardless of location. Compact in design, comparable in size to a business card, and designed for easy mounting, the ORC3990 offers sought-after versatility for IoT applications. The ability to function with excellent TCO in terms of cost compared to terrestrial IoT solutions makes it a valuable asset for any IoT deployment focused on sustainability and longevity.
The NaviSoC by ChipCraft is a sophisticated GNSS receiver system integrated with an application processor on a single piece of silicon. Known for its compact design, the NaviSoC provides exceptional performance in terms of precision, reliability, and security, complemented with low power consumption. This well-rounded GNSS solution is customizable to meet diverse application needs, making it suitable for IoT, Lane-level Navigation, UAV, and more. Designed to handle a wide range of GNSS applications, the NaviSoC is well-suited for scenarios that demand high accuracy and efficiency. Its architecture supports applications such as asset tracking, smart agriculture, and time synchronization while maintaining stringent security protocols. The flexibility in its design allows for adaptation and scalability depending on specific user requirements. The NaviSoC continuously aims to advance GNSS technology by delivering a holistic integration of processing capabilities. It stands as a testament to ChipCraft's innovative strides in creating dynamic, high-performance semiconductor solutions that excel in global positioning and navigation. The module's efficiency and adaptability offer a robust foundation for future GNSS system developments.
The Automotive AI Inference SoC by Cortus is a cutting-edge chip designed to revolutionize image processing and artificial intelligence applications in advanced driver-assistance systems (ADAS). Leveraging RISC-V expertise, this SoC is engineered for low power and high performance, particularly suited to the rigorous demands of autonomous driving and smart city infrastructures. Built to support Level 2 to Level 4 autonomous driving standards, this AI Inference SoC features powerful processing capabilities, enabling complex image processing algorithms akin to those used in advanced visual recognition tasks. Designed for mid to high-end automotive markets, it offers adaptability and precision, key to enhancing the safety and efficiency of driver support systems. The chip's architecture allows it to handle a tremendous amount of data throughput, crucial for real-time decision-making required in dynamic automotive environments. With its advanced processing efficiency and low power consumption, the Automotive AI Inference SoC stands as a pivotal component in the evolution of intelligent transportation systems.
Wasiela's DVB-S2-LDPC-BCH provides a sophisticated forward error correction system designed for digital video broadcasting applications, particularly suited for satellite transmission. This product combines low-density parity-check (LDPC) codes with Bose Chaudhuri Hocquenghem (BCH) codes to achieve quasi error-free operation, operating effectively close to the Shannon limit.<br><br>The implementation boasts an irregular parity check matrix and layered decoding to increase decoding efficiency. The minimum sum algorithm is utilized for optimal performance with soft decision decoding capabilities that allow for higher error correction. This product also complies with ETSI EN 302 307-1 V1.4.1 standards, ensuring high quality and reliability in digital transmission systems.<br><br>Additional functionalities include a BCH decoder adept at correcting multiple errors per codeword, making this solution an ideal choice for ensuring data integrity in demanding satellite communication conditions. Wasiela offers this IP complete with synthesizeable Verilog code, a system model in Matlab, and thorough documentation, ensuring a smooth integration process for any application.
The RT990 represents RafaelMicro's prowess in developing optical communication components, specifically for Cable Television (CATV) systems. This TIA excels in signal amplification, essential for clear, high-fidelity video and audio transmission across optical networks.
eSi-Comms represents EnSilica’s suite of communication IP blocks, designed to enhance modern communication systems through flexible, parameterized IP. These IPs are optimized for a range of air interface standards, including 4G, 5G, Wi-Fi, and DVB, providing a robust framework for both custom and standardized wireless designs.\n\nThe flexibility of eSi-Comms IP allows it to be configured for various interfacing standards, supporting high-level synchronization, equalization, and modulation techniques. The suite includes advanced DSP algorithms and control loops that ensure reliable communication links, vital for applications like wireless sensors and cellular networks.\n\nEnSilica also supports software-defined radio (SDR) applications by offering hardware accelerators compatible with processor cores like ARM, enhancing processing power while maintaining flexibility. This adaptability makes eSi-Comms IP a valuable asset in developing efficient, high-performance communication solutions that can quickly adapt to changing technological demands.
The Matchstiq™ X40 is a high-performance software-defined radio (SDR) engineered with a low size, weight, and power (SWaP) design. This SDR is optimized for edge computing, particularly suited for artificial intelligence (AI) and machine learning (ML) applications. It integrates a robust RF front end with multi-channel digital transceivers, providing access to frequencies up to 18GHz and a bandwidth of 450MHz. It features a Nvidia Orin NX 16G for advanced data processing and an AMD Zynq Ultrascale+ FPGA for signal integration. The small form factor, with precise dimensions and modest weight, offers advantages in space-constrained deployments such as unmanned aerial systems (UxS) and ALE payloads. The Matchstiq™ X40 facilitates superior performance in frequency agility, ideal for spectrum management and complex signal detection tasks. The SDR's architecture supports numerous interface options including USB 3.0 and 1 GbE networking, complemented by serial port connectivity. This device is designed to leverage the libsidekiq API for seamless API integration, making it an indispensable tool for rapid prototyping, testing, and field deployment.
The ADQ35 is a versatile dual-channel digitizer designed for high-performance data acquisition at a sampling rate of 10 GSPS. With its flexible configuration, the ADQ35 supports both a two-channel operation at 5 GSPS and a single-channel mode at the full 10 GSPS. The device is DC-coupled with a bandwidth capacity of up to 2.5 GHz, which suits it for a variety of conditions where signal integrity is key. A highlight of the ADQ35 is its open onboard Xilinx Kintex Ultrascale KU115 FPGA, offering extensive capabilities for custom digital signal processing. This device also facilitates peer-to-peer streaming at a rapidity of 14 Gbyte/s, enabling direct and efficient data transfer to GPUs or CPUs. This makes it exceptional for applications that rely on large-scale data handling and processing efficiency. The ADQ35 is engineered for use in various high-demand applications such as Time-of-Flight Mass Spectrometry, LiDAR systems, and scientific instrumentation. This flexibility is further enhanced by an array of standard and optional firmware packages, which empower users to tailor the device's capabilities according to specific project needs.
This ISM Band RF IP provides a comprehensive solution designed for integration into BLE applications, offering a robust platform with GF 22FDX process node capabilities. Its components include an advanced RF transceiver and digital power amplifier, achieving a peak power output of +23 dBm. The IP optimizes signal strength and minimizes space requirements with an integrated balun and matching network. Designed for versatility, the ISM Band RF IP is adaptable across different process nodes, making it a flexible choice for customers seeking to develop sophisticated RF ICs. The transceiver is in line with modern communication standards and is particularly useful for applications in low-power communication environments. This flexibility allows for the development of cost-effective, high-performing merchant market ICs. Orca Systems ensures that their IP can be efficiently licensed and integrated into various systems, promoting a streamlined and effective path to market for BLE developers. The focus on reduced power consumption and enhanced signal capabilities underscores the value of this IP in expanding and enhancing wireless communication methodologies.
The Polar encoding and decoding IP, compliant with 3GPP standards, offers comprehensive support for various uplink and downlink channels in 5G NR. Utilizing advanced decoding techniques, it provides unparalleled error correction with scalable parameters for parallelism and latency optimization. The Polar solution by AccelerComm is a versatile and powerful option for deploying efficient communication systems, supporting FPGA and ASIC processes, and offering flexibility in system design and implementation, significantly contributing to high error correction performance.
The RWM6050 Baseband Modem from Blu Wireless is a high-performance component designed for mmWave communications. It supports gigabit-level data rates through its advanced modulation and channelization technologies, making it ideal for various access and backhaul applications. The modem's substantial flexibility is attributed to its compatibility with multiple RF chipsets and its design which is influenced by Renesas collaboration, ensuring robust, scalable wireless connectivity. This modem features dual integrated modems and an adaptable digital front end, including PHY, MAC, and ADC/DAC functionalities. It supports beamforming with phased array antennas, facilitating efficient signal processing and network synchronization for enhanced performance. These attributes make the RWM6050 a key enabler for deploying next-generation wireless communication systems. Built to optimize cost efficiency and power consumption, the RWM6050 offers versatile options in channelization and modulation coding, effectively scaling bandwidth to match multi-gigabit requirements. It provides a powerful solution to meet the growing demands of modern data networks, effectively balancing performance, adaptability, and integration ease.
The software-defined High PHY from AccelerComm is tailored for ARM processor architectures, offering flexibility to accommodate a wide array of platforms. This configurable solution can operate independently or, if needed, with hardware acceleration, depending on the application's specific power and performance needs. It's suitable for use in situations where adaptability is paramount and is optimized to minimize latency and maximize efficiency across different platforms, adhering to O-RAN standards, and enhancing system capability by integrating with other IP offerings such as accelerators.
The TW330 specializes in high-performance image processing, focusing on advanced coordinate transformation utilities using GPU technological advancements. It supports distortion correction and resolution scaling up to 16K x 16K with various image formats like RGB and YUV. Its diverse applications in digital camera products, automotive displays, and VR systems underscore its versatility. TW330 is perfect for scenarios needing on-the-fly image adjustments, ensuring clarity and fidelity in large-scale projections and displays.
The 802.11 LDPC solution from Wasiela is designed to excel in delivering high throughput and robust error correction for wireless communication systems. It supports frame-to-frame, on-the-fly reconfiguration, enabling adaptability to varying data loads and transmission conditions. By permitting configurable LDPC decoding iterations, it allows users to find the perfect balance between throughput and error correction, ensuring optimum performance in all scenarios.<br><br>This LDPC offering matches bit-error-rate and packet-error-rate performance requirements, solidifying its reputation as a reliable choice for modern wireless systems. With its ability to handle high throughput at minimal latency, the 802.11 LDPC component is essential for applications demanding high-speed data transmission, ensuring that error-free data packets are a consistent reality.<br><br>Wasiela's design of the 802.11 LDPC takes into account the need for both performance and flexibility, crafting a solution that is ready to integrate seamlessly into various applications, from consumer electronics to industrial communication networks. This adaptability is a testament to Wasiela's commitment to empowering developers with IP cores that are both cutting-edge and user-friendly.
The ADQ35-WB is a robust data acquisition module designed to handle both high-frequency and dual-channel applications at a high sampling rate. It offers either a dual-channel configuration at 5 GSPS or a single-channel setup at 10 GSPS. The digitizer boasts a significant 9.0 GHz usable analog input bandwidth, making it ideal for complex and high-demand applications such as RADAR, LiDAR, and scientific research. Equipped with an open onboard Xilinx Kintex Ultrascale KU115 FPGA, the ADQ35-WB provides substantial resources for custom real-time digital signal processing. This module also supports high-speed peer-to-peer streaming of data to GPUs or CPUs at speeds up to 14 Gbyte/s. This high throughput is complemented by advanced triggering options, making it highly functional for sophisticated data handling and processing. In terms of practical usage, the ADQ35-WB includes a comprehensive suite of hardware options, firmware, and software tools designed for straightforward integration into existing systems. This includes the default data acquisition firmware, optional waveform averaging, and pulse detection firmware, as well as a development kit for customized FPGA development.
The CANmodule-III is a full CAN controller catering to complex automotive and industrial applications. It supports advanced features like multiple FIFO and mailbox configurations, ensuring effective message handling. With compliance to CAN2.0B, this controller ensures impeccable communication across CAN networks, making it suitable for highly demanding environments. It's designed to seamlessly integrate custom or standard filters, enhancing message security and efficiency. Engineered with flexibility in mind, it surpasses basic CAN functionalities, offering the ability to adapt additional application-specific functions as wraparounds that leave the core uninfluenced. This ensures stability while meeting specific design requirements. Integrating the CANmodule-III into your design is facilitated by its robust interface and modular structure, guaranteeing compatibility with both ASIC and FPGA technologies. With its refined architecture, it consistently delivers high performance across a range of sectors where CAN communication is integral.
The CANmodule-IIIx is an advanced CAN controller that builds upon the foundation set by its predecessors to meet the rigorous demands of modern communication systems. Capable of managing 32 receive and 32 transmit mailboxes, this module is perfect for intensive applications requiring high throughput and reliability. It is designed to work seamlessly with industry-standard CAN2.0B protocols, ensuring consistent performance across various devices and systems. The CANmodule-IIIx also includes robust support for storage and retrieval of messages via its FIFO-based architecture, making it suitable for high-speed communications in automotive and industrial networks. In addition, this controller benefits from customizable application-specific features that enhance its overall functionality without compromising the integrity of the core functionalities. With its high integrity, reliability, and ease of use, the CANmodule-IIIx is a top choice for developers looking to implement complex CAN network solutions across various technologies including FPGA and ASIC.
The CANmodule-IIx is a sophisticated CAN controller tailored for streamlined message handling within specialized network systems. With its FIFO-based design architecture, it offers efficient message throughput and storage, meeting the demands of high-speed communication environments. It is fully compliant with the CAN2.0B protocol, ensuring reliable and standardized communication capabilities. The CANmodule-IIx is versatile, controlling data transfers across various modules effortlessly, while its efficient design architecture supports both FPGA and ASIC technologies. Equipped to handle an array of custom filters, this module allows for enhanced message control tailored to application-specific requirements. Its robust construction and flexible configuration options make it an ideal choice for automotive communications, industrial automation, and other demanding sectors where reliability and speed are crucial.
The HOTLink II Product Suite is specifically designed to enhance and support optical communication within advanced avionics systems. It stands as a pivotal element for systems requiring robust high-speed data transmission, such as graphics generation and flight simulation. The product suite offers engineers a reliable framework to develop and optimize communication channels within their systems, addressing the need for precise data flow in demanding operational environments. This suite's capabilities extend to simplifying design processes by integrating essential tools that facilitate the development of complex communication systems. Such systems are vital for ensuring seamless data transmission in avionics, where precision and reliability are crucial. The HOTLink II Product Suite empowers developers to create highly efficient optical interfaces that meet the challenges of modern aerospace and defense applications. In addition to its core functions, the suite offers comprehensive resources that aid in enhancing the overall performance of optical data links. It provides engineers with the flexibility to adapt the technology for use across various platforms, ensuring consistency and reliability of data flow, which is essential for maintaining the integrity of flight-critical systems.
Wireless Sensor Modules by Granite SemiCom are designed to provide high flexibility and extended range for IoT applications. Utilizing LoRa transceivers, these modules operate over long distances, making them suitable for environments where connectivity over vast areas is required. Their design is optimized for battery efficiency, ensuring long operational lifetimes with low power consumption. These modules also support over-the-air updates, enhancing their functionality and adaptability in dynamic settings. With built-in encryption, they offer secure wireless communication, crucial for safeguarding data integrity across networks.
Polar Encoders/Decoders from Creonic are designed with the latest communication standards in mind, delivering exceptional performance in error correction through polar coding techniques. Originally developed for 5G systems, polar coding offers strong error correction capabilities with high efficiency, making these cores critical for next-generation communication systems. These encoders/decoders provide a consistent performance boost by efficiently utilizing channel capacity, which is particularly beneficial in high-throughput scenarios such as wireless backhaul and cellular networks. Creonic’s implementation focuses on minimizing complexity while maximizing speed, ensuring the cores can handle demanding communication tasks without excessive processing overhead. The Polar Encoders/Decoders IP cores are packed with a rich set of features that include adjustable code rates and length, providing adaptability to various requirements. With comprehensive support for both FPGA and ASIC deployments, they offer a robust, flexible solution for those looking to enhance their existing digital communication frameworks.
Turbo Encoders/Decoders by Creonic represent key components for achieving effective forward error correction in communication systems. Utilizing turbo coding, these IP cores enhance data throughput by rapidly encoding and decoding signals, ensuring minimal error propagation and optimal data integrity. Widely used in standards like DVB-RCS2 and LTE, Turbo coding provides excellent performance gains in error correction. These cores are specifically designed to handle large volumes of data with high efficiency, allowing technologies like 4G and upcoming 5G networks to deliver their promised speeds reliably. Creonic’s Turbo Encoders/Decoders support a range of code rates, making them adaptable for various transmission conditions and enabling dynamic applications across different communication landscapes. Importantly, they incorporate advanced algorithmic techniques to accelerate processing speeds and reduce latency – essential qualities for real-time applications. Supported with a suite of testing environments and simulation models, these IP cores ensure straightforward integration into user hardware, providing considerable flexibility for both FPGA and ASIC implementation scenarios.
The 60GHz Wireless Solution by CLOP Technologies employs the IEEE 802.11ad WiFi standard, also known as the Wireless Gigabit Alliance MAC/PHY specification, to deliver high-speed data transfer. With peak data rates reaching up to 4.6Gbps, it is perfect for complex applications like real-time, uncompressed HD video streaming and high-speed file transfer, improving today’s WiFi speeds tenfold. A key feature of this technology is its support for 802.11ad IP networking, facilitating IP-based tasks such as peer-to-peer communication and router/access point functionalities. It also includes a USB 3.0 host interface for easy connection to hosts and compensates for RF impairments, ensuring robust performance even at high data operations. This product is engineered to handle the substantial data demands of modern IoT devices and provide a competitive advantage through its enhanced wireless data technology. Functioning in the 57GHz to 66GHz frequency band, it uses modulation modes like BPSK, QPSK, and 16QAM. Its FEC coding rates include LDPC 1/2, 5/8, 3/4, and 13/16, with AES-128 hardware security and IEEE 802.11e Real Time QoS to ensure a quality, secured wireless experience.
ArrayNav is an innovative GNSS solution that employs multiple antennas, enhancing sensitivity and accuracy to combat common issues like multipath interference and signal jamming. This technology is designed to increase the effectiveness of global positioning systems by using adaptive antenna systems, a concept borrowed from advanced wireless communications. ArrayNav provides up to 18dB gain in signal strength for fading channels and ensures robust performance even in complex environments like urban canyons. By identifying and nulling unwanted signals, it maintains the integrity of GNSS operations against spoofing and interference. This technology is vital for applications needing high precision under challenging signal conditions. With its sophisticated antenna diversity, ArrayNav is crafted to deliver sub-meter precision and swift signal acquisition. This makes it a valuable component for navigation in densely constructed urban landscapes or covered environments where satellite visibility might be obscured. ArrayNav's capability to handle multipath and interference issues effectively makes it a preferred choice for high-reliability navigation systems, contributing to both enhanced security and accuracy.
The Cortus NB-IoT C200 is a sophisticated narrowband-IoT solution integrated with Bluetooth Low Energy capabilities, designed to meet the needs of smart IoT systems. This IP enables seamless connectivity in sub-GHz unlicensed ISM bands, offering robust performance for remote and wireless communication. Ideally suited for smart metering and industrial IoT applications, this IP delivers reliable, low-power wireless connectivity essential for long-distance communication without sacrificing battery life. Built with the latest advancements in wireless technology, the NB-IoT C200 provides comprehensive support for various IoT standards, ensuring broad compatibility and adoption across multiple platforms. Its low-data-rate, extensive coverage, and reduced power consumption features make it an optimal choice for portable devices and remote sensors that rely on uninterrupted connections. With its capacity to handle significant data processing at reduced bandwidths, the NB-IoT C200 is in line with the demands of modern IoT ecosystems. This model is particularly adept at maintaining efficient operations in dense urban environments, thanks to its noise-immune and highly stable connection protocols.
Designed for efficient low-density parity-check decoding, Mobiveil's 5G NR LDPC Decoder IP implements an optimized version of the Min-Sum algorithm. This design provides flexibility with programmable bit widths and supports early termination features, enhancing decoding speeds. It is particularly adept in 5G communications, allowing for real-time iterative correction and improving overall transmission reliability in high-performance wireless applications.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The 802.11ah HaLow Transceiver by Palma Ceia represents a significant advance in IoT communications technology. Designed to address the power and bandwidth limitations of traditional Wi-Fi for IoT applications, it offers enhanced range, lower power consumption, and operates in sub-1 GHz bandwidths. This transceiver supports low data rate communications over long distances, making it perfect for IoT devices that require reliable network presence. Its integrated power management mechanisms ensure prolonged battery life for sensor-based applications. Moreover, with stringent adherence to the 802.11ah standard, the transceiver guarantees compatibility with various IoT ecosystems. This IP's capability to function as both a standalone component or part of a System-on-Chip (SoC) allows for flexible design implementations. Applications range from smart city infrastructures to personal health monitoring devices, highlighting its versatility in meeting diverse connectivity needs in the IoT domain.
The ADQ7DC is a state-of-the-art digitizer that offers a blend of high resolution with 14 bits and a rapid 10 GSPS sampling rate. This model surpasses previous limitations in high-speed applications, opening new possibilities for advanced measurement and processing tasks. It operates in both single-channel at 10 GSPS and dual-channel at 5 GSPS modes, offering versatility in data capture requirements. Its DC-coupled input boasts a commendable 3 GHz input bandwidth, with capabilities for programmable DC-offsets and a digital noise reduction filter. The onboard Xilinx Kintex Ultrascale KU115 FPGA provides ample resources for diverse real-time digital signal processing tasks. With peer-to-peer data streaming to GPUs facilitated at 7 Gbyte/s, users gain enhanced efficiency for intensive data handling applications. With its broad compatibility with various form factors like PCIe and PXIe, ADQ7DC is ideal for high-speed RF data recording, scientific instruments, and more. The built-in firmware offers a rich selection of application-specific functions that can be accessed without any need for FPGA development, significantly simplifying its operation and integration.
The NeuroVoice AI Chip offers a revolutionary solution for voice processing, harnessing neuromorphic frontend technology to provide ultra-low power consumption and superior noise resilience. It is designed for hearables and smart voice-controlled devices, ensuring efficient operation even in high-noise environments. This chip processes audio data on-device, eliminating the need for continuous cloud connectivity while enhancing user privacy. By integrating NASP technology, the NeuroVoice chip excels in voice activity detection, smart voice control, and voice extraction, making it ideal for applications in earbuds, voice access systems, and smart home devices. Its ability to only transmit or recognize human voice while muting background sounds significantly improves command clarity and user interactions, especially in environments prone to irregular noises. The chip is designed to adapt to various audio inputs, providing capabilities for clear communication, enhancing speech intelligibility, and offering features like voice passthrough in hearing aids. With power consumption kept below 150µW, it allows for prolonged device usage and efficient battery management, making it an ideal component for modern voice-activated devices and hearing assistance technologies.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
The PCS2100 Wi-Fi HaLow IoT STA/Client is a transceiver designed to extend Wi-Fi networks to IoT devices operating in challenging environments. Utilizing the 802.11ah standard, this product emphasizes long-range transmission with a low power requirement, making it ideal for battery-powered IoT sensors and devices. With its sub-1GHz frequency, the PCS2100 provides superior wall penetration and reaches further distances compared to traditional Wi-Fi frequencies. It supports ultra-narrow bandwidth modulations, which enhances spectrum efficiency and minimizes interference. This makes it suitable for densely populated areas where multiple IoT devices need to be reliably connected. Palma Ceia has ensured that the PCS2100 is versatile, allowing it to integrate seamlessly into existing IoT ecosystems while offering robust security features to protect data integrity. Its adaptability and power efficiency are perfect matches for various IoT applications such as smart agriculture, logistics tracking, and environmental monitoring.
Efinix's Titanium Ti375 FPGA is a high-density device designed for applications demanding low power consumption alongside robust processing capabilities. This FPGA is embedded with the Quantum® compute fabric, an architecture that delivers significant power, performance, and area benefits. Notably, the Ti375 incorporates a hardened quad-core RISC-V block, various high-speed transceivers for protocols like PCIe Gen4, and supports LPDDR4 DRAM for efficient memory operations. The Ti375 excels in its ability to facilitate high-speed communications and sophisticated data processing, owing in part to its multiple full-duplex transceivers. These transceivers support a swath of industries by enabling data rates up to 16 Gbps for PCIe interfaces or up to 10 Gbps for Ethernet links. Additionally, the FPGA is equipped with advanced MIPI D-PHY functionalities, crucial for applications in the fields of imaging and vision. This versatile FPGA supports the development of complex systems, from industrial automation to advanced consumer electronics, by offering features like extensive I/O configurations and on-board debugging capabilities. With the comprehensive Efinity software suite, developers can streamline the transition from RTL design to bitstream generation, enhancing project timelines significantly. Whether used as a standalone solution or integrated into a larger system, the Ti375 provides an adaptable framework for modern design challenges.
Creonic's LDPC Encoders/Decoders are designed to provide high-efficiency error correction for modern communication systems. These IP cores follow advanced LDPC (Low-Density Parity-Check) coding schemes to offer a balance of performance and flexibility. They are suitable for use in a plethora of standards such as DVB-S2, DVB-S2X, 5G, and CCSDS, ensuring robust data transmission across various signal conditions. The LDPC solutions by Creonic are known for their high throughput, making them fit for applications that demand speed and accuracy. Their capability to process and correct errors efficiently ensures data integrity, especially in bandwidth-critical systems. Users can expect comprehensive integration support with available design kits and simulation models that aid seamless incorporation within existing hardware platforms. With flexibility for both FPGA and ASIC implementations, Creonic's LDPC encoders and decoders come equipped with adaptive features that allow for various code rates and block lengths. This adaptability ensures that users can tailor the application to meet specific requirements, benefiting from the cores' proven reliability in delivering high-quality data communication.
The mmWave PLL by CoreHW is a sophisticated frequency synthesizer designed to meet the demands of modern wireless communication networks and radar systems. It features a high-accuracy fractional-N PLL frequency synthesizer with a very low noise voltage-controlled oscillator (VCO). This design supports efficient generation of low phase noise carriers and rapid chirp frequency modulations required for fast-frequency modulated continuous wave (FMCW) radar. Operating initially in the frequency range of 19.00-20.15 GHz, the mmWave PLL is engineered to extend to radar frequency bands from 38-40.5 GHz and even further to 76-81 GHz through frequency multipliers. Its scalable frequency configuration makes it suitable for diverse applications including 5G networks and various mmWave communication devices, providing flexibility for adaptation to specific needs. Key features include integrated bandgap references, low-dropout regulators (LDOs), and integrated frequency multipliers. The PLL supports fractionally precise chirp modulation capabilities, making it ideal for automotive radar applications like collision avoidance and distance measurement. The device is robust, maintaining optimal performance across a wide temperature range, and includes comprehensive built-in self-test and calibration features to facilitate reliable deployment in high-demand environments.
AccelerComm's High PHY Accelerators are a set of scalable IP cores for ASIC, FPGA, and SoC platforms, employing patented signal processing algorithms to boost throughput while lowering latency and power consumption. These accelerators are essential for enhancing the overall performance of 5G NR networks. They support diverse architectures with flexibility in integration, catering to specific deployment capacities across platforms. These accelerators showcase AccelerComm's dedication to efficiency and performance, providing adaptable and robust designs suited for cutting-edge technological applications.
The Hyperspectral Imaging System from IMEC offers an advanced portable solution for comprehensive spectral analysis. By employing cutting-edge sensor technology combined with powerful optics, it captures a broad spectrum of light. This system is instrumental in industries ranging from agriculture to healthcare. It provides precise imaging capabilities, enabling users to confidently conduct critical assessments such as plant health monitoring, mineral detection, or even advanced medical diagnostics. Hyperspectral technology bridges the gap between large-scale economic efficiency and intricate analysis, paving the way for new applications across fields by offering unprecedented spectral resolution.
The LTE Lite from Wasiela offers a light yet powerful solution for User Equipment (UE) LTE applications, specifically designed to support CAT 0/1 PHY. It is compatible with intermediate frequency inputs and offers flexible channel bandwidths ranging from 1.4 MHz to 20 MHz, supporting a variety of modulation schemes including QPSK, 16QAM, and 64QAM.<br><br>This product is ideally suited for integrating into systems requiring flexible and scalable LTE solutions. Its design leverages a synthesizable Verilog-2001 framework, making it highly portable and adaptable for various applications. The operation is automated through a master finite state machine, optimizing the interaction between the LTE Lite and other system components.<br><br>Noteworthy is its ability to correct significant frequency and timing mismatches, ensuring reliable data transmission across extended network environments. Overall, LTE Lite by Wasiela offers a compelling blend of performance, flexibility, and ease-of-integration for a wide range of telecommunications and consumer electronics applications.
The PCS2500 Wi-Fi HaLow Access Point enables extended Wi-Fi coverage for IoT applications in industrial and consumer environments. This IP is based on the IEEE 802.11ah standard and is engineered for low power consumption and robust performance in extended ranges. As an access point, the PCS2500 can connect a multitude of IoT devices over wide areas, maintaining reliable communication channels even in electrically noisy environments. It offers features like advanced interference mitigation and efficient data throughput to ensure smooth and consistent network performance. This access point is designed to enhance IoT network flexibility, supporting various applications from smart homes to large-scale industrial setups. With a focus on ease of integration and scalability, the PCS2500 is a key component for building expansive and responsive IoT networks.
IRIS is a precision-engineered tool tailored for RF and analog IC simulation. Its primary purpose is to provide designers with accurate and fast electromagnetic simulations that are essential for crafting high-performance RF circuits and analog designs. With the growing demand for advanced radio frequency applications, IRIS serves as a vital resource for engineers aiming to push the boundaries of innovation. The tool boasts high fidelity in simulating RF and analog behaviors, catering to the need for precise modeling in frequency-dependent environments. IRIS allows engineers to evaluate various scenarios, ensuring device robustness and reliability when deployed in real-world applications. This foresight is particularly beneficial in rapidly evolving industries where technological superiority is a cornerstone of success. By facilitating comprehensive assessments, IRIS ensures that potential performance issues are identified and rectified early in the design process, thus securing a smoother path to production. The tool's efficient simulations make it indispensable for developers focused on cutting-edge RF and analog designs.
AccelerComm's LDPC solution brings in innovative designs that balance performance with efficiency for 5G NR data channels. Featuring robust error correction capabilities, this IP uses state-of-the-art architectural design to achieve superior throughput without error floors, essential for high-demand communication systems. It's adaptable and can be integrated seamlessly into existing systems, supporting various platform configurations and ensuring high hardware efficiency and low latency—all while complying with 3GPP standards for optimal integration.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
The EW6181 is an advanced multi-GNSS silicon designed for high sensitivity and low power consumption, a stand-out product in GPS and GNSS technology. It supports multiple global positioning systems like GPS L1, Glonass, BeiDou, Galileo, SBAS, WASS, and A-GNSS. This silicon includes an integrated RF frontend, a digital baseband for signal processing, and ARM MCU to efficiently run the necessary firmware. This chip is tuned for low energy use, incorporating a DC-DC converter along with high voltage and low voltage LDOs, which makes it ideal for battery-powered devices. Its size and energy efficiency make it a competitive module component that reduces the overall Bill of Materials (BoM) for manufacturers. The EW6181's architecture is optimized for cloud readiness, offering enhanced capabilities for applications needing intensified accuracy and power savings through cloud connectivity. A unique feature of the EW6181 is its implementation in a 2-antenna Evaluation Kit, showcasing its potential to improve device connectivity and performance with antenna diversity mode, perfect for rotating devices like action cameras and wearable tech. This diversity offers key advantages in both connectivity and user experience, emphasizing the EW6181 as a flexible, high-performing component in various technological ecosystems.
RF Integration's 802.11 Transceiver Core is specifically engineered to support wireless LAN communications. Compatible with IEEE 802.11 a/b/g/n standards, this transceiver facilitates seamless high-speed data transfer for a range of multimedia and internet connectivity applications. It integrates RF front-end components and baseband processing blocks, ensuring efficient handling of signal transmission and reception. The core is designed for power efficiency and superior performance, making it ideal for use in consumer electronics such as laptops, smartphones, and tablets. With support for multiple configurations and enhancements like MIMO (Multiple Input Multiple Output) technology, it caters to the growing demand for robust wireless solutions that provide improved data throughput and extended range. Its compatibility with both legacy and modern wireless standards ensures that it remains a versatile solution as network infrastructures evolve.
The DVB-RCS and IEEE 802.16 WiMAX Turbo Decoder is expertly crafted for decoding tasks in high-speed data networks, particularly those using satellite and broadband wireless communication standards. This 8 state Duobinary Turbo Decoder features an optional 64 state Viterbi decoder, highlighting its capacity for intricate data throughput and error correction. Functional in a multitude of data environments, this decoder can handle a variety of signal paths, ensuring robust data recovery and integrity. Its architecture is especially suited for dynamic network conditions, offering adaptability and reliability-critical factors in maintaining service quality in challenging communication scenarios. This Decoder is ideal for systems operating under diverse protocols, ensuring seamless interoperability and efficient error detection and correction. By optimizing data processing technologies, it supports high-speed data exchanges across broader channels, catering to the growing demand for superior network performance in modern telecommunication infrastructures.