All IPs > Security IP > Cryptography Cores
In today's interconnected world, the importance of secure communication and data protection cannot be overstated. Cryptography cores are a crucial subset of semiconductor IPs designed to provide foundational security solutions across a variety of electronic systems. At their core, these IPs implement complex algorithms that ensure the confidentiality, integrity, and authenticity of data being processed and exchanged.
The cryptography cores available in this category offer a diverse range of features tailored to different security needs. From symmetric-key algorithms like AES to asymmetric-key systems such as RSA and ECC, these cores ensure that systems can securely encrypt and decrypt information, protecting it from unauthorized access and tampering. By embedding these cryptographic functions directly into hardware, it becomes possible to achieve faster processing speeds and higher levels of security compared to software implementations.
These semiconductor IPs are widely used in applications where data security is paramount. This includes, but is not limited to, industries such as finance, telecommunications, and healthcare. Devices utilizing cryptography cores can range from secure payment systems, ensuring safe financial transactions, to mobile devices for secure communications, to medical devices that safeguard sensitive health information. Additionally, with the rise of the Internet of Things (IoT), cryptography cores are increasingly crucial in providing secure connections for a myriad of smart devices.
By integrating cryptography cores into your designs, you not only improve security but also future-proof your products against many potential vulnerabilities. As security threats continue to evolve, having robust cryptography solutions is essential for maintaining trust and reliability in your products and services. Whether you're developing a new application or enhancing an existing one, our category of cryptography cores offers the semiconductor IP solutions you need to meet today's stringent security demands.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Tiempo Secure's True Random Number Generator (TRNG) is a cryptographic IP core designed to infuse high levels of security in digital systems. This module is vital for generating unpredictable random numbers used across various cryptographic functions such as key generation, encryption, digital signatures, and more. The TRNG is crafted to adhere to the highest standards of randomness and security as outlined by NIST and AIS31 test suites. It supports crucial protocols in secure communications like IPsec, MACsec, and TLS/SSL while providing raw data access for AIS31 characterization and incorporating comprehensive health tests. With its ability to integrate seamlessly into existing designs, the TRNG stands as a critical element for enhancing system security. Its implementation includes wrappers for standard buses such as APB and AXI, ensuring compatibility and ease of integration into existing SoC architectures. The TRNG is a cornerstone for secure device operation, ensuring that cryptographic operations maintain their integrity and randomness, thereby safeguarding against potential security breaches in the system.
KPIT provides state-of-the-art solutions for vehicle diagnostics and aftersales service, essential for the maintenance of software-intensive vehicles. The iDART framework offers comprehensive diagnostic functions and enhances service operations through AI-guided systems. This framework facilitates the transition to a unified, future-proof diagnostic ecosystem, reducing downtime and ensuring optimal vehicle performance. KPIT's solutions streamline complex diagnostic processes, making vehicles easier to manage and repair over their lifespans, enhancing customer satisfaction and loyalty.
SphinX provides industry-standard encryption and decryption using high-performance, low-latency AES-XTS technology. Its design features independent, non-blocking encryption and decryption channels, ensuring data security is maintained without impeding processing speed or system throughput. SphinX is tailored for environments where data protection is paramount, delivering robust security capabilities while preserving system efficiency and performance.
PUFrt is a foundational security solution that equips semiconductors with hardware root key generation and storage, essential for establishing a Hardware Root of Trust. It introduces a 1024-bit PUF-based identification code and a true random number generator (TRNG) that comply with stringent cryptographic standards, enhancing data protection against diverse threats. The design includes secure OTP storage and an anti-tamper shell, providing a robust defense against physical attacks. Assured compatibility with varied architectures allows PUFrt to integrate seamlessly, offering key provisioning and securing critical data across system platforms.
Secure OTP offers advanced anti-fuse memory protection, serving as a reliable safeguard for embedded non-volatile memory. Integrating Physical Macros and Digital RTL, it provides a robust solution for sensitive data storage such as keys and boot code. With a 1024-bit PUF, Secure OTP handles data scrambling and IO shuffling, ensuring high-security protection against physical threats. Its universality in integration across multiple ASIC applications makes it an integral component in securing data within IoT devices and extending its utility to diverse markets such as PCIe and Smart TVs.
Tiempo Secure's Post-Quantum Cryptography (PQC) is designed to offer protection against emerging quantum computing threats, ensuring that cryptographic systems remain secure in the future. This cryptographic solution integrates advanced algorithms that are resilient to quantum attacks, providing a robust next-generation security layer. Key components of the PQC offering include quantum-resistant code signatures, key encapsulation mechanisms, and digital signatures, leveraging advanced algorithms such as the Leighton-Micali Hash-Based Signature Scheme, Crystals-Dilithium, and Crystals-Kyber. These mechanisms are engineered to provide future-proof security, aligning with evolving cryptographic requirements. Tailored for adaptability, PQC ensures dependable security through architecture-ready, hardware-accelerated algorithms that fit into various digital systems. This adaptability makes it suitable for applications seeking enhanced protective measures against quantum threats. With PQC, Tiempo Secure offers a forward-looking approach to securing digital assets, ensuring they are safeguarded from the potential risks posed by quantum computing advancements. This makes it an essential component for modern security strategies, providing peace of mind in a fast-evolving technological landscape.
PUFcc is a crypto coprocessor that combines a Hardware Root of Trust with a comprehensive suite of cryptographic capabilities. It integrates seamlessly into various system architectures, providing a complete security protocol solution required for IoT and AI technologies. The PUFcc leverages its foundational PUFrt's secure design while enhancing cryptographic functionality with certified algorithms. This drop-in IP module features direct memory access, enabling faster data interaction necessary for real-time applications. Particularly with its latest iteration, the PUFcc7, improvements in algorithm performance and TLS1.3 compliance demonstrate its adaptability to evolving standards.
The AES Encrypt/Decrypt module offers robust security features, accommodating 128/192/256-bit keys for both encryption and decryption tasks. This module is engineered for low latency and minimal power consumption, making it suitable for high-demand environments where security and performance are critical. The design implements Galois Field calculations using an 8-bit primitive polynomial, enabling parallel processing of key calculation and data encryption to minimize clock cycle use. The flexibility of the module is evident in its runtime programmability, ensuring that each operation can be tailored to meet specific security and performance criteria. Applications span across secure communications and any data exchange requiring high encryption standards, with the system delivering verified RTL against a broad suite of scenarios to guarantee functional integrity.
The Dynamic Neural Accelerator II Architecture (DNA-II) by EdgeCortix is a sophisticated neural network IP core structured for extensive parallelism and efficiency enhancement. Distinguished by its run-time reconfigurable interconnects between computing elements, DNA-II supports a broad spectrum of AI models, including both convolutional and transformer networks, making it suitable for diverse edge AI applications. With its scalable performance starting from 1K MACs, the DNA-II architecture integrates easily with many SoC and FPGA applications. This architecture provides a foundation for the SAKURA-II AI Accelerator, supporting up to 240 TOPS in processing capacity. The unique aspect of DNA-II is its utilization of advanced data path configurations to optimize processing parallelism and resource allocation, thereby minimizing on-chip memory bandwidth limitations. The DNA-II is particularly noted for its superior computational capabilities, ensuring that AI models operate with maximum efficiency and speed. Leveraging its patented run-time reconfigurable data paths, it significantly increases hardware performance metrics and energy efficiency. This capability not only enhances the compute power available for complex inference tasks but also reduces the power footprint, which is critical for edge-based deployments.
The THOR Toolbox is designed to provide robust NFC and UHF connectivity solutions, enabling efficient wireless communication across devices. This toolbox is crucial for developing products that require seamless integration of near-field communication and ultra-high-frequency radio tags, which are instrumental in applications such as inventory management and product tracking. THOR Toolbox facilitates easy development and integration, offering a complete set of tools necessary for prototyping and testing NFC and UHF features. It allows engineers to validate their design concepts quickly and effectively, ensuring that the final product meets all necessary specifications and standards. By utilizing the THOR Toolbox, designers can expedite the design process, minimize time-to-market, and enhance the functionality and reliability of their products. It is particularly valuable in environments where data security and seamless connectivity are paramount, ensuring that products are future-proofed for evolving standards and requirements in communication technology.
FortiCrypt is designed to provide AES protection against side-channel attacks (SCA) and fault injection attacks (FIA) without compromising on performance or latency. It utilizes sophisticated masking methods and has been rigorously tested using the Test Vector Leakage Assessment (TVLA) methodology. FortiCrypt supports various high-performance configurations, including ultra-high performance, ultra-low power, and a balanced approach that meets diverse security needs. These configurations allow for encryption of high-definition video streams on less powerful CPUs, making it ideal for a range of applications that require advanced security.
The PSA Compliant Crypto API by Tiempo Secure offers a streamlined interface for implementing cryptographic functions, ensuring robust digital security. It is a comprehensive package that simplifies cryptographic operations while adhering strictly to the Platform Security Architecture (PSA) benchmarks. Engineered for efficiency, the API provides a software library supporting both Physical Unclonable Functions (PUFs) and a True Random Number Generator with Deterministic Random Bit Generator (TRNG+DRBG). Its design ensures minimal on-chip SRAM usage, occupying only a few kilobytes, ideal for space-constrained environments. Platforms integrating this API can achieve the prestigious 'PSA Certified Storage' status, proving compliance with stringent standards. Its extensive logging options, highly optimized SHA-256, and adherence to MISRA C standards make it a robust choice for enhancing system security. This API enables secure storage of arbitrary keys using SRAM PUFs and supports the generation of 256-bit true random seeds, vital for secure operating environments. It simplifies complex security functions, making it an ideal choice for enhancing system protection across various platforms.
The 100 Gbps Polar Encoder and Decoder from IPrium is a high-speed solution designed to meet the needs of ultra-fast data transmission networks. Polar coding, known for its capacity-achieving attributes, ensures that data can be transmitted reliably even near the channel capacity limit. This encoder and decoder pair excels in providing comprehensive error correction capabilities while accommodating substantial data rates, essential for cutting-edge telecommunication networks and data centers. By implementing sophisticated polar codes, these cores manage to minimize error rates, enhancing overall communication fidelity. With applications spanning from 5G networks to data-intensive server environments, the 100 Gbps Polar Encoder and Decoder is a versatile tool for future-proofing network infrastructure. By utilizing this technology, IPrium combines high throughput with reliable error correction, catering to the evolving demands of modern digital communication frameworks.
Polar Encoders/Decoders from Creonic are designed with the latest communication standards in mind, delivering exceptional performance in error correction through polar coding techniques. Originally developed for 5G systems, polar coding offers strong error correction capabilities with high efficiency, making these cores critical for next-generation communication systems. These encoders/decoders provide a consistent performance boost by efficiently utilizing channel capacity, which is particularly beneficial in high-throughput scenarios such as wireless backhaul and cellular networks. Creonic’s implementation focuses on minimizing complexity while maximizing speed, ensuring the cores can handle demanding communication tasks without excessive processing overhead. The Polar Encoders/Decoders IP cores are packed with a rich set of features that include adjustable code rates and length, providing adaptability to various requirements. With comprehensive support for both FPGA and ASIC deployments, they offer a robust, flexible solution for those looking to enhance their existing digital communication frameworks.
Turbo Encoders/Decoders by Creonic represent key components for achieving effective forward error correction in communication systems. Utilizing turbo coding, these IP cores enhance data throughput by rapidly encoding and decoding signals, ensuring minimal error propagation and optimal data integrity. Widely used in standards like DVB-RCS2 and LTE, Turbo coding provides excellent performance gains in error correction. These cores are specifically designed to handle large volumes of data with high efficiency, allowing technologies like 4G and upcoming 5G networks to deliver their promised speeds reliably. Creonic’s Turbo Encoders/Decoders support a range of code rates, making them adaptable for various transmission conditions and enabling dynamic applications across different communication landscapes. Importantly, they incorporate advanced algorithmic techniques to accelerate processing speeds and reduce latency – essential qualities for real-time applications. Supported with a suite of testing environments and simulation models, these IP cores ensure straightforward integration into user hardware, providing considerable flexibility for both FPGA and ASIC implementation scenarios.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Creonic's LDPC Encoders/Decoders are designed to provide high-efficiency error correction for modern communication systems. These IP cores follow advanced LDPC (Low-Density Parity-Check) coding schemes to offer a balance of performance and flexibility. They are suitable for use in a plethora of standards such as DVB-S2, DVB-S2X, 5G, and CCSDS, ensuring robust data transmission across various signal conditions. The LDPC solutions by Creonic are known for their high throughput, making them fit for applications that demand speed and accuracy. Their capability to process and correct errors efficiently ensures data integrity, especially in bandwidth-critical systems. Users can expect comprehensive integration support with available design kits and simulation models that aid seamless incorporation within existing hardware platforms. With flexibility for both FPGA and ASIC implementations, Creonic's LDPC encoders and decoders come equipped with adaptive features that allow for various code rates and block lengths. This adaptability ensures that users can tailor the application to meet specific requirements, benefiting from the cores' proven reliability in delivering high-quality data communication.
Polar ID is a comprehensive biometric security solution designed for smartphones and beyond, featuring the unique ability to sense the full polarization state of light. This system enhances biometric recognition by using advanced meta-optic technology, allowing it to capture the distinctive 'polarization signature' of a human face. This capability provides a robust defense against sophisticated 3D masks and spoofing attempts, making it a leading choice for secure facial authentication. Polar ID eliminates the need for complex optical modules typical in structured light systems and does not rely on expensive time-of-flight sensors. By delivering all necessary information from a single image, Polar ID streamlines the authentication process, significantly reducing the size and cost of the system. It provides high-resolution recognition across various lighting conditions, from bright daylight to total darkness, ensuring a reliable and secure experience for users. Employing Polar ID, manufacturers can enable secure digital transactions and access controls without compromising on user experience or device aesthetics. By operating seamlessly even when users wear sunglasses or face masks, this system sets a new standard in facial recognition technology. Its compact design fits easily into the most challenging form factors, making it accessible for a wide range of mobile devices.
Post-Quantum Cryptography Processing Engine Adds support for lattice-based cryptographic operations such as ML-KEM and ML-DSA. PQPlatform-Lattice provides post-quantum support for these NIST-standardized algorithms with minimal area, and leverages an existing SHA-3 accelerator, powered by PQShield-supplied firmware. It’s designed for minimal area, and maximum compatibility, and is deployed with optional firmware-backed side-channel resistance.
The AES-XTS solution by Helion is tailored for disk encryption, leveraging the Tweakable block cipher algorithm to provide enhanced data security at the sector level on storage devices. The AES-XTS mode is designed to prevent threats like copy-and-paste or dictionary attacks and can independently encrypt and decrypt data in sector-sized blocks. This encryption core is crucial for safeguarding sensitive data on storage arrays, ensuring that identical plaintext blocks placed at different sectors result in distinct ciphertext. Helion offers a variety of AES-XTS cores to address differing data throughput needs, with capabilities ranging from less than 1Gbps to over 64Gbps, making it suitable for singular hard disks to large server arrays. Helion's AES-XTS solutions can be deployed on both ASIC and FPGA platforms, ensuring maximum performance and resource efficiency across varied technological landscapes. They support key sizes of 128-bit and 256-bit, with options for Ciphertext Stealing, adapting to diverse encryption protocols and operational environments.
The SHA-2 Crypto Engine from Tiempo Secure delivers advanced hashing functionality that is pivotal for ensuring data integrity and security in various applications. This IP core stands out for its efficient processing capabilities, supporting hashing functions like SHA-256 and SHA-224. Designed with a 1 cycle per round architecture, the SHA-2 Crypto Engine supports both the import and export of SHA-256 states, catering to even the most complex cryptographic operations. Its ability to handle any message length with bit granularity makes it versatile for wide-ranging applications. Internal padding is seamlessly handled within the IP, and for ease of integration, it comes with wrappers for standard buses such as APB and AXI. This ensures it fits well into a plethora of existing designs, making it a reliable choice for implementing digital signatures and data integrity checks. A unique feature of the SHA-2 Crypto Engine is its readiness to handle pre-padded payloads, optimizing processing without compromising on performance. It empowers developers to boost their system's security robustness while benefiting from an optimized silicon resource-to-performance ratio.
aiWare is a cutting-edge hardware solution dedicated to facilitating neural processing for automotive AI applications. As part of aiMotive’s advanced offerings, the aiWare NPU (Neural Processing Unit) provides a scalable AI inference platform optimized for cost-sensitive and multi-sensor automotive applications ranging from Level 2 to Level 4 driving automation. With its unique SDK focused on neural network optimization, aiWare offers up to 256 Effective TOPS per core, on par with leading industry efficiency benchmarks. The aiWare hardware IP integrates smoothly into automotive systems due to its ISO 26262 ASIL B certification, making it suitable for production environments requiring rigorous safety standards. Its innovative architecture utilizes both on-chip local memory and dense on-chip RAM for efficient data handling, significantly reducing external memory needs. This focus on minimizing off-chip traffic enhances the overall performance while adhering to stringent automotive requirements. Optimized for high-speed operation, aiWare can reach up to 1024 TOPS, providing flexibility across a wide range of AI workloads including CNNs, LSTMs, and RNNs. Designed for easy layout and software integration, aiWare supports essential activation and pooling functions natively, allowing maximum processing efficiency for neural networks without host CPU interference. This makes it an exemplary choice for automotive-grade AI, supporting various advanced driving capabilities and applications.
The eSi-Crypto suite from EnSilica offers an extensive range of cryptographic IPs designed to provide high-quality encryption and authentication functionalities. A standout feature of this suite is its True Random Number Generator (TRNG), which adheres to NIST 800-22 standards and ensures robust random number generation essential for secure communication. These cryptographic cores are versatile and can be easily integrated through various bus interfaces like AMBA APB/AHB and AXI.\n\nSupporting numerous algorithms such as CRYSTALS Kyber and Dilithium, ECDSA/ECC, and AES, the eSi-Crypto suite advances quantum-resilient cryptography. This feature is crucial as it prepares secure digital communications against future quantum threats. Moreover, the suite includes high-throughput solutions suitable for applications that demand both efficiency and resource optimization, like V2X communications.\n\nEnSilica's cryptographic IPs exhibit compatibility with ASIC and FPGA targets, offering low resource usage while maintaining exceptionally high throughput. The suite also encloses IPs for various SHA algorithms, ChaCha20, Poly1305, and traditional standards like RSA and TDES. This comprehensive range meeting both modern cryptographic demands ensures that data protection remains robust and flexible in diverse application scenarios.
Secure-IC's Post-Quantum Cryptography IP encompasses advanced solutions designed to counter the potential threats posed by quantum computing. This IP includes hardware accelerators and software libraries implementing lattice-based and hash-based algorithms, offering extensive protection against various side-channel attacks. With capabilities for key generation, encapsulation, and decapsulation, this solution integrates seamlessly into AMBA interfaces, ensuring secure and efficient cryptographic processes in future-proof environments.
The AndeSoft software stack provides a comprehensive suite of software components such as operating systems, Linux kernels, various libraries, and middleware. These components aim to expedite the customer's product development cycle, enabling them to focus more on application-specific requirements instead of general development concerns. The software is optimized for AndesCore processors and helps to reduce time-to-market without compromising performance.
The Cramium Personal Hardware Security Module, or PHSM, by CrossBar, is designed to address the growing need for enhanced security measures in electronic devices. By leveraging CrossBar's ReRAM technology, the PHSM offers a robust solution for secure key storage and encryption, protecting devices from unauthorized access and cyber threats. It acts as a vital component in maintaining the integrity and confidentiality of data across various applications. The module incorporates cryptographic mechanisms to create a secure environment against physical and digital attacks, ensuring that sensitive information remains protected from sophisticated hacking attempts. The intrinsic characteristics of ReRAM technology, such as its high randomness and low bit error rates, form the core of the PHSM's ability to deter potential attacks. Engineered with a focus on root of trust applications, the PHSM reinforces secure authentication processes, which are crucial in industries like automotive, medical, and IoT-based systems. The compact design aids in seamless integration within semiconductor hardware, thereby supporting diverse applications that demand rigorous security protocols.
Tiempo Secure's SHA-3 Crypto Engine is an advanced cryptographic module that offers exceptional flexibility and performance for modern security needs. Emphasizing scalability, the engine supports varying numbers of hashing rounds per clock cycle, optimizing the silicon resource usage while ensuring high throughput. One of the key features is the ability to select between fixed-length and extendable-output functions (XOF) for each message, catering to diverse application requirements. This flexibility is easily manageable through simple configuration settings, making it adaptable to specific needs. Internally, the SHA-3 engine manages message padding and allows for efficient import/export of the KECCAK-p state. The architecture is designed for integration simplicity, featuring wrappers compatible with standard bus protocols like APB and AXI, facilitating smooth incorporation into a myriad of systems. In addition to supporting SHA-3 standard functions, it accelerates the Kangaroo Twelve algorithm, offering a comprehensive suite of cryptographic tools for enhanced data security and integrity across various applications.
FortiMac delivers robust security for HMAC SHA2 implementations by offering powerful protection against both side-channel (SC) and fault injection (FI) attacks. It employs the Threshold Implementation paradigm to ensure high-level security with a minimal gate footprint. FortiMac's core technology has undergone extensive analytical and physical validation to guarantee its effectiveness against modern threats. It is an ideal choice for applications requiring strong and reliable cryptographic protection.
The Securyzr iSSP, or Integrated Security Services Platform, is a robust lifecycle management solution tailored for secure deployment, supply, and management of embedded devices. This platform facilitates zero-touch security lifecycle services such as provisioning, firmware updates, and security monitoring, thus ensuring consistent and reliable security from chip manufacture to device decommissioning. It integrates both a secure element (iSE) and a server component, creating a comprehensive chip-to-cloud security solution capable of functioning on public and private cloud environments.
The FortiPKA-RISC-V serves as a highly efficient public key accelerator that offloads intense computational tasks from the main CPU. It features a unique technology that enhances performance by eliminating unnecessary data transformations, thus providing a small footprint but robust performance. This makes it suitable for applications such as networks, communications, and embedded systems where efficiency and speed are essential. The accelerator supports multiple cryptographic algorithms and interfaces, ensuring broad compatibility with various systems and technologies.
The AES Encryption for RFID applications is engineered to provide robust security for data in RFID communications. Utilizing Advanced Encryption Standard (AES) techniques, it offers a secure and efficient mechanism for protecting sensitive information transmitted in RFID systems. This encryption solution is ideal for applications where data integrity and confidentiality are paramount, protecting against unauthorized access and ensuring secure wireless transactions.
The AES (standard modes) product from Helion offers a robust encryption solution featuring the Advanced Encryption Standard (AES) algorithm, a 128-bit block cipher known for its efficiency and security. With key sizes of 128, 192, and 256 bits, the AES algorithm complies with NIST standards and is recognized globally for securing sensitive information. This product caters to applications necessitating rapid data processing and heightened security, such as in IPsec, wireless communication, and storage encryption. Helion's AES cores are crafted to deliver optimal performance across a vast array of settings, including both ASIC and FPGA implementations. The cores are designed with scalability in mind, accommodating applications from minimal data rates up to multi-gigabit transmission speeds. Thanks to their architecture, these cores maintain high usability, enabling easy adoption and integration into user systems without excessive resource allocation. Helion's AES suite includes numerous versions tailored to meet varying data transmission needs, ensuring adaptability in resource-constrained environments. Users benefit from the choice of low-power, space-efficient, and high-speed solutions, supporting a wide range of encryption requirements. These cores are also compatible with an array of programmable technologies, reaffirming their utility across diverse platforms, from commercial applications to government-level data protection setups.
Post-Quantum Security Subsystem A cryptographic subsystem, designed to provide cryptographic services. These services include post-quantum signature generation, verification, and secure key establishment. PQPlatform-SubSys uses its built-in CPU independently from the surrounding system, allowing cryptographic services to be offloaded efficiently from the system processor.
The Quantum Resistant Encryption Core by Crypto Quantique is engineered to provide unparalleled security for IoT devices through its integration of quantum technology. This core is designed to defend against the potential future threats posed by quantum computers, ensuring long-term data security. It utilizes advanced quantum algorithms that offer higher levels of encryption compared to traditional methods, making it highly resilient to attempts at unauthorized access. A major advantage of this encryption core lies in its capacity to offer both future-proof and adaptable security protocols. These features are essential for modern IoT devices, which require not only resistant infrastructures to potential quantum-level risks but also flexibility in deployment across various platforms and devices. Its design ensures that it can be embedded into a wide variety of IoT ecosystems, providing security that is scalable and responsive to an evolving threat landscape. Furthermore, this core is distinguished by its ability to seamlessly integrate with existing hardware setups. Crypto Quantique ensures that their encryption core is compatible with numerous process nodes and foundries, thereby offering broad support for different manufacturing requirements and enhancing the security framework of any digital platform. Its robust design and high compatibility make it a valuable asset for any organization aiming to protect sensitive information sustainably and effectively.
Post-Quantum Cryptography Processing Engine Adds support for lattice-based cryptographic operations such as ML-KEM and ML-DSA. PQPlatform-Lattice provides post-quantum support for these NIST-standardized algorithms with minimal area, and leverages an existing SHA-3 accelerator, powered by PQShield-supplied firmware. It’s designed for minimal area, and maximum compatibility, and is deployed with optional firmware-backed side-channel resistance.
The SOQPSK-TG LDPC Modulator by IPrium offers superior modulation capabilities, integrating Selectable Offset Quadrature Phase-Shift Keying with Turbo-LDPC coding. This combination is especially beneficial for aerospace telemetry where high efficiency and robustness are required for data transmission over long distances. This sophisticated modulator supports reliable data modulation, essential for maintaining the integrity of data in critical communication paths such as those between spacecraft and ground stations. Its design focuses on achieving high spectral efficiency and power efficiency, optimizing frequency utilization while minimizing power consumption. Spacecraft communications benefit greatly from this modulator due to its error correction performance, contributing to mission safety and success. IPrium's dedication to high-performance standards ensures that this product not only meets but exceeds industry expectations for aerospace communication systems.
This Hash Function IP embodies robust cryptographic capabilities, supporting MD5, SHA-1, and SHA-256 algorithms. Ideal for applications requiring data integrity checks and secure transmissions, it is designed to minimize resource consumption while maximizing speed. This IP is well-suited to a wide variety of digital environments, ensuring data accuracy and security in everyday operations.
Post-quantum Software Development Kit Provides easy-to-use software implementations of both post-quantum and classical cryptographic primitives. It’s designed with prototyping and experimentation in mind, consisting of an integration of PQShield’s PQCryptoLib library with two popular high-level cryptography libraries: OpenSSL and mbedTLS. OpenSSL: a widely-adopted secure-communication library mbedTLS: primarily intended for use in embedded system and IoT deployments
The Yuzhen 600 RFID Chip by T-Head is a high-efficiency chip designed for radio-frequency identification applications. This chip is equipped with advanced features to facilitate reliable and fast data capture in RFID systems. It supports a wide range of operating frequencies, making it versatile for various application environments, from logistics to retail management.\n\nThe Yuzhen 600 is crafted with energy efficiency in mind, ensuring prolonged operation and minimal power consumption. Its architecture allows for quick read and write cycles, enhancing throughput and operational efficiency in high-demand settings. This makes it ideal for inventory tracking, asset management, and supply chain logistics.\n\nFurthermore, the Yuzhen 600 offers robust security features to protect data integrity and privacy, a crucial aspect in high-stakes environments where sensitive information is processed. The chip's adaptability to diverse RFID protocols makes it a flexible solution for integrators looking for versatile RFID products.
The DAES processor serves as a robust cryptographic co-processor designed to support the Rijndael algorithm, which is crucial for advanced encryption standards. Capable of handling 128-bit and 256-bit key lengths, this unit provides robust security measures for various cipher block modes such as ECB, CBC, CFB, OFB, and CTR. Integrated with internal key expansion modules, the DAES ensures efficient cryptographic operations while maintaining secure key management. Its architecture supports integration with APB, AHB, and AXI buses, which simplifies its deployment across diverse silicon environments and enhances its applicability in systems necessitating high levels of security. This cryptographic unit is ideal for applications in secure communications, defense, and areas requiring data confidentiality and integrity. The DAES's tailored encryption capabilities make it a formidable choice for developers seeking to bolster system security and manage complex data encryption processes.
CoMira Solutions' MACSec IP is designed to provide robust security and integrity to networking applications, adhering to the IEEE 802.1AE-2006 MACSec standard. This IP enables secure and reliable transmission of data over LAN, safeguarding against disruption and unauthorized interception. Built with a time-division multiplexed cut-through architecture, the IP offers high throughput for multiple channels while maintaining synchronization-independent operation, thereby providing efficiency without compromising on security. Features include support for FIPS-compliant encryption algorithms, flexible multi-port operation, and customizable security associations, making it an ideal solution for secure networking environments.
The SFA 100 is designed for handling data processing tasks at the edge of IoT networks. This component is built to efficiently process data streams, making it ideal for edge computing environments where low latency and high throughput are crucial. It plays a vital role in enhancing the performance and efficiency of IoT networks by managing data processing directly at the source, thus reducing the need for data transmission back to central servers.
Post-Quantum Cryptography Processor PQPlatform-CoPro (PQP-HW-COP) adds PQShield’s state-of-the-art post-quantum cryptography (PQC) to your security sub-system, with optional side-channel countermeasures (SCA). PQPlatform-CoPro can be optimized for minimum area as part of an existing security sub-system. PQPlatform-CoPro is designed to be run by an existing CPU in your security system, using PQShield’s supplied firmware.
The AES Encryption Core is a highly efficient IP core designed for robust security applications. This core is widely recognized for its versatility and has been proven in both FPGA and ASIC environments repeatedly. With nearly 60 licensing instances, it stands as a trusted solution for secure data encryption across multiple platforms. Designed with precision, the AES core is NIST certified and adheres to stringent security protocols, making it suitable for applications that require top-tier data protection. It integrates seamlessly into security frameworks, delivering reliable encryption that withstands extensive evaluation and testing. By leveraging advanced encryption methodologies, this IP core ensures comprehensive data security for various industrial applications. It is adept at managing encrypted data efficiently, making it an ideal choice for sectors demanding fast, reliable encryption without compromising security standards.
The iShield Key is an advanced hardware authentication tool designed to protect digital identities with the utmost security. Combining the robustness of FIDO security standards with MIFARE DESFire EV3 technology, the iShield Key offers unparalleled access control and authentication capabilities. It is crafted to meet the diverse needs of modern user authentication applications that extend beyond traditional methods. Designed for flexibility, the iShield Key provides users with enhanced security options, safeguarding against online threats such as phishing and account takeovers. Its hardware-based protection ensures that sensitive information, such as passwords and private keys, remain secure from tampering and unauthorized access. Perfect for both personal and enterprise use, the iShield Key seamlessly integrates with existing systems, offering a plug-and-play solution for enhanced cybersecurity. Its user-friendly design ensures that security measures can be implemented efficiently without the need for extensive technical knowledge, making it a valuable tool in the digital security arsenal.
ReRAM Secure Keys by CrossBar provide a cutting-edge solution for applications requiring a robust security framework. This technology leverages the unique characteristics of ReRAM technology to generate cryptographic keys that serve as the foundation for secure device operations. These keys function as Digital Fingerprints, crucial in preventing unauthorized access and copying. ReRAM Secure Keys technology surpasses traditional SRAM-based security solutions, offering high randomness, low error rates, and strong resistance to tampering. It is particularly well-suited for devices in IoT, computing, and infrastructure where security threats are prevalent and systems require stringent protective measures. This solution enhances device root of trust, a vital component for authentication and encryption processes. Its ability to securely maintain cryptographic keys even in foundry nodes smaller than 28nm underscores its versatility and strength in the industry's pursuit of high-security standards across various electronic applications.
Helion's SHA hashing cores offer powerful solutions for secure data verification needs, featuring implementation of widely recognized hash functions such as SHA-1 and the SHA-2 family, which includes SHA-224, SHA-256, SHA-384, and SHA-512. These one-way cryptographic functions generate fixed-length message digests for data verification, ensuring data integrity and authentication in digital signatures, security protocols like IPsec, and TLS/SSL. These cores are built to cater to different processing demands, providing both high-performance and resource-efficient options. For applications that require rapid processing with minimal area impact, Helion's FAST hashing core family achieves data rates up to 4Gbps. Alternatively, their TINY hashing core family is designed to handle low power and data rate applications, making it suitable for less demanding environments with space constraints. Helion's SHA hashing solutions are versatile, supporting various platforms including Xilinx, Altera, and Microsemi FPGAs, as well as ASIC implementations. Their efficient architecture ensures ease of integration without compromising on performance, catering to a range of applications from simple data integrity checks to complex cryptographic procedures.
The ECC Verification Core delivers high-performance verification of elliptic curve cryptographic operations, ensuring superior data protection. Central to modern public key infrastructures, this core supports advanced elliptic curves and is equipped for efficient elliptic curve digital signature operations. Incorporating this core into security systems grants stakeholders the advantage of reliable data verification processes across sectors like telecommunications, military, and internet services. This core facilitates resilient signature verification, essential for applications that handle sensitive and private communications. Through detailed point multiplication processes and swift data throughput, the ECC Verification Core maintains operational efficiency while upholding rigorous security protocols. It is a strategic asset for organizations looking to elevate their security postures, providing robust, scalable solutions to authenticate data and digital identities.
ReRAM as FTP (Few-Time Programmable) and OTP (One-Time Programmable) Memory from CrossBar introduces a flexible approach to non-volatile memory that suits a variety of secure application needs. This technology leverages the company's advanced ReRAM cells to offer a memory solution that combines the capabilities of high-performance, multi-time programmable memory with the added benefits of FTP and OTP adaptability. This adaptability allows for versatile memory partitioning, enabling the use of secure physical unclonable function (PUF) keys within the same memory architecture. Such features make it an excellent choice for applications in automotive, industrial, and consumer electronics where data security and endurance are paramount. Furthermore, the ReRAM-based FTP/OTP memory is constructed to be compatible across various semiconductor processes, ensuring easy integration into existing and new chip designs. This cross-compatibility reduces the overall die area and cost, an advantage for businesses looking to deploy large volumes of such memory solutions at a lower cost without compromising on performance or security.