All IPs > Security IP
Security IPs are an integral category within the semiconductor industry focusing on the protection of electronic data and hardware. As technological advancements continue to proliferate across critical sectors like finance, healthcare, and automotive, securing data and hardware has never been more paramount. Security IPs are designed to provide essential security features such as encryption, secure communications, and access control to safeguard sensitive information and devices from unauthorized access and cyber threats.
Within the Security IP category, you will find robust offerings that include both hardware and software-based solutions tailored to various security needs. Content Protection Software enables secure data transmission and protects digital content from piracy and unauthorized distribution. Cryptography Cores and Cryptography Software Libraries offer foundational tools for implementing strong encryption algorithms that are crucial for securing communications and data storage.
Embedded Security Modules are integrated within semiconductor devices to facilitate secure data processing and enhance trust in device operations by preventing code tampering and unauthorized hardware modification. Platform Security solutions encompass a broad range of protective measures designed to secure the entire hardware and software ecosystem, ensuring that devices are safe from potential vulnerabilities at every level.
Additionally, Security Protocol Accelerators and Security Subsystems act as dedicated processing units to efficiently handle complex security algorithms and protocols, enhancing the performance of security operations while reducing the burden on primary CPUs. With an unpredictable security landscape, leveraging a range of specialized Security IPs allows designers and engineers to build robust, secure, and reliable semiconductor solutions that can withstand evolving cyber threats.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
Tiempo Secure's True Random Number Generator (TRNG) is a cryptographic IP core designed to infuse high levels of security in digital systems. This module is vital for generating unpredictable random numbers used across various cryptographic functions such as key generation, encryption, digital signatures, and more. The TRNG is crafted to adhere to the highest standards of randomness and security as outlined by NIST and AIS31 test suites. It supports crucial protocols in secure communications like IPsec, MACsec, and TLS/SSL while providing raw data access for AIS31 characterization and incorporating comprehensive health tests. With its ability to integrate seamlessly into existing designs, the TRNG stands as a critical element for enhancing system security. Its implementation includes wrappers for standard buses such as APB and AXI, ensuring compatibility and ease of integration into existing SoC architectures. The TRNG is a cornerstone for secure device operation, ensuring that cryptographic operations maintain their integrity and randomness, thereby safeguarding against potential security breaches in the system.
KPIT offers a comprehensive solution for Autonomous Driving and Advanced Driver Assistance Systems. This suite facilitates the widespread adoption of Level 3 and above autonomy in vehicles, providing high safety standards through robust testing and validation frameworks. The integration of AI-driven decision-making extends beyond perception to enhance the intelligence of autonomous systems. With a commitment to addressing existing challenges such as localization issues, AI limitations, and validation fragmentation, KPIT empowers automakers to produce vehicles that are both highly autonomous and reliable.
KPIT excels at providing AUTOSAR solutions that streamline software integration and improve vehicle architecture. The company's focus on middleware development ensures efficient application deployment and integration within both classic and adaptive AUTOSAR frameworks. KPIT's solutions enable quick software updates, robust validation processes, and cost-effective production timelines, essential for the evolving landscape of Software-Defined Vehicles (SDVs).
KPIT provides state-of-the-art solutions for vehicle diagnostics and aftersales service, essential for the maintenance of software-intensive vehicles. The iDART framework offers comprehensive diagnostic functions and enhances service operations through AI-guided systems. This framework facilitates the transition to a unified, future-proof diagnostic ecosystem, reducing downtime and ensuring optimal vehicle performance. KPIT's solutions streamline complex diagnostic processes, making vehicles easier to manage and repair over their lifespans, enhancing customer satisfaction and loyalty.
The AHB-Lite APB4 Bridge facilitates connectivity between different bus protocols, specifically the AMBA 3 AHB-Lite and AMBA APB v2.0. As a soft IP, it is parameterized, making it adaptable to various design specifications. This bridge is crucial in systems requiring efficient data transport between high-speed and low-power subsystems, providing a seamless communication interface.
Origin E1 neural engines are expertly adjusted for networks that are typically employed in always-on applications. These include devices such as home appliances, smartphones, and edge nodes requiring around 1 TOPS performance. This focused optimization makes the E1 LittleNPU processors particularly suitable for cost- and area-sensitive applications, making efficient use of energy and reducing processing latency to negligible levels. The design also incorporates a power-efficient architecture that maintains low power consumption while handling always-sensing data operations. This enables continuous sampling and analysis of visual information without compromising on efficiency or user privacy. Additionally, the architecture is rooted in Expedera's packet-based design which allows for parallel execution across layers, optimizing performance and resource utilization. Market-leading efficiency with up to 18 TOPS/W further underlines Origin E1's capacity to deliver outstanding AI performance with minimal resources. The processor supports standard and proprietary neural network operations, ensuring versatility in its applications. Importantly, it accommodates a comprehensive software stack that includes an array of tools such as compilers and quantizers to facilitate deployment in diverse use cases without requiring extensive re-designs. Its application has already seen it deployed in over 10 million devices worldwide, in various consumer technology formats.
Spec-TRACER is an integrated requirements lifecycle management application, purpose-built for FPGA and ASIC design environments. It supports the comprehensive management of design specifications and facilitates traceability across the development process, from initial specification capture through verification. This tool is invaluable in projects requiring stringent accountability and regulatory compliance, as seen in aerospace and automotive sectors. It enhances project consistency by ensuring that all design requirements are traceable, verifiable, and adhered to throughout the development phase. With features that allow for detailed analysis, reporting, and change management, Spec-TRACER simplifies the complexity of managing design requirements. Teams can achieve enhanced coordination and transparency, verifying that all specifications are met and documented appropriately, thus utilizing thorough and documented processes for effective project management.
The RV12 RISC-V Processor is a versatile, highly configurable single-issue CPU designed for the embedded market, adhering to the RV32I and RV64I RISC-V instructions. This processor implements a Harvard architecture, enabling simultaneous access to instruction and data memory, enhancing overall performance. The RV12 is part of Roa Logic's extensive CPU family, which is characterized by flexibility and underpinning efficient resource utilization for embedded systems.
SphinX provides industry-standard encryption and decryption using high-performance, low-latency AES-XTS technology. Its design features independent, non-blocking encryption and decryption channels, ensuring data security is maintained without impeding processing speed or system throughput. SphinX is tailored for environments where data protection is paramount, delivering robust security capabilities while preserving system efficiency and performance.
PUFrt is a foundational security solution that equips semiconductors with hardware root key generation and storage, essential for establishing a Hardware Root of Trust. It introduces a 1024-bit PUF-based identification code and a true random number generator (TRNG) that comply with stringent cryptographic standards, enhancing data protection against diverse threats. The design includes secure OTP storage and an anti-tamper shell, providing a robust defense against physical attacks. Assured compatibility with varied architectures allows PUFrt to integrate seamlessly, offering key provisioning and securing critical data across system platforms.
The AHB-Lite Multilayer Switch is engineered to provide a high-performance, low-latency interconnect fabric capable of supporting numerous bus masters and slaves. This switch is essential in complex system architectures where multiple data paths need to be managed efficiently simultaneously, ensuring seamless data throughput and reduced bottlenecks in system operations.
Secure OTP offers advanced anti-fuse memory protection, serving as a reliable safeguard for embedded non-volatile memory. Integrating Physical Macros and Digital RTL, it provides a robust solution for sensitive data storage such as keys and boot code. With a 1024-bit PUF, Secure OTP handles data scrambling and IO shuffling, ensuring high-security protection against physical threats. Its universality in integration across multiple ASIC applications makes it an integral component in securing data within IoT devices and extending its utility to diverse markets such as PCIe and Smart TVs.
Tiempo Secure's Post-Quantum Cryptography (PQC) is designed to offer protection against emerging quantum computing threats, ensuring that cryptographic systems remain secure in the future. This cryptographic solution integrates advanced algorithms that are resilient to quantum attacks, providing a robust next-generation security layer. Key components of the PQC offering include quantum-resistant code signatures, key encapsulation mechanisms, and digital signatures, leveraging advanced algorithms such as the Leighton-Micali Hash-Based Signature Scheme, Crystals-Dilithium, and Crystals-Kyber. These mechanisms are engineered to provide future-proof security, aligning with evolving cryptographic requirements. Tailored for adaptability, PQC ensures dependable security through architecture-ready, hardware-accelerated algorithms that fit into various digital systems. This adaptability makes it suitable for applications seeking enhanced protective measures against quantum threats. With PQC, Tiempo Secure offers a forward-looking approach to securing digital assets, ensuring they are safeguarded from the potential risks posed by quantum computing advancements. This makes it an essential component for modern security strategies, providing peace of mind in a fast-evolving technological landscape.
PUFcc is a crypto coprocessor that combines a Hardware Root of Trust with a comprehensive suite of cryptographic capabilities. It integrates seamlessly into various system architectures, providing a complete security protocol solution required for IoT and AI technologies. The PUFcc leverages its foundational PUFrt's secure design while enhancing cryptographic functionality with certified algorithms. This drop-in IP module features direct memory access, enabling faster data interaction necessary for real-time applications. Particularly with its latest iteration, the PUFcc7, improvements in algorithm performance and TLS1.3 compliance demonstrate its adaptability to evolving standards.
The AES Encrypt/Decrypt module offers robust security features, accommodating 128/192/256-bit keys for both encryption and decryption tasks. This module is engineered for low latency and minimal power consumption, making it suitable for high-demand environments where security and performance are critical. The design implements Galois Field calculations using an 8-bit primitive polynomial, enabling parallel processing of key calculation and data encryption to minimize clock cycle use. The flexibility of the module is evident in its runtime programmability, ensuring that each operation can be tailored to meet specific security and performance criteria. Applications span across secure communications and any data exchange requiring high encryption standards, with the system delivering verified RTL against a broad suite of scenarios to guarantee functional integrity.
Post-Quantum Software Library General purpose FIPS 140-3 certified cryptographic library for a wide variety of applications. PQCryptoLib is designed to provide the latest standardized post-quantum and classical algorithms in a software environment. With a configurable, secure and easy to use API, it’s optimized for crypto-agility, particularly when it comes to FIPS compliant hybrid solutions and protecting against harvest-now-decrypt-later attacks. The goal of PQCryptoLib is to help organizations transition to quantum resistance in a manageable, easy-to-integrate solution.
Secure-IC's Secure Protocol Engines provide high-performance IP blocks aimed at offloading network and security processing tasks. These engines are designed to efficiently accelerate cryptographic operations within both FPGA and ASIC environments. They allow for seamless integration into existing security architectures, facilitating enhanced data protection and processing speed, which are essential in modern high-performance computing scenarios.
xT CDx is an advanced genomic profiling solution used for comprehensive tumor and normal matched testing in oncology. With a focus on solid tumors, xT CDx leverages extensive gene coverage to aid in clinical decision-making. The system utilizes high-depth sequencing to provide actionable insights, aligning genomic findings with targeted therapy options. The platform is renowned for its substantial coverage of exons and is accredited for detecting a wide array of variants that contribute significantly to personalized medicine. As an in vitro diagnostic system, xT CDx is designed to serve as a companion diagnostic tool for oncologists, particularly in tailoring treatments that align with existing therapeutic guidelines. Its sophisticated analytical capabilities ensure that oncologists have the support they need to match patient profiles with clinical trials and approved treatments promptly. This facilitates a genomic-centric approach, integrating DNA sequencing insights into the broader clinical workflow. Incorporating both tumor and normal tissue comparisons, xT CDx is able to discern hereditary traits that might influence cancer treatment. This dual-approach testing enhances the diagnosis accuracy and optimizes treatment pathways, setting a new standard in oncology precision testing.
The Dynamic Neural Accelerator II Architecture (DNA-II) by EdgeCortix is a sophisticated neural network IP core structured for extensive parallelism and efficiency enhancement. Distinguished by its run-time reconfigurable interconnects between computing elements, DNA-II supports a broad spectrum of AI models, including both convolutional and transformer networks, making it suitable for diverse edge AI applications. With its scalable performance starting from 1K MACs, the DNA-II architecture integrates easily with many SoC and FPGA applications. This architecture provides a foundation for the SAKURA-II AI Accelerator, supporting up to 240 TOPS in processing capacity. The unique aspect of DNA-II is its utilization of advanced data path configurations to optimize processing parallelism and resource allocation, thereby minimizing on-chip memory bandwidth limitations. The DNA-II is particularly noted for its superior computational capabilities, ensuring that AI models operate with maximum efficiency and speed. Leveraging its patented run-time reconfigurable data paths, it significantly increases hardware performance metrics and energy efficiency. This capability not only enhances the compute power available for complex inference tasks but also reduces the power footprint, which is critical for edge-based deployments.
The THOR Toolbox is designed to provide robust NFC and UHF connectivity solutions, enabling efficient wireless communication across devices. This toolbox is crucial for developing products that require seamless integration of near-field communication and ultra-high-frequency radio tags, which are instrumental in applications such as inventory management and product tracking. THOR Toolbox facilitates easy development and integration, offering a complete set of tools necessary for prototyping and testing NFC and UHF features. It allows engineers to validate their design concepts quickly and effectively, ensuring that the final product meets all necessary specifications and standards. By utilizing the THOR Toolbox, designers can expedite the design process, minimize time-to-market, and enhance the functionality and reliability of their products. It is particularly valuable in environments where data security and seamless connectivity are paramount, ensuring that products are future-proofed for evolving standards and requirements in communication technology.
The Aeonic Integrated Droop Response System is designed to enhance droop and DVFS response for integrated circuits. It includes multi-threshold droop detection and fast adaptation times, ensuring power savings and optimal system performance. This technology provides extensive observability and integrates standard interfaces like APB & JTAG, aiding silicon health management by delivering data-driven insights for lifecycle analytics.
Post-quantum cryptography library for memory-constrained platforms PQCryptoLib-Embedded is a version of PQCryptoLib, PQShield’s library of post-quantum cryptographic algorithms, which is designed for microcontrollers or memory-constrained platforms. The library is highly configurable at build time, which means binary size and memory footprint can be minimized, making this product ideal for constrained devices. Efficiency is important in implementing ML-DSA and ML-KEM, especially for devices or networks requiring quantum-safe TLS communication such as in IoT environment. As a standard software library, PQCryptoLib-Embedded is a versatile tool for developing post-quantum protocols in memory-constrained situations.
The PSA Compliant Crypto API by Tiempo Secure offers a streamlined interface for implementing cryptographic functions, ensuring robust digital security. It is a comprehensive package that simplifies cryptographic operations while adhering strictly to the Platform Security Architecture (PSA) benchmarks. Engineered for efficiency, the API provides a software library supporting both Physical Unclonable Functions (PUFs) and a True Random Number Generator with Deterministic Random Bit Generator (TRNG+DRBG). Its design ensures minimal on-chip SRAM usage, occupying only a few kilobytes, ideal for space-constrained environments. Platforms integrating this API can achieve the prestigious 'PSA Certified Storage' status, proving compliance with stringent standards. Its extensive logging options, highly optimized SHA-256, and adherence to MISRA C standards make it a robust choice for enhancing system security. This API enables secure storage of arbitrary keys using SRAM PUFs and supports the generation of 256-bit true random seeds, vital for secure operating environments. It simplifies complex security functions, making it an ideal choice for enhancing system protection across various platforms.
Topaz FPGAs from Efinix are designed for volume applications where performance and cost-effectiveness are paramount. Built on their distinctive Quantum® compute fabric, Topaz devices offer an efficient architecture that balances logic resource availability with power minimization. Suitable for a plethora of applications from machine vision to wireless communication, these FPGAs are characterized by their robust protocol support, including PCIe Gen3, MIPI D-PHY, and various Ethernet configurations. One of the standout features of Topaz FPGAs is their flexibility. These devices can be effortlessly adapted into systems requiring seamless high-speed data management and integration. This adaptability is further enhanced by the extensive logic resource options, which allow increased innovation and the ability to add new features without extensive redesigns. Topaz FPGAs also offer product longevity, thriving in industries where extended lifecycle support is necessary. Efinix ensures ongoing support until at least 2045, making these FPGAs a reliable choice for projects aiming for enduring market presence. Among the key sectors benefiting from Topaz's flexibility are medical imaging and industrial control, where precision and reliability are critical. Moreover, Efinix facilitates migration from Topaz to Titanium for projects requiring enhanced performance, ensuring scalability and minimizing redesign efforts. With varying BGA packages available, Topaz FPGAs provide comprehensive solutions that cater to both the technological needs and strategic goals of enterprises.
FortiCrypt is designed to provide AES protection against side-channel attacks (SCA) and fault injection attacks (FIA) without compromising on performance or latency. It utilizes sophisticated masking methods and has been rigorously tested using the Test Vector Leakage Assessment (TVLA) methodology. FortiCrypt supports various high-performance configurations, including ultra-high performance, ultra-low power, and a balanced approach that meets diverse security needs. These configurations allow for encryption of high-definition video streams on less powerful CPUs, making it ideal for a range of applications that require advanced security.
The PLIC (Platform-Level Interrupt Controller) is a fully compliant RISC-V IP designed to manage multiple interrupt sources within a system. This feature-rich controller is configurable, allowing it to be tailored to specific system requirements while maintaining compliance with RISC-V architectural standards. Its flexibility and capability to prioritize interrupt handling ensure efficient processing, which is crucial for high-performance computing environments.
The 100 Gbps Polar Encoder and Decoder from IPrium is a high-speed solution designed to meet the needs of ultra-fast data transmission networks. Polar coding, known for its capacity-achieving attributes, ensures that data can be transmitted reliably even near the channel capacity limit. This encoder and decoder pair excels in providing comprehensive error correction capabilities while accommodating substantial data rates, essential for cutting-edge telecommunication networks and data centers. By implementing sophisticated polar codes, these cores manage to minimize error rates, enhancing overall communication fidelity. With applications spanning from 5G networks to data-intensive server environments, the 100 Gbps Polar Encoder and Decoder is a versatile tool for future-proofing network infrastructure. By utilizing this technology, IPrium combines high throughput with reliable error correction, catering to the evolving demands of modern digital communication frameworks.
Polar Encoders/Decoders from Creonic are designed with the latest communication standards in mind, delivering exceptional performance in error correction through polar coding techniques. Originally developed for 5G systems, polar coding offers strong error correction capabilities with high efficiency, making these cores critical for next-generation communication systems. These encoders/decoders provide a consistent performance boost by efficiently utilizing channel capacity, which is particularly beneficial in high-throughput scenarios such as wireless backhaul and cellular networks. Creonic’s implementation focuses on minimizing complexity while maximizing speed, ensuring the cores can handle demanding communication tasks without excessive processing overhead. The Polar Encoders/Decoders IP cores are packed with a rich set of features that include adjustable code rates and length, providing adaptability to various requirements. With comprehensive support for both FPGA and ASIC deployments, they offer a robust, flexible solution for those looking to enhance their existing digital communication frameworks.
Turbo Encoders/Decoders by Creonic represent key components for achieving effective forward error correction in communication systems. Utilizing turbo coding, these IP cores enhance data throughput by rapidly encoding and decoding signals, ensuring minimal error propagation and optimal data integrity. Widely used in standards like DVB-RCS2 and LTE, Turbo coding provides excellent performance gains in error correction. These cores are specifically designed to handle large volumes of data with high efficiency, allowing technologies like 4G and upcoming 5G networks to deliver their promised speeds reliably. Creonic’s Turbo Encoders/Decoders support a range of code rates, making them adaptable for various transmission conditions and enabling dynamic applications across different communication landscapes. Importantly, they incorporate advanced algorithmic techniques to accelerate processing speeds and reduce latency – essential qualities for real-time applications. Supported with a suite of testing environments and simulation models, these IP cores ensure straightforward integration into user hardware, providing considerable flexibility for both FPGA and ASIC implementation scenarios.
The ULYSS MCU range from Cortus is a powerful suite of automotive microcontrollers designed to address the complex demands of modern automotive applications. These MCUs are anchored by a highly optimized 32/64-bit RISC-V architecture, delivering impressive performance levels from 120MHz to 1.5GHz, making them suitable for a variety of automotive functions such as body control, safety systems, and infotainment. ULYSS MCUs are engineered to accommodate extensive application domains, providing reliability and efficiency within harsh automotive environments. They feature advanced processing capabilities and are designed to integrate seamlessly into various automotive systems, offering developers a versatile platform for building next-generation automotive solutions. The ULYSS MCU family stands out for its scalability and adaptability, enabling manufacturers to design robust automotive electronics tailored to specific needs while ensuring cost-effectiveness. With their support for a wide range of automotive networking and control applications, ULYSS MCUs are pivotal in the development of reliable, state-of-the-art automotive systems.
The Alcora V-by-One HS is a compact and efficient FMC daughter card that brings the V-by-One HS interface to any FPGA development board with high-speed transceivers. Supporting up to 16 RX and TX lanes when combining two cards, Alcora excels in transmitting high-resolution video signals, accommodating resolutions up to 4K at 120Hz or 8K at 30Hz. Alcora's design is flexible, available with either 51-pin or 41-pin headers, catering to different setup requirements. It includes two clock generators to sysnthesize reference clocks for the transceivers, ensuring reduced jitter on recovered RX clocks. The V-by-One HS technology is perfect for high-frame-rate video applications in the flat panel display sector. This versatile card is targeted at manufacturers and developers looking to implement high-speed, high-quality video interfaces within their products. Its robust design and high performance make it an excellent choice for embedding into video-centric FPGA applications, ensuring stellar performance in visually demanding environments.
Post-Quantum Cryptography Processing Engine Adds support for lattice-based cryptographic operations such as ML-KEM and ML-DSA. PQPlatform-Lattice provides post-quantum support for these NIST-standardized algorithms with minimal area, and leverages an existing SHA-3 accelerator, powered by PQShield-supplied firmware. It’s designed for minimal area, and maximum compatibility, and is deployed with optional firmware-backed side-channel resistance.
The ATEK367P4 functions as a versatile phase shifter component designed for RF systems working between 2 GHz to 4 GHz. This analog phase shifter provides an extensive phase range adjustable from 0 to 375 degrees, maximizing flexibility in phase alignment applications. It has a low insertion loss of 3 dB, ensuring minimal signal degradation during the shifting process. Encased in a 4×4 mm QFN package, it provides a compact footprint, enhancing its usability in space-constrained designs such as phased array antennas and electronic warfare systems. The phase shifter operates with variable control voltage, offering ease of integration with existing signal processing frameworks. ATEK367P4 is integral for applications demanding precise phase adjustments, notably in aerospace and defense communication systems where accuracy and agility are imperative. Its design facilitates seamless integration, ensuring reliability and performance consistency in complex signal processing tasks.
DolphinWare IPs is a versatile portfolio of intellectual property solutions that enable efficient SoC design. This collection includes various control logic components such as FIFO, arbiter, and arithmetic components like math operators and converters. In addition, the logic components span counters, registers, and multiplexers, providing essential functionalities for diverse industrial applications. The IPs in this lineup are meticulously designed to ensure data integrity, supported by robust verification IPs for AXI4, APB, SD4.0, and more. This comprehensive suite meets the stringent demands of modern electronic designs, facilitating seamless integration into existing design paradigms. Beyond their broad functionality, DolphinWare’s offerings are fundamental to applications requiring specific control logic and data integrity solutions, making them indispensable for enterprises looking to modernize or expand their product offerings while ensuring compliance with industry standards.
Creonic's LDPC Encoders/Decoders are designed to provide high-efficiency error correction for modern communication systems. These IP cores follow advanced LDPC (Low-Density Parity-Check) coding schemes to offer a balance of performance and flexibility. They are suitable for use in a plethora of standards such as DVB-S2, DVB-S2X, 5G, and CCSDS, ensuring robust data transmission across various signal conditions. The LDPC solutions by Creonic are known for their high throughput, making them fit for applications that demand speed and accuracy. Their capability to process and correct errors efficiently ensures data integrity, especially in bandwidth-critical systems. Users can expect comprehensive integration support with available design kits and simulation models that aid seamless incorporation within existing hardware platforms. With flexibility for both FPGA and ASIC implementations, Creonic's LDPC encoders and decoders come equipped with adaptive features that allow for various code rates and block lengths. This adaptability ensures that users can tailor the application to meet specific requirements, benefiting from the cores' proven reliability in delivering high-quality data communication.
Polar ID is a comprehensive biometric security solution designed for smartphones and beyond, featuring the unique ability to sense the full polarization state of light. This system enhances biometric recognition by using advanced meta-optic technology, allowing it to capture the distinctive 'polarization signature' of a human face. This capability provides a robust defense against sophisticated 3D masks and spoofing attempts, making it a leading choice for secure facial authentication. Polar ID eliminates the need for complex optical modules typical in structured light systems and does not rely on expensive time-of-flight sensors. By delivering all necessary information from a single image, Polar ID streamlines the authentication process, significantly reducing the size and cost of the system. It provides high-resolution recognition across various lighting conditions, from bright daylight to total darkness, ensuring a reliable and secure experience for users. Employing Polar ID, manufacturers can enable secure digital transactions and access controls without compromising on user experience or device aesthetics. By operating seamlessly even when users wear sunglasses or face masks, this system sets a new standard in facial recognition technology. Its compact design fits easily into the most challenging form factors, making it accessible for a wide range of mobile devices.
The SHA-2 Crypto Engine from Tiempo Secure delivers advanced hashing functionality that is pivotal for ensuring data integrity and security in various applications. This IP core stands out for its efficient processing capabilities, supporting hashing functions like SHA-256 and SHA-224. Designed with a 1 cycle per round architecture, the SHA-2 Crypto Engine supports both the import and export of SHA-256 states, catering to even the most complex cryptographic operations. Its ability to handle any message length with bit granularity makes it versatile for wide-ranging applications. Internal padding is seamlessly handled within the IP, and for ease of integration, it comes with wrappers for standard buses such as APB and AXI. This ensures it fits well into a plethora of existing designs, making it a reliable choice for implementing digital signatures and data integrity checks. A unique feature of the SHA-2 Crypto Engine is its readiness to handle pre-padded payloads, optimizing processing without compromising on performance. It empowers developers to boost their system's security robustness while benefiting from an optimized silicon resource-to-performance ratio.
The AES-XTS solution by Helion is tailored for disk encryption, leveraging the Tweakable block cipher algorithm to provide enhanced data security at the sector level on storage devices. The AES-XTS mode is designed to prevent threats like copy-and-paste or dictionary attacks and can independently encrypt and decrypt data in sector-sized blocks. This encryption core is crucial for safeguarding sensitive data on storage arrays, ensuring that identical plaintext blocks placed at different sectors result in distinct ciphertext. Helion offers a variety of AES-XTS cores to address differing data throughput needs, with capabilities ranging from less than 1Gbps to over 64Gbps, making it suitable for singular hard disks to large server arrays. Helion's AES-XTS solutions can be deployed on both ASIC and FPGA platforms, ensuring maximum performance and resource efficiency across varied technological landscapes. They support key sizes of 128-bit and 256-bit, with options for Ciphertext Stealing, adapting to diverse encryption protocols and operational environments.
aiWare is a cutting-edge hardware solution dedicated to facilitating neural processing for automotive AI applications. As part of aiMotive’s advanced offerings, the aiWare NPU (Neural Processing Unit) provides a scalable AI inference platform optimized for cost-sensitive and multi-sensor automotive applications ranging from Level 2 to Level 4 driving automation. With its unique SDK focused on neural network optimization, aiWare offers up to 256 Effective TOPS per core, on par with leading industry efficiency benchmarks. The aiWare hardware IP integrates smoothly into automotive systems due to its ISO 26262 ASIL B certification, making it suitable for production environments requiring rigorous safety standards. Its innovative architecture utilizes both on-chip local memory and dense on-chip RAM for efficient data handling, significantly reducing external memory needs. This focus on minimizing off-chip traffic enhances the overall performance while adhering to stringent automotive requirements. Optimized for high-speed operation, aiWare can reach up to 1024 TOPS, providing flexibility across a wide range of AI workloads including CNNs, LSTMs, and RNNs. Designed for easy layout and software integration, aiWare supports essential activation and pooling functions natively, allowing maximum processing efficiency for neural networks without host CPU interference. This makes it an exemplary choice for automotive-grade AI, supporting various advanced driving capabilities and applications.
ChipJuice is an innovative tool for reverse engineering integrated circuits, uniquely designed for comprehensive IC analysis and security evaluation. This versatile software tool supports digital forensics, backdoor research, and IP infringement investigations, making it indispensable for labs, government entities, and semiconductor companies. ChipJuice operates efficiently across various IC architectures, allowing users to extract internal architecture details and generate detailed reports, including netlists and hardware description language files. The tool's intuitive user interface and high-performance processing algorithms make it accessible to users of different expertise levels, from beginners to advanced professionals. It is capable of handling a wide range of chips, regardless of their size, technology node, or complexity, providing a scalable solution for diverse reverse engineering tasks. ChipJuice's automated standard cell research feature further enhances its analytic capabilities, enabling efficient identification and cataloging of IC components. Moreover, ChipJuice facilitates a seamless analysis process by simply using electronic images of a chip's digital core. This allows for precise signal tracing and thorough IC evaluation, supporting its users' strategic objectives in security audits and architectural exploration. ChipJuice is an essential tool for those seeking to delve deep into ICs for security validation and developmental insights.
The eSi-Crypto suite from EnSilica offers an extensive range of cryptographic IPs designed to provide high-quality encryption and authentication functionalities. A standout feature of this suite is its True Random Number Generator (TRNG), which adheres to NIST 800-22 standards and ensures robust random number generation essential for secure communication. These cryptographic cores are versatile and can be easily integrated through various bus interfaces like AMBA APB/AHB and AXI.\n\nSupporting numerous algorithms such as CRYSTALS Kyber and Dilithium, ECDSA/ECC, and AES, the eSi-Crypto suite advances quantum-resilient cryptography. This feature is crucial as it prepares secure digital communications against future quantum threats. Moreover, the suite includes high-throughput solutions suitable for applications that demand both efficiency and resource optimization, like V2X communications.\n\nEnSilica's cryptographic IPs exhibit compatibility with ASIC and FPGA targets, offering low resource usage while maintaining exceptionally high throughput. The suite also encloses IPs for various SHA algorithms, ChaCha20, Poly1305, and traditional standards like RSA and TDES. This comprehensive range meeting both modern cryptographic demands ensures that data protection remains robust and flexible in diverse application scenarios.
Secure-IC's Post-Quantum Cryptography IP encompasses advanced solutions designed to counter the potential threats posed by quantum computing. This IP includes hardware accelerators and software libraries implementing lattice-based and hash-based algorithms, offering extensive protection against various side-channel attacks. With capabilities for key generation, encapsulation, and decapsulation, this solution integrates seamlessly into AMBA interfaces, ensuring secure and efficient cryptographic processes in future-proof environments.
The AndeSoft software stack provides a comprehensive suite of software components such as operating systems, Linux kernels, various libraries, and middleware. These components aim to expedite the customer's product development cycle, enabling them to focus more on application-specific requirements instead of general development concerns. The software is optimized for AndesCore processors and helps to reduce time-to-market without compromising performance.
The Cramium Personal Hardware Security Module, or PHSM, by CrossBar, is designed to address the growing need for enhanced security measures in electronic devices. By leveraging CrossBar's ReRAM technology, the PHSM offers a robust solution for secure key storage and encryption, protecting devices from unauthorized access and cyber threats. It acts as a vital component in maintaining the integrity and confidentiality of data across various applications. The module incorporates cryptographic mechanisms to create a secure environment against physical and digital attacks, ensuring that sensitive information remains protected from sophisticated hacking attempts. The intrinsic characteristics of ReRAM technology, such as its high randomness and low bit error rates, form the core of the PHSM's ability to deter potential attacks. Engineered with a focus on root of trust applications, the PHSM reinforces secure authentication processes, which are crucial in industries like automotive, medical, and IoT-based systems. The compact design aids in seamless integration within semiconductor hardware, thereby supporting diverse applications that demand rigorous security protocols.
Tiempo Secure's SHA-3 Crypto Engine is an advanced cryptographic module that offers exceptional flexibility and performance for modern security needs. Emphasizing scalability, the engine supports varying numbers of hashing rounds per clock cycle, optimizing the silicon resource usage while ensuring high throughput. One of the key features is the ability to select between fixed-length and extendable-output functions (XOF) for each message, catering to diverse application requirements. This flexibility is easily manageable through simple configuration settings, making it adaptable to specific needs. Internally, the SHA-3 engine manages message padding and allows for efficient import/export of the KECCAK-p state. The architecture is designed for integration simplicity, featuring wrappers compatible with standard bus protocols like APB and AXI, facilitating smooth incorporation into a myriad of systems. In addition to supporting SHA-3 standard functions, it accelerates the Kangaroo Twelve algorithm, offering a comprehensive suite of cryptographic tools for enhanced data security and integrity across various applications.
FortiMac delivers robust security for HMAC SHA2 implementations by offering powerful protection against both side-channel (SC) and fault injection (FI) attacks. It employs the Threshold Implementation paradigm to ensure high-level security with a minimal gate footprint. FortiMac's core technology has undergone extensive analytical and physical validation to guarantee its effectiveness against modern threats. It is an ideal choice for applications requiring strong and reliable cryptographic protection.
The Securyzr iSSP, or Integrated Security Services Platform, is a robust lifecycle management solution tailored for secure deployment, supply, and management of embedded devices. This platform facilitates zero-touch security lifecycle services such as provisioning, firmware updates, and security monitoring, thus ensuring consistent and reliable security from chip manufacture to device decommissioning. It integrates both a secure element (iSE) and a server component, creating a comprehensive chip-to-cloud security solution capable of functioning on public and private cloud environments.