All IPs > Processor > Processor Cores
Processor cores are fundamental components in central processing units (CPUs) and systems-on-chip (SoCs) for a myriad of digital devices ranging from personal computers and smartphones to more specialized equipment like embedded systems. Within the category of Processor Cores, you'll find a diverse selection of semiconductor IPs tailored to meet the varying demands of speed, power efficiency, and processing capability required by today's technology-driven world.
Our Processor Cores category provides an extensive library of semiconductor IPs, enabling designers to integrate powerful, efficient, and scalable cores into their projects. These IPs are essential for firms aiming to innovate and achieve a competitive edge within the fast-evolving tech landscape. Whether you're developing high-performance computing solutions or aiming for energy-efficient mobile gadgets, our processor core IP offerings are designed to support a wide range of architectures, from single-core microcontrollers to multi-core, multi-threaded processors.
One of the primary uses of processor core IPs is to define the architecture and functions of a core within a chip. These IPs provide the blueprint for building custom processors that can handle specific applications efficiently. They cover a broad spectrum of processing needs, including general-purpose processing, digital signal processing, and application-specific processing tasks. This flexibility allows developers to choose IPs that align perfectly with their product specifications, ensuring optimal performance and power usage.
In our Processor Cores category, you'll discover IPs suited for creating processors that power everything from wearables and IoT devices to servers and network infrastructure hardware. By leveraging these semiconductor IPs, businesses can significantly reduce time-to-market, lower development costs, and ensure that their products remain at the forefront of technology innovation. Each IP in this category is crafted to meet industry standards, providing robust solutions that integrate seamlessly into various technological environments.
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
The IDesignSpec GDI is a highly efficient graphical design interface offering an integrated platform for semiconductor design. It is aimed at enhancing the design process by providing a unified environment that supports the generation of development collateral from high-level specifications. The product facilitates seamless integration with other design and verification tools, ensuring that all teams remain aligned and efficient. One of its standout features is the ability to automatically update all output files whenever a specification changes, which significantly reduces manual errors and synchronizes the workflow across design, verification, and documentation stages. Designed with versatility in mind, IDesignSpec GDI supports the development of SOC, ASIC, and FPGA products. It offers features that streamline processes such as UVM Testbench creation, RTL design code generation, and system-level SoC validation. Its automated flow replaces the need for manual coding, allowing design teams to maintain focus on essential engineering tasks. This product is integral for teams keen on minimizing development time while maximizing productivity and accuracy across all stages of semiconductor development. Moreover, IDesignSpec GDI is known for its excellent support for various semiconductor elements such as registers and memories, standard IP, and custom sequences. It caters efficiently to the needs of design engineers, embedded programmers, and post-silicon lab teams, providing a robust framework for managing every developmental aspect. By ensuring consistency between firmware and software code, it upholds high standards, thereby guaranteeing the quality and reliability of the final product.
The RISC-V BK Core Series by Codasip offers a suite of processor cores designed for efficiency and configurability, each catering to specific computational needs. This series leverages the openness of the RISC-V architecture, providing a foundation that developers can customize for various applications. These cores are adept for use in IoT, automotive, and industrial applications where performance and power efficiency are critical. The BK Core Series is designed to provide low latency and high throughput, ensuring optimal performance for embedded systems. Each core in the series is developed with a focus on power efficiency, making it suitable for battery-operated devices where longevity is essential. The scalability of the BK Core Series allows designers to adjust configurations to meet different performance requirements without compromising on power consumption. In implementing the RISC-V open standard, Codasip has ensured that these cores are highly adaptable, with the ability to integrate with various peripherals and other IPs. This makes the BK Core Series a versatile choice for engineers looking to deploy advanced computing capabilities efficiently.
IDS-Batch CLI provides a command-line interface to automate the batch processing of design files within semiconductor projects. This tool offers a seamless integration option for executing repetitive tasks, ensuring consistency and efficiency across various processes. It eliminates the need for manual intervention in file management, streamlining workflows and accelerating project timelines. With IDS-Batch CLI, teams can automate the generation and synchronization of development collateral, aligning with changing specifications without disrupting project momentum. The product is particularly beneficial for large-scale projects requiring massive data processing and file management. By automating these routine tasks, IDS-Batch CLI diminishes the scope for human error and enhances accuracy in output files. This is crucial in maintaining the integrity of the design and verification processes, providing a reliable solution for integrated circuit designers who need precise control over project components. IDS-Batch CLI's design aligns with Agnisys's suite of automation tools, ensuring that users experience a consistent interface across multiple products. It supports the generation and maintenance of critical files required for SOC, ASIC, and FPGA developments, aiding companies in reducing labor costs and increasing workflow efficiency.
Avispado is crafted as a 64-bit in-order RISC-V core that prioritizes efficiency and simplicity. Designed for energy-sensitive systems, it provides a balance between performance and power consumption, making it ideal for machine learning tasks where energy efficiency is paramount. Its 2-wide in-order pipeline smoothly manages instruction processing while maintaining low power usage. This core's architecture supports high-performance computing demands by allowing extensive customization, such as scalable instruction and data cache sizes and branch prediction tuning. Its integration with the Gazzillion Misses™ technology enhances its capacity to manage data with high sparsity, resulting in superior energy efficiency per operation. Its vector-ready design with the Vector Specification 1.0 provides flexibility in computational tasks, enhancing its workload handling capabilities. Avispado is equipped for multiprocessing environments with support for cache coherence, leveraging the CHI interface and customizable down to AXI. This flexibility makes Avispado a perfect component for building cost-efficient, high-performance SoCs tailored for specific machine learning applications, providing robust performance without excessive silicon footprint.
The EMSA5-FS is a 32-bit embedded processor core designed to cater to high safety standards, making it ideal for functional safety applications. Engineered for robustness, this RISC-V processor core is particularly suited for automotive and other safety-critical applications where compliance with stringent industry standards is a must. Its architecture is optimized for low-latency operations, providing enhanced processing power while maintaining a small silicon footprint. Functionally, the EMSA5-FS supports secure execution with cryptography-based separation of execution contexts. This design ensures that only authorized code can run, a pivotal feature in environments susceptible to attacks. The core's safety features are complemented by its energy-efficient operation, making it not only safe but also cost-effective, particularly in battery-run devices. The processor's seamless integration capabilities are another highlight, making it compatible with various development tools and environments. Whether used in isolated tasks or as part of complex SoCs, the EMSA5-FS is an invaluable asset for engineers aiming to create secure, functional, and efficient systems, ideally in automotive and IoT sectors.
IDS-Integrate provides a unified solution for integrating various design and verification components within semiconductor projects. By offering a cohesive platform for assembling SOCs, ASICs, and FPGAs, IDS-Integrate ensures that all pieces of a project fit together perfectly, minimizing integration time and improving product reliability. The tool is crucial for teams looking to streamline complex integrations without sacrificing quality or precision. IDS-Integrate stands out with its capability to integrate disparate elements into a harmonious system, facilitating easier management of complex semiconductor architectures. Its functionality supports project teams in synchronizing the outputs from various stages of development, following changes to specifications or design adjustments. This tool's integration methodologies include comprehensive checks and balances that ensure compatibility and functionality, making it a vital component in Agnisys's suite for enhancing workflow efficiencies. With IDS-Integrate, project teams can confidently finalize integrations, benefiting from reduced development cycles and increased resource optimization.
Offering a high-performance processing solution, the eSi-3250 is a 32-bit RISC IP core suitable for ASIC or FPGA systems requiring on-chip caching due to slower eFlash memories or off-chip access. This core is engineered to support an impressive set of functionalities, making it a standout option for applications needing robust processing coupled with efficient data handling capabilities. The inclusion of separate configurable instruction and data caches enhances the core’s capability to manage complex instructions and data storage efficiently, thus augmenting overall performance. With a robust instruction set that supports IEEE 754 compliant floating-point instructions and full 64-bit arithmetic operations, the eSi-3250 is suitable for advanced computational demands. Its design incorporates a 5-stage pipeline for high-frequency operations, underpinned by significant power efficiency, ensuring minimal energy consumption. Accommodating both user and supervisor operating modes, the processor provides a secure environment for multitasking operations. Multiple debug options, comprehensive user-defined instruction support, and integration with various peripheral interfaces render the eSi-3250 a versatile and high-functioning core, ideal for challenging computational environments that prioritize processing speed and power efficiency.
Crafted for the embedded market, the RV12 RISC-V Processor is a flexible, single-core CPU that adheres to the RV32I and RV64I specifications of the RISC-V instruction set. It supports a Harvard architecture, fostering simultaneous access to instruction and data memories, enhancing computational efficiency. Known for its adaptability, it can be configured to meet diverse processor needs in embedded applications. As part of the 32/64-bit CPU family, the RV12 processor is designed to offer an open-source pathway for projects needing a dependable processing unit. Its adherence to a standard instruction set ensures broad compatibility and ease of integration into various technological setups. The processor is accompanied by extensive documentation and testbenches, ensuring robust implementation capabilities. Supporting both FPGA and ASIC deployments, the RV12 is an ideal candidate for developers looking to harness the benefits of RISC-V's open-source ecosystem. The processor's design focus is centered on maximizing performance while maintaining low power consumption, making it a popular choice for modern embedded applications.
The Cortex-M series processors serve as a flexible foundation for developing custom ASIC solutions. These processors can handle tasks requiring various processing capacities and co-processor features such as floating-point units and different memory setups. They are particularly suitable for IoT applications that need to integrate processing cores with analog and sensor components. ASIC North has created a platform to streamline the development of ARM Cortex-M based devices, capable of addressing the intricate needs of IoT edge devices, focusing on ultra-low power consumption and high-level data security. The platform aims to simplify the development process by consolidating various technological and digital components into cohesive designs. This approach empowers developers to leverage existing ARM technologies and integrate them efficiently, streamlining the development of applications like IoT due to its advanced analog and digital capabilities. The platform provides a competitive edge by optimizing designs for energy efficiency and operational reliability. Focusing on IoT endpoints, this platform can manage energy efficiently to prolong battery life—a crucial factor for field-deployed sensors. It also emphasizes security, incorporating both software and hardware encryption to protect data flows between devices and cloud servers. ASIC North's expertise ensures that these devices not only enhance operational capacity but also maintain the security of transmitted data in IoT ecosystems.
Atrevido is a versatile 64-bit RISC-V core engineered for out-of-order processing, offering significant customizability and performance efficiency. Targeting applications in machine learning and artificial intelligence, Atrevido is built to handle demanding workloads with ease. Its architecture allows for 2, 3, or 4-wide pipeline configurations, enhancing its ability to manage multiple processes simultaneously and efficiently. This core's strength lies in its ability to navigate complex computations with minimal latency, thanks to the integration of Gazzillion Misses™ technology. This feature maximizes memory bandwidth utilization, making the core particularly well-suited for environments with high data sparsity and long memory latencies. Its out-of-order execution capability is crucial for improving throughput in applications requiring rapid data processing, such as recommendation systems and high-performance computing tasks. Atrevido also supports the RISC-V Vector Specification 1.0, allowing for the integration of vector instructions that optimize tasks typically associated with AI workloads. This feature, combined with native support for cache-coherent multiprocessing, makes Atrevido a powerful choice for constructing scalable, efficient SoCs. Its configurability ensures that developers can tailor the core precisely to meet the specific needs of their projects.
The eSi-1600 is an economical and energy-efficient 16-bit RISC processor core, well-suited for integration into ASIC and FPGA designs. It provides an effective performance-level akin to that of more costly 32-bit CPUs but offers a system cost similar to that of simpler 8-bit CPUs. Its architecture focuses on control applications within mature mixed-signal processes with under 64KB of memory. This core is specifically designed for scenarios where reduced power consumption is vital, facilitating an energy-efficient operation since fewer clock cycles are needed to run applications as compared to 8-bit CPUs. The eSi-1600 architecture comprises 16 or 32 general-purpose registers, 92 basic instructions, and 10 diverse addressing modes, allowing up to 74 user-defined instructions to be incorporated for custom application needs. Its unique architectural design with a 5-stage pipeline supports rapid instruction processing, while an optional memory protection unit and AMBA AHB buses provide robust system integration. Debug options such as JTAG or serial debug, optional trace, and performance counters grant developers the tools needed for efficient debugging and system analysis. Optimized for DFT and silicon-proven, the eSi-1600 is delivered as a Verilog RTL IP core, facilitating adaptability to a customer-specific design. Its design allows for seamless integration with AMBA peripherals like UART, SPI, and I2C among others, ensuring compatibility with third-party IPs. Intended for low-power applications, it supports intricate data manipulations and fast low-power state transitions, making it ideal for scenarios necessitating elevated energy efficiency as well as enhanced code density.
The eSi-3200 is a versatile 32-bit RISC processor core optimized for low-cost and low-power applications. Without internal caching, this core is well-suited for embedded control tasks where deterministic performance is essential, making it ideal for situations demanding reliable, real-time control. Its architecture utilizes a modified-Harvard approach for dual instruction and data fetching, ensuring rapid data processing and minimal interruptions. The processor offers an extensive instruction set with the capability to incorporate user-specific commands, broadening its functionality to suit targeted applications. It includes options for a floating-point unit that adheres to IEEE 754 standards, further enriching its computational capabilities with instructions for single-precision floating points and 64-bit arithmetic operations. Its robust design allows for fast instruction processing through a 5-stage pipeline, maintaining exceptional performance with a 4.12 CoreMark per MHz efficiency. Beyond its architectural advantages, the eSi-3200 facilitates energy efficiency by maximizing code density through its smart instruction encoding in both 16 and 32 bits. It supports comprehensive operating modes with a focus on both user and supervisor protection to safeguard system integrity during operation. With a suite of debugging tools and supports for various AMBA peripherals, the eSi-3200 stands out as a reliable choice for developers needing a high-performing, energy-efficient processor core.
The AndesCore processors consist of a versatile lineup of 32-bit and 64-bit CPU cores engineered for cutting-edge applications in emerging markets. Designed around the AndeStar V5 instruction set architecture and compliant with RISC-V standards, these processors offer a variety of solutions for diverse requirements. The compact series, featuring cores like the N22, are tailored for low power consumption and high performance, reaching benchmarks like 3.95 Coremark/MHz. This series emphasizes efficiency with a streamlined 2-stage pipeline for optimal operation. For enhanced design capabilities, the 25 and 27 series boast a 5-stage pipeline configuration, offering high frequency and performance efficiency. The 25 series, which includes models like the AX25 and AX25MP, supports multicore configurations and cache management systems to ensure coherent data processing. The advanced architecture allows these processors to accommodate high throughput requirements efficiently. The advanced 45 and 65 series incorporate dual-issue and out-of-order 8-stage and 13-stage pipelines, respectively. These series underscore Andes Technology's commitment to sophisticated processor design, supporting complex computations with vector processing units ideal for uses in scientific computing, multimedia processing, and machine learning. Innovations like MemBoost, coherence management, and vectored interrupt controllers enhance these cores, making them suitable for demanding technical landscapes.
The eSi-3264 is an advanced 32/64-bit RISC CPU designed for high-performance applications needing DSP (Digital Signal Processing) capabilities, making it ideal for areas like audio processing, motion control, and sensor data analysis. Its architecture incorporates SIMD (Single Instruction Multiple Data) extensions, allowing for efficient data processing with minimal silicon real estate, ensuring a balance between performance and power consumption. This processor features a comprehensive instruction set supporting dual and quad SIMD operations along with precision IEEE 754 floating-point instructions. Additional adaptations include bit manipulation and complex arithmetic operations, enhancing the processor's capability to handle demanding computational workloads effectively. A pipelined MAC unit and configurable data and instruction caches bolster processing speeds, maintaining optimal power efficiency. Augmented with extensive debugging options, including trace and performance counters, the eSi-3264 is versatile for various implementations, from rapid prototyping to deployment in robust industrial environments. It supports both user-defined instructions and comprehensive peripheral integration using standard AMBA buses, enabling seamless enhancements and extensions tailored to specific application requirements.
The eSi-1650 is a compact, low-power 16-bit RISC CPU core integrating an instruction cache which enhances its performance and area efficiency, particularly for mature electronic nodes employing OTP or Flash for program memory. Designed for energy-efficient execution, it minimizes power consumption by circumventing the need for extensive shadow RAMs while facilitating prolonged high-frequency CPU operation. This makes it exceptionally well-suited for applications where an 8-bit CPU might typically suffice but necessitates an upgrade due to its limitations. Configuration options abound with the eSi-1650, which supports 16 or 32 general-purpose registers, and offers 92 basic instructions alongside 74 user-defined ones. Its architectural attributes include a customizable instruction cache (ranging from 1-64kB and varied ways of associativity), enabling optimal performance across various process nodes. The 5-stage pipeline ensures efficient instruction processing, while maintaining fast interrupt response times crucial in responsive system applications. Delivering a convenient migration path, whether for increased cache requirements or shifting to higher bit architectures, the eSi-1650 is designed to support efficient software development through a license-free toolchain. Debugging tools, like hardware breakpoints and performance counters, complement the support for multi-process settings, offering a professional and streamlined debugging experience. Ready for deployment, the core integrates seamlessly with AMBA peripheral components, bolstering its capability to meet a wide range of application requirements while maintaining a cost-effective profile.
The BX2 baseband processor from Ceva is a highly programmable and versatile hybrid DSP capable of handling a wide array of signal processing and control workloads. It integrates seamlessly with diverse applications, ranging from high-performance computing devices to embedded systems, providing a balanced mix of DSP power and control flexibility. Ceva's BX2 provides a robust solution for audio processing, wireless communications, and general-purpose DSP applications. It boasts high-level programmability which allows developers to tailor processing capabilities to specific project needs, enhancing both efficiency and performance. The processor also facilitates easy integration into existing hardware architectures, empowering developers to innovate without the constraint of reconfiguring their system designs significantly. Its capacity to manage extensive computing tasks while maintaining low energy consumption makes it a preferred choice for battery-powered applications, ensuring enhanced performance without compromising on longevity.