All IPs > Platform Level IP > Processor Core Independent
In the ever-evolving landscape of semiconductor technologies, processor core independent IPs play a crucial role in designing flexible and scalable digital systems. These semiconductor technologies offer the versatility of enabling functionalities independent of a specific processor core, making them invaluable for a variety of applications where flexibility and reusability are paramount.
Processor core independent semiconductor IPs are tailored to function across different processor architectures, avoiding the constraints tied to any one specific core. This characteristic is particularly beneficial in embedded systems, where designers aim to balance cost, performance, and power efficiency while ensuring seamless integration. These IPs provide solutions that accommodate diverse processing requirements, from small-scale embedded controllers to large-scale data centers, making them essential components in the toolkit of semiconductor design engineers.
Products in this category often include memory controllers, I/O interfaces, and various digital signal processing blocks, each designed to operate autonomously from the central processor's architecture. This independence allows manufacturers to leverage these IPs in a broad array of devices, from consumer electronics to automotive systems, without the need for extensive redesigns for different processor families. Moreover, this flexibility championed by processor core independent IPs significantly accelerates the time-to-market for many devices, offering a competitive edge in high-paced industry environments.
Furthermore, the adoption of processor core independent IPs supports the development of customized, application-specific integrated circuits (ASICs) and system-on-chips (SoCs) that require unique configurations, without the overhead of processor-specific dependencies. By embracing these advanced semiconductor IPs, businesses can ensure that their devices are future-proof, scalable, and capable of integrating new functionalities as technologies advance without being hindered by processor-specific limitations. This adaptability positions processor core independent IPs as a vital cog in the machine of modern semiconductor design and innovation.
KPIT's iDART platform addresses the challenges posed by software-defined vehicles, focusing on optimizing diagnostics, maintenance, and aftersales services. By deploying advanced AI-driven diagnostics and self-learning systems, the platform enhances the reliability of vehicle servicing and improves the overall customer experience. This transformation embraces legacy system integration while advancing toward fully automated, predictive, and customer-centered service models that support the evolving demands of the automotive market.
The ORC3990 is a sophisticated System on Chip (SoC) solution designed for low-power sensor-to-satellite communication within the LEO satellite spectrum. Utilizing Totum's DMSS technology, it achieves superior doppler performance, facilitating robust connectivity for IoT devices. The integration of an RF transceiver, power amplifiers, ARM CPUs, and memory components makes it a highly versatile module. Leveraging advanced power management technology, this SoC supports a battery life that exceeds ten years, even within industrial temperature ranges from -40 to +85°C. It's optimized for usage with Totum's global LEO satellite network, ensuring substantial indoor signal coverage without the need for additional GNSS components. Efficiency is a key feature, with the chip operating in the 2.4 GHz ISM band, providing unparalleled connectivity regardless of location. Compact in design, comparable in size to a business card, and designed for easy mounting, the ORC3990 offers sought-after versatility for IoT applications. The ability to function with excellent TCO in terms of cost compared to terrestrial IoT solutions makes it a valuable asset for any IoT deployment focused on sustainability and longevity.
The Chimera GPNPU stands as a powerful neural processing unit tailor-made for on-device AI computing. This processor architecture revolutionizes the landscape of SoC design, providing a unified execution pipeline that integrates both matrix and vector operations with control code typically handled by separate cores. Such integration boosts developer productivity and enhances performance significantly. The Chimera GPNPU's ability to run diverse AI models—including classical backbones, vision transformers, and large language models—demonstrates its adaptability to future AI developments. Its scalable design enables handling of extensive computational workloads reaching up to 864 TOPs, making it suitable for a wide array of applications including automotive-grade AI solutions. This licensable processor core is built with a unique hybrid architecture that combines Von Neuman and 2D SIMD matrix instructions, facilitating efficient execution of a myriad array of data processing tasks. The Chimera GPNPU has been optimized for integration, allowing seamless incorporation into modern SoC designs for high-speed and power-efficient computing. Key features include a robust instruction set tailored for ML tasks, effective memory optimization strategies, and a systematic approach to on-chip data handling, all working to minimize power usage while maximizing throughput and computational accuracy. Furthermore, the Chimera GPNPU not only meets contemporary demands of AI processing but is forward-compatible with potential advancements in machine learning models. Through comprehensive safety enhancements, it addresses stringent automotive safety requirements, ensuring reliable performance in critical applications like ADAS and enhanced in-cabin monitoring systems. This combination of performance, efficiency, and scalability positions the Chimera GPNPU as a pivotal tool in the advancement of AI-driven technologies within industries demanding high reliability and long-term support.
The H-Series PHY offers a groundbreaking approach to high bandwidth memory solutions, specifically fine-tuned for applications in AI, ML, graphics, and high-performance computing. This PHY IP core is engineered to deliver top-notch performance, accommodating challenging demands with optimized area and power consumption. It supports HBM2 and HBM2E standards with a robust data rate capability of up to 3200 MB/sec, allowing seamless integration with advanced systems. This PHY leverages a 2.5D interposer level design and supports up to 16 channels, providing substantial bandwidth in competitive environments. Notably, it is compatible with pseudo-channel configurations and manages up to 8 stacked HBM2E memories, delivering exceptional memory performance. The DFI 5.0 interface ensures smooth connectivity, making it ideal for AI, ML, graphics, and networking applications, delivering peak performance in various scenarios. Optimized for areas of low power and high efficiency, the H-Series PHY is crafted to reduce latency intricately. Its structural efficiency is underscored by its ability to balance performance with minimalistic design requirements, setting a benchmark for PHY implementations in demanding settings.
The AndeShape Platforms include a range of systems designed for developing with AndesCore processors. These platforms are split into categories such as microcontroller platforms and FPGA development kits. They offer integrated solutions with pre-configured IP blocks to simplify the design process for complex systems. Through its assortment of hardware development tools, AndeShape platforms cater to various stages of product development from inception to demonstration, making it easier for engineers to create efficient, scalable solutions.
The GSHARK GPU IP accelerates graphics on embedded systems, delivering high performance with low power consumption while minimizing CPU load. Designed for embedded devices like digital cameras and automotive equipment, the GSHARK-IP leverages advanced proprietary architectures to achieve smooth graphics rendering akin to those seen on PCs and gaming consoles. Its proven track record with over a hundred million shipments highlights its reliability in commercial silicons.
AndesCore processors are designed as high-performance CPU cores targeting a variety of market segments. These processors, built on the RISC-V compatible AndeStar™ architecture, provide scalable solutions suitable for applications in AI, IoT, and more. The V5 core family is renowned for its performance efficiency and flexibility, featuring 32-bit and 64-bit cores that support an array of computing tasks. Each core is engineered to meet diverse application requirements, ranging from streamlined low-power designs to high-throughput models.
The Arria 10 System on Module (SoM) is designed with an emphasis on embedded and automotive vision applications. This compact module leverages Altera's Arria 10 SoC devices in a sleek 29x29 mm package, offering a plethora of interfaces while maintaining a small, efficient form factor. It features an Altera Arria 10 SoC FPGA with a range from 160 to 480 KLEs, coupled with a Cortex A9 Dual-Core CPU. This enables robust integration and performance for demanding applications. The module's power management system ensures a seamless power-up and -down sequence, requiring only a 12V supply from the baseboard. Its dual DDR4 memory interfaces provide up to 2.4 Gbit/s per pin, offering a total bandwidth of up to 230 Gbit/s for both CPU and FPGA memory systems. This module supports a wide array of high-speed interfaces, including PCIe Gen3 x8, 10/40 Gbit/s Ethernet, DisplayPort, and 12G SDI, making it suitable for complex imaging and communication tasks. Additional features include up to 32 LVDS lanes for configurable RX or TX, two USB interfaces with OTG support, and ARM I²C, SPI, and GPIO interface signals. Furthermore, the Arria 10 SoM includes pre-configured IP for memory controllers and an Angstrom Linux distribution, facilitating rapid development and deployment of applications.
NeuroMosAIc Studio is a comprehensive software platform designed to accelerate AI development and deployment across various domains. This platform serves as an essential toolkit for transforming neural network models into hardware-optimized formats specific for AiM Future's accelerators. With broad functionalities including conversion, quantization, compression, and optimization of neural networks, it empowers AI developers to enhance model performance and efficiency. The studio facilitates advanced precision analysis and adjustment, ensuring models are tuned to operate optimally within hardware constraints while maintaining accuracy. Its capability to generate C code and provide runtime libraries aids in seamless integration within target environments, enhancing the capability of developers to leverage AI accelerators fully. Through this suite, companies gain access to an array of tools including an NMP compiler, simulator, and support for NMP-aware training. These tools allow for optimized training stages and quantization of models, providing significant operational benefits in AI-powered solutions. NeuroMosAIc Studio, therefore, contributes to reducing development cycles and costs while ensuring top-notch performance of deployed AI applications.
The Metis AIPU PCIe AI Accelerator Card represents a powerful computing solution for high-demand AI applications. This card, equipped with a single Metis AI Processing Unit, delivers extraordinary processing capabilities, reaching up to 214 Tera Operations Per Second (TOPS). Designed to handle intensive computing tasks, it is particularly suited for applications requiring substantial computational power and rapid data processing, such as real-time video analytics and AI-driven operations in various industrial and retail environments. This accelerator card integrates seamlessly into PCIe slots, providing developers with an easy-to-deploy solution enhanced by Axelera AI's Voyager Software Development Kit. The kit simplifies the deployment of neural networks, making it a practical tool for both seasoned developers and newcomers to AI technology. The card's power efficiency is a standout feature, aimed at reducing operational costs while ensuring optimal performance. With its innovative architecture, the Metis AIPU PCIe AI Accelerator Card not only meets but exceeds the needs of modern AI applications, ensuring users can harness significant processing power without the overheads associated with traditional systems.
VisualSim Architect is a sophisticated software platform dedicated to the modeling and simulation of system performance, power, and functionality. It empowers system engineers to explore designs virtually, measuring potential bottlenecks and power consumption before actual production begins. The platform aids in validating different hardware and software architectures, ensuring that the system is designed for optimal efficiency and performance. It also enables users to create virtual prototypes that mimic real-life system behaviors, thus facilitating a deeper understanding of potential implementation challenges. This preemptive approach allows companies to fine-tune their designs, ensuring that all components work harmoniously, thereby reducing risk and accelerating time-to-market. Furthermore, the platform's flexible system-level modeling capabilities cater to a diverse range of application fields, from automotive to consumer electronics.
The Cobra platform is designed specifically for the Xilinx Kintex-7, delivering robust performance for development and prototyping within digital systems. This platform facilitates the rapid integration and testing of Trilinear's extended IP offerings, particularly for advanced DisplayPort applications. It provides essential tools for developers looking to streamline their design process and reduce project timelines.
AccelerComm's Software-Defined High PHY is an adaptable O-RAN solution, optimized for the ARM processor architecture. This High PHY solution can operate with or without hardware acceleration, tailored to meet various capacity and power specifications. Developed to complement ASIC/SoC products, it supports a wide range of platforms, enhancing performance flexibility and integration simplicity. This solution is particularly beneficial in environments where dynamic computing capabilities are required and is pivotal in ensuring effective network scaling and performance delivery.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
The SiFive Performance family of processors is crafted to address the demands of data center workloads, multimedia processing, networking, and storage applications. Featuring 64-bit, out-of-order cores, they provide a wide range of design options tailored to workload necessities. This family includes processors ranging from three to six-wide out-of-order cores, equipped with dedicated vector engines optimized for AI workloads. These processors deliver top-tier performance within energy-efficient parameters, making them highly suitable for mobile devices, consumer electronics, and edge computing infrastructure.
ZIA Stereo Vision is an advanced stereoscopic vision module designed to provide precise distance estimation. By combining left and right camera inputs, it leverages semi-global matching algorithms to derive depth maps essential for applications like autonomous vehicles and robotic navigation. It operates under varying image resolutions and provides high-speed processing, ensuring integration into systems where rapid environmental mapping is crucial. Its hardware design optimizes power, space, and performance metrics, making it ideal for high-demand use cases that rely on accurate spatial awareness.
The ONNC Calibrator is crafted to optimize AI System-on-Chips by employing post-training quantization (PTQ) techniques to maintain high precision, especially in architectures using fixed-point formats like INT8. By leveraging architecture-aware quantization, it ensures chips retain 99.99% accuracy, offering unparalleled precision control across diverse hardware configurations. This calibrator supports configurable bit-width architectures, allowing the balance of precision and performance to be tailored for various applications. Capable of working with different AI frameworks such as ONNX and PyTorch, the calibrator aligns seamlessly with standard PTQ workflows without needing complex retraining. Its internal AI engine autonomously determines optimal scaling factors, making it an indispensable tool in maintaining model accuracy while reducing computational demand.
The Vega eFPGA from Rapid Silicon represents an innovative leap in providing customizable FPGA capabilities to System-on-Chip (SoC) designs. This eFPGA is designed to deliver flexibility and efficiency, allowing a seamless integration that enhances performance without raising costs. By embedding programmability directly into SoCs, Vega eFPGA facilitates diverse and adaptable computing needs. Structured with three configurable tile types – CLB, BRAM, and DSP – the Vega eFPGA is engineered for optimal performance. The CLB comprises eight 6-input lookup tables (LUTs), each offering dual independent outputs. It includes features like fast adders with carry chains and programmable registers, ensuring computational versatility. The BRAM component supports 36Kb dual-port memory, adaptable as 18Kb split memory configurations. The DSP tile incorporates an 18×20 multiplier with a 64-bit accumulator, supporting complex mathematical processing. Rapid Silicon's Vega eFPGA is optimized for scalability, providing flexibility in tile configurations to meet varied application requirements. It ensures ample compatibility with existing systems through seamless SoC integration, proprietary Raptor EDA tools, and robust IP libraries. These capabilities enable Vega to offer bespoke solutions tailored to specific end-user needs.
The Dynamic Neural Accelerator II (DNA-II) by EdgeCortix represents a new leap in neural network processing. This IP core is exceptionally efficient and provides scalable performance by reconfiguring runtime interconnects between its computing units. Supporting both convolutional and transformer models, DNA-II is tailored for edge AI tasks that demand high parallel processing. The modular DNA-II stands out by enhancing parallelism and optimizing on-chip memory bandwidth usage. Its symbiotic relationship with software solutions like the MERA compiler boosts its efficacy in deploying neural networks across varied applications, from smart cities to automotive systems.
The NOC-X technology offers a revolutionary approach to interconnect chip architectures, enabling efficient communication pathways across multi-core processors. Aimed at high-demand data-centric applications, it optimizes signal transmission for enhanced processing efficacy and reduced bottlenecks across complex computational frameworks. NOC-X leverages a digital-centric approach to network on chip design, minimizing power consumption without compromising on data exchange speeds. This IP is crucial for scenarios where rapid, reliable communication across various cores is paramount, ensuring that all parts of the system efficiently interact in real-time. This capability is essential for data-heavy industries pushing the boundaries of technology. Supporting tech nodes from 12nm to 28nm, NOC-X is adaptable to a wide range of applications, from consumer electronics to high-performance computing solutions. Its introduction into chiplet technology opens avenues for scalable, adaptable systems that can evolve with advancing technological demands, delivering significant gains in speed and operational efficiency.
The SiFive Essential processors offer a highly flexible IP platform, allowing customization to fit specific application needs. These processors span microcontrollers, IoT devices, real-time control, and general processing tasks. With options ranging from the most compact 2-3 stage MCUs to complex, superscalar designs suitable for Linux-based applications, the Essential series provides exceptional configurability. It caters to a wide range of market demands while maintaining a focus on power and area optimization, making it optimal for embedded systems and control plane processing.
Time-Triggered Ethernet (TTE) is a state-of-the-art networking technology designed for deterministic real-time communication over Ethernet. It integrates seamlessly with existing Ethernet infrastructure, providing fault-tolerant solutions for critical systems in aerospace, automotive, and industrial applications. TTE simplifies the design of networks by maintaining safety and redundancy at the network level, thus easing the application design processes. It ensures precise traffic scheduling, allowing for the integration of tight control loops and the certification of safety networks. TTE's ability to offer replicated packet communication guarantees message transmission even in fault scenarios, enhancing system availability and simplifying failure management.
TySOM Boards are a powerful solution in Aldec's line of embedded system prototyping tools, bringing the practicality of high-performance FPGA-based platforms to system design applications. These boards integrate a range of FPGAs like Xilinx’s Zynq UltraScale+, Zynq-7000, and Microchip's PolarFire SoC, catering to a broad spectrum of advanced computational needs. With industry standard interfaces such as FMC and BPX, these boards are not only versatile but also easily expandable with Aldec’s extensive daughter card selection. Thus, they stand out in facilitating the fast development of embedded applications spanning from automotive systems to AI, machine learning, and IoT. TySOM Boards provide a user-friendly platform that enables engineers to bridge the gap between conceptual design and physical implementation, fostering innovation in high-demand sectors like automotive advanced driver assistance systems (ADAS) and industrial automation. Their design supports a multitude of applications where performance and reliability are paramount, thus allowing designers unprecedented flexibility and capability in high-stakes development environments. As embedded system prototyping continues to grow in complexity, TySOM Boards offer a scalable path forward, meeting the challenges of next-generation technology design and deployment.
The Digital Radio (GDR) from GIRD Systems is a highly adaptable, reconfigurable multi-channel Software Defined Radio (SDR) equipped with robust high-speed signal processing capabilities. At its core, the GDR features a single board module easily customizable to cater to diverse requirements for both either embedded and standalone systems. Covering an extensive frequency range, the GDR can be set up to function with one or two separate transceivers, whether full or half duplex. Its flexible architecture allows operation in either a single channel or multiple-input, multiple-output (MIMO) configurations, accommodating a wide array of use cases. The SDR’s underlying flexibility not only makes it suitable for a broad range of applications but also ensures it can be tailored to suit specific operational needs effectively. By supporting both standalone and embedded configurations, the GDR enhances communication reliability in dynamic environments. Ideal for deployment in congested and contested settings, the GDR's capability to adapt quickly to evolving requirements makes it a valuable tool for advanced signal processing and digital communication tasks. Its modular design focuses on minimizing overheads while maintaining high performance, thereby offering cost-effective solutions with minimal design compromise.
The Menta eFPGA IP Cores v5 are designed to be highly versatile, high-density programmable logic blocks embedded within SoCs or ASICs. These cores help designers define precise resource requirements to meet application-specific needs, available in both Soft RTL and Hard GDSII options. The key advantages of these cores include significant cost reduction, improved performance, and lower power consumption compared to traditional on-board FPGAs. One of the main features of Menta's eFPGA is its architecture, which conserves board space and drastically reduces power usage, as much as 50% less than comparable FPGA-based solutions. Integration directly on-chip reduces I/O latency and overcomes the limitations of traditional chip-to-chip communication interfaces. Additionally, Menta's eFPGA supports a broad range of technology nodes, from 350nm to less than 5nm, offering unparalleled silicon process portability. Menta's eFPGA architecture is easy to integrate, verified at various stages including formal verification and system simulation. It features trusted controls over bitstream loading and offers customization options for logic blocks, DSP arithmetic functions, and power-saving features. The standard-cell designed eFPGAs cater to unique application needs while being platform adaptive, ensuring broad compatibility and design flexibility.
The Akeana 1000 Series offers 64-bit RISC-V processors tailored for high-performance computing and data processing. These processors are versatile, supporting various applications from smart homes to automotive sensing. With a focus on performance, the series includes multi-threading support and options for in-order or out-of-order execution, providing solutions to different computational needs. Configurable with instruction issue widths ranging from single to quad-issue, the Akeana 1000 Series addresses a wide spectrum of applications. This mid-range offering features memory management units with substantial TLB capacity, supporting address translation for efficient process management. Enhanced by ECC support, these processors ensure data integrity across tasks. With customization options including vector extensions and shared cache configurations, the Akeana 1000 Series stands as an adaptable solution for high-end microcontroller and gateway applications. It balances power and performance, extending its utility to industrial automation and edge AI applications.
Imec's Monolithic Microsystems embody the seamless integration of diverse functionalities onto a single chip, heralding a new era of miniaturization and efficiency in various applications. These microsystems are crafted through state-of-the-art semiconductor processes, allowing for the incorporation of multiple components into one coherent unit. This innovation is particularly revolutionary for technologies requiring sophisticated multi-domain integration, such as wearable devices, medical implants, and smart sensors. By uniting digital logic, sensors, actuators, and communication capabilities onto a single chip, the Monolithic Microsystems greatly reduce the need for additional components, thereby minimizing device size and enhancing reliability. Imec's comprehensive approach to microsystem development ensures that these chips deliver powerful capabilities with low energy consumption, meeting the demands of modern technologies aiming for sustainability without sacrificing performance. As a cornerstone of smart technology advancement, Monolithic Microsystems set the stage for future integrated solutions in complex tech ecosystems.
The NeuroSense AI Chip, an ultra-low power neuromorphic frontend, is engineered for wearables to address the challenges of power efficiency and data accuracy in health monitoring applications. This tiny AI chip is designed to process data directly at the sensor level, which includes tasks like heart rate measurement and human activity recognition. By performing computations locally, NeuroSense minimizes the need for cloud connections, thereby ensuring privacy and prolonging battery life. The chip excels in accuracy, significantly outperforming conventional algorithm-based solutions by offering three times better heart rate accuracy. This is achieved through its ability to reduce power consumption to below 100µW, allowing users to experience extended device operation without frequent recharging. The NeuroSense supports a simple configuration setup, making it suitable for integration into a variety of wearable devices such as fitness trackers, smartwatches, and health monitors. Its capabilities extend to advanced features like activity matrices, enabling devices to learn new human activities and classify tasks according to intensity levels. Additional functions include monitoring parameters like oxygen saturation and arrhythmia, enhancing the utility of wearable devices in providing comprehensive health insights. The chip's integration leads to reduced manufacturing costs, a smaller IC footprint, and a rapid time-to-market for new products.
TUNGA is an innovative multi-core RISC-V SoC designed to advance high-performance computing and AI workflows using posit arithmetic. This SoC is equipped with multiple CRISP-cores, enabling efficient real-number computation with the integration of posit numerical representations. The TUNGA system exploits the power of the posit data type, known for offering enhanced computational precision and reduced bit-utilization compared to traditional formats. A standout feature of TUNGA is its fixed-point accumulator structure, QUIRE, which ensures exact calculation of dot products for vector lengths extending to approximately 2 billion elements. This precision makes it highly suitable for tasks in cryptography, AI, and data-intensive computations that require high accuracy. In addition, TUNGA leverages a pool of FPGA gates designed for hardware reconfiguration, facilitating the acceleration of processes such as data center services by optimizing task execution paths and supporting non-standard data types. TUNGA is fully programmable and supports various arithmetic operations for specialized computational needs, particularly within high-demand sectors like AI and machine learning, where processing speed and accuracy are critical. By integrating programmability through FPGA gates, users can tailor the SoC for specific workloads, thereby allowing Calligo's TUNGA to stand out as an adaptable element of next-generation cloud and edge computing solutions.
The Semidynamics Vector Unit is a powerful processing element designed for applications requiring complex parallel computations such as those found in machine learning and AI workloads. Its remarkable configurability allows it to be adapted for different data types ranging from 8-bit integers to 64-bit floating-point numbers, supporting standards up to RVV 1.0. The unit can perform a wide array of operations due to its included arithmetic units for addition, subtraction, and complex tasks like multiplication and logic operations. PHased to deliver exceptional performance, the Vector Unit leverages a cross-vector-core network that ensures high bandwidth connectivity among its vector cores, capable of scaling up to 32 cores. This feature helps maximize operational efficiency, allowing tasks to be distributed across multiple cores for optimized performance and power efficiency. Its design caters to extensive data path configurations, allowing users to choose from DLEN options ranging from 128 bits to an impressive 2048 bits in width. Moreover, this Vector Unit supports flexible hardware setups by aligning vector register lengths (VLEN) with the data path requirements, offering up to an 8X ratio between VLEN and DLEN. This capability enhances its adaptability, allowing it to absorb memory latencies effectively, making it particularly suitable for AI inferencing tasks that require rapid iteration and heavy computational loads. Its integration with existing Semidynamics technologies like the Tensor Unit ensures a seamless performance boost across hardware configurations.
The SAKURA-II AI Accelerator by EdgeCortix is a high-efficiency device designed for demanding edge applications. This cutting-edge accelerator is tailored for fast, real-time, single-batch AI inferencing with low energy consumption and minimal footprint. The hardware enables users to process complex generative AI models such as Llama 2 and Stable Diffusion. By supporting multi-billion parameter models, it excels in areas like Vision, Language, and Audio AI applications. Its edge efficiency is further augmented by its high utilization of AI compute, surpassing many competing solutions. This ensures superior functionality across vast applications.
The Titanium Ti375 is an innovative FPGA from Efinix, designed for applications requiring high-density logic and low power consumption. This component integrates the advanced Efinix Quantum compute fabric with extensive I/O capabilities, making it highly suitable for a range of demanding tasks. Featuring a hardened RISC-V block and versatile SerDes transceivers, the Ti375 is built to handle complex tasks such as compute acceleration and machine learning applications. One of the standout features of the Ti375 is its SerDes transceiver, capable of supporting multiple protocols including PCIe 4.0, Ethernet SGMII, and 10GBase-KR, offering data rates from 1.25 Gbps to 16 Gbps. This makes it ideal for high-speed network and communication applications. The FPGA's RISC-V block enhances processing capabilities with a quad-core configuration, efficiently balancing hardware and software tasks. For developers, the Ti375 offers configurable high-speed I/O, supporting a variety of single-ended and differential standards, including MIPI and LVDS. This configurability ensures that developers can tailor I/O to meet specific system needs, facilitating seamless integration into existing infrastructures. Additionally, the Titanium series' power and performance metrics ensure that it is adept for applications in automotive, industrial automation, machine vision, and more.
ChipJuice is an advanced reverse engineering tool specifically crafted to facilitate the exploration and analysis of Integrated Circuit (IC) architectures. This innovative platform equips users with the ability to uncover the intricate details of IC designs, regardless of their complexity or size. By utilizing an intuitive workflow, ChipJuice expedites the extraction process, enabling the conversion of electronic imagery of chip internals into comprehensive architectural descriptions such as netlists, GDSII, and Verilog files. Primarily aimed at law enforcement agencies, chip manufacturers, and integrators, ChipJuice addresses various hardware security challenges. It is instrumental in identifying potential backdoors, assessing chip security, and determining technology infringement. With functionality that spans from education to the recovery of obsolete devices, ChipJuice stands out with its ability to handle diverse chip types—be it microcontrollers, microprocessors, or SoCs—across varying material compositions and node technologies. Continuously refined through practical application, ChipJuice incorporates intelligent features like "Automated Standard Cell Research," which improves efficiency in further analyses by cataloging identified cell patterns. This feature significantly accelerates the analysis of subsequent chips, making it a versatile and indispensable tool in the realm of IC reverse engineering.
The General Purpose Accelerator, known as Aptos, from Ascenium is a state-of-the-art innovation designed to redefine computing efficiency. Unlike traditional CPUs, Aptos is an integrated solution that enhances performance across all generic software applications without requiring modifications to the code. This technology utilizes a unique compiler-driven approach and simplifies CPU architecture, making it adept at executing a wide range of computational tasks with significant energy efficiency. At the heart of the Aptos design is the capability to handle tasks typically managed by out-of-order RISC CPUs, yet it does so with a streamlined and parallel approach, allowing data centers to move past current performance barriers. The architecture is aligned with the LLVM compiler, ensuring that it remains source-code compatible with numerous programming languages, an advantage when future-proofing investments in software infrastructure. The efficiency gains from Aptos are notably due to its ability to handle standard high-level language software in a more efficient manner, achieving nearly four times the efficiency compared to existing state-of-the-art CPUs. This is instrumental in reducing the energy footprint of data centers globally, aligning with broader sustainability goals by cutting carbon emissions and operational costs. Moreover, this makes the technology extremely appealing to organizations seeking tangible ROI through energy savings and performance enhancements.
The NeuroVoice AI Chip offers a revolutionary solution for voice processing, harnessing neuromorphic frontend technology to provide ultra-low power consumption and superior noise resilience. It is designed for hearables and smart voice-controlled devices, ensuring efficient operation even in high-noise environments. This chip processes audio data on-device, eliminating the need for continuous cloud connectivity while enhancing user privacy. By integrating NASP technology, the NeuroVoice chip excels in voice activity detection, smart voice control, and voice extraction, making it ideal for applications in earbuds, voice access systems, and smart home devices. Its ability to only transmit or recognize human voice while muting background sounds significantly improves command clarity and user interactions, especially in environments prone to irregular noises. The chip is designed to adapt to various audio inputs, providing capabilities for clear communication, enhancing speech intelligibility, and offering features like voice passthrough in hearing aids. With power consumption kept below 150µW, it allows for prolonged device usage and efficient battery management, making it an ideal component for modern voice-activated devices and hearing assistance technologies.
The DQ80251 is a soft core of a highly advanced and high-performance microcontroller, finely tuned for speed and efficiency. Designed with a revolutionary Quad-Pipelined architecture, this IP offers compatibility with both 16-bit and 32-bit instructions, making it versatile for a wide range of applications. The core significantly enhances the performance capabilities of embedded systems, being more than 75 times faster than the original 8051 processor developed by Intel. Its efficient design not only accelerates operations but also optimizes power usage, catering to demanding computational tasks while maintaining power efficiency. The microcontroller core provides a remarkable execution rate of 75.08 Dhrystones per million instructions per second (DMIPS), which translates into a substantial improvement in speed for embedded solutions. Its compact design, measuring just 13,500 gates in size, enables it to be integrated into systems without requiring extensive resources, making it an economical choice for developers. Furthermore, the core supports an extensive memory space of up to 8 megabytes, accommodating complex applications with ease. Built with flexibility in mind, it can seamlessly integrate into various hardware setups, from simple embedded devices to more sophisticated systems. The DQ80251 core integrates seamlessly with numerous peripherals and debugging tools, including the DoCD (Digital on Chip Debugger), effectively supporting software development and system diagnostics. This capability allows developers to conduct thorough testing and debugging directly on-chip, significantly reducing development time and accelerating product deployment. Overall, the DQ80251 microcontroller from DCD-SEMI stands out as a cornerstone for developers aiming to create high-performance, resource-efficient, and scalable electronics applications.
FlexNoC Interconnect is a state-of-the-art network-on-chip (NoC) solution designed to enhance the design and performance of system-on-chip (SoC) devices. As a physically aware product, it supports complex and diverse protocols, meeting the rigorous demands of high-performance computing. This interconnect fabric reduces design iterations and accelerates timing closure by providing early issue detection and facilitating efficient signal routing. The FlexNoC utilizes a highly configurable mesh topology that facilitates connections across SoC components, ensuring robust data transfer with minimal power consumption. Its design supports multiple clock and voltage domains, enabling dynamic power management and enabling the seamless integration of various IP blocks including CPU, GPU, and AI processors. The adaptability of FlexNoC makes it suitable for a wide range of applications from small embedded devices to extensive data center systems. With its focus on scalability, the FlexNoC Interconnect also incorporates advanced traceability features that monitor and optimize on-chip data traffic, further enabling developers to refine system performance. Its compatibility with the latest semiconductor processes ensures that it remains a future-proof choice for designers looking to enhance connectivity within SoC designs.
The MimicPro Prototyping System is a high-performance platform designed to elevate the prototyping process for ASICs and pre-silicon software development. Utilizing FPGA technology, it enables rapid development by significantly cutting down both design validation time and rerun efforts. MimicPro provides exceptional system visibility and debugging capabilities that allow developers to efficiently address software bugs without the need for expensive emulation equipment.<br> <br> Scalability is at the heart of the MimicPro System, allowing enterprises to prototype large ASIC families with a flexible setup ranging from 1 to 32 FPGAs. This modular design ensures the system can grow alongside business needs, whether it’s used for AI, vision, processor, communication, or other SoCs. Additionally, built-in security features enable encrypted prototyping, safeguarding user IPs in both cloud and enterprise deployments.<br> <br> The system boasts 120MGates of performance, equipped with a memory analyzer and compiler for enhanced functionality. Local memory debugging further assists in minimizing time-to-market while ensuring product reliability and efficiency. With support for cloud operations and seamless integration with current digital tools, MimicPro stands as a comprehensive solution catering to modern prototyping requirements.
RISC-V Core-hub Generators are central to InCore's strategy to streamline SoC design by allowing developers full control over customizing core-hubs at both the ISA and microarchitecture levels. This system grants engineers unprecedented flexibility, enabling them to tailor design specifications to unique needs, ensuring performance optimization and integration ease within complex systems. These generators are a key component in developing next-generation processors that demand high efficiency and rapid deployment. By revolutionizing the traditional approach to processor customization, these Core-hub Generators significantly cut down development time and costs. They facilitate a seamless design experience, where conversion from ideas to silicon is made fluid through their YAML hardware description approach, known for its agility and precision. This innovative method showcases InCore's dedication to transforming semiconductor design into a more accessible and faster process, which is vital in today's fast-moving tech landscape. These RISC-V Generators are not just tools but a comprehensive solution that address the challenges of modern processor design. By allowing detailed configuration, they support robust security measures and efficient resource management, thus minimizing overheads. This adaptability makes them suitable for diverse applications, reinforcing InCore's mission to democratize access to high-level, customizable silicon solutions.
The Tyr AI Processor Family is a robust line of chips designed to optimize performance and efficiency for a wide range of AI applications, including autonomous driving and edge AI deployments. Each processor in the Tyr lineup is fully programmable and engineered to operate seamlessly with any host processor or algorithm. These processors offer substantial computational power, fostered by cutting-edge architecture that supports high-level language programming. This approach ensures ease of integration and fast deployment of new algorithms.<br><br>The processors are tailored for next-generation AI tasks and are capable of effectively managing the complexities of both AI and digital signal processing (DSP) workflows. They capitalize on multi-core design for scalability, ensuring that performance metrics remain robust even as computational demands increase. Additionally, Tyr processors maintain a low footprint both in terms of physical space and power consumption, making them ideal for cost-sensitive and power-sensitive applications.<br><br>The family offers a range of options such as the Tyr1, Tyr2, and Tyr4, each differentiated by their compute power and core configurations. This diversity ensures that users can select an option best suited for their specific operational requirements, whether seeking maximal power or minimal resource consumption. Furthermore, the processors are ISO26262/ASIL-D ready, enhancing their applicability in automotive and safety-critical environments.
The Ultra-Low-Power 64-Bit RISC-V Core by Micro Magic, Inc. is a groundbreaking processor core designed for efficiency in both power consumption and performance. Operating at a mere 10mW at 1GHz, this core leverages advanced design techniques to run at reduced voltages without sacrificing performance, achieving clock speeds up to 5 GHz. This innovation is particularly valuable for applications requiring high-speed processing while maintaining low power usage, making it ideal for portable and battery-operated devices. Micro Magic's 64-bit RISC-V architecture embraces a streamlined design that minimizes energy consumption and maximizes processing throughput. The core's architecture is optimized for high performance under low-power conditions, which is essential for modern electronics that require prolonged battery life and environmental sustainability. This core supports a wide range of applications from consumer electronics to automotive systems where energy efficiency and computational power are paramount. The RISC-V core also benefits from Micro Magic's suite of integrated design tools, which streamline the development process and enable seamless integration into larger systems. With a focus on reducing total ownership costs and enhancing product life cycle, Micro Magic's RISC-V core stands out as a versatile and eco-friendly solution in the semiconductor market.
UltraRISC Technology's UR-E Processor Core is engineered for high-efficiency computation, especially suited for edge computing scenarios. It harnesses RISC-V architecture's advantages, ensuring a high degree of efficiency for power-sensitive applications. This core focuses on delivering optimum performance across different application domains, accommodating specific computational requirements with its customizable configuration. Offering compatibility with the RISC-V instruction set, the UR-E core can be tailored to specific needs, thus optimizing the processing capability for edge devices. It's designed to support essential processor core resources and SoC-level IP, thereby enabling robust systems that require efficient processing power. The UR-E core exemplifies UltraRISC's dedication to delivering versatile, high-performance computing solutions.
The Azurite Core-hub is crafted to offer a highly efficient RISC-V implementation, specifically aimed at minimizing both area and power consumption. This core-hub is ideally suited for embedded applications, where space and power efficiency are paramount. It demonstrates InCore's commitment to high-efficiency solutions that do not compromise on performance, making it an excellent choice for systems requiring compact and power-conservative designs. This particular Core-hub is characterized by its proficiency in integrating standard RISC-V UnCore components such as interrupt controllers and debugging tools, ensuring broad functionality within a streamlined architecture. Designed with a focus on sustaining excellent performance with reduced resources, the Azurite Core-hub stands as a benchmark for RISC-V cores capable of delivering top-notch performance while conserving energy and space. Azurite's versatility is a key feature, allowing it to be a foundational component in systems that need efficient computation in controlled environments. Its ability to seamlessly integrate into broader systems makes it a preferred choice for industries that value robust yet compact solutions.
GIRD Systems develops highly configurable IP cores, designed to be hardware-agnostic, which are instrumental in digital signal processing (DSP), communications, and electronic warfare (EW) applications. These cores are defined through inferred VHDL implementations and can be efficiently adapted onto several platforms including Xilinx, Altera, and Microsemi FPGAs, besides being applicable for ASICs and various synthesis targets. The company's approach eliminates the need for re-coding across different target platforms, drastically reducing the time-to-market and fostering multi-target design adaptability. With performance and portability at its heart, these IP cores facilitate the deployment of sophisticated algorithms across disparate hardware, while maintaining consistency and performance standards. By enabling manufacturers to target a broad array of applications without having to rewrite underlying code, GIRD Systems' IP cores streamline the development process and enhance design flexibility. These offerings are backed by comprehensive support and documentation to ensure seamless integration into existing workflows, effectively advancing signal processing capabilities within diverse operational frameworks.
Forest Runtime is a robust execution platform for neural network models, providing a retargetable and modular architecture suited for various hardware environments, from data centers to mobile and TinyML applications. It facilitates the seamless execution of compiled models using common C++ APIs along with C and Python bindings, making it versatile for a broad range of AI applications. The runtime supports 'hot batching' technology, allowing models to alter batch sizes and input shapes at runtime, which is essential for modern neural networks like BERT and DLRM. This feature maximizes hardware utilization and minimizes response time by dynamically connecting various system resources efficiently. It also incorporates unique 'bridging' technology that allows resource-sharing among multiple accelerator cards and sessions, thereby supporting scalability and high throughput in server environments.
SystemBIST is a sophisticated, vendor-independent plug-and-play IC tailored for the flexible configuration of FPGAs on PCBs. The aim of this solution is to simplify the FPGA configuration and testing processes by eliminating the need for PROMs and complex firmware. SystemBIST utilizes the IEEE 1149.1 and IEEE 1532 standards, ensuring broad applicability across different vendor products while maintaining high quality and configuration flexibility.\n\nThe hallmark of SystemBIST is its ability to execute deterministic Built-In Self Test (BIST) for PCBs and system-level components. This significantly simplifies the testing process as embedded test patterns and scripts can be reused, providing reliable testing scenarios without additional software efforts. SystemBIST’s capabilities extend beyond FPGA programming, enabling re-programming and testing of CPLDs and other components in the field, ensuring products remain adaptable and secure.\n\nWith comprehensive support from Intellitech’s Eclipse Test Development Environment, SystemBIST provides a centralized framework for the generation, validation, and application of test suites, integrating seamlessly with existing system configurations. This capability is complemented by SystemBIST’s robust anti-tamper and counterfeit protection, featuring embedded security measures to safeguard the integrity of designs.
The Altera Agilex 7 F-Series SoC is a versatile module that blends the strengths of Intel's Agilex FPGAs with an integrated system-on-chip (SoC). Built on Intel's 10nm SuperFin process technology, this FPGA is optimized for a variety of applications across multiple sectors, including bioscience, quantum computing, and electronic warfare. It features advanced high-performance capabilities, enabling system designers to implement complex functions with efficiency. The system-on-module (SoM) configuration is equipped with heat management components like active heatsinks and fans, making it ideal for embedded applications. The integration of various processing elements within a single silicon platform enhances the module's efficiency, offering reduced power consumption and improved performance. By providing pre-validated and tested modules, the Agilex 7 F-Series SoC facilitates ease of use and accelerates time-to-market for developers. This module is complemented by compatible carrier boards, which expand its utility in diverse applications while allowing seamless integration for complex embedded designs.
The Altera Stratix 10 SoC is a powerful module utilizing Intel's Stratix FPGA technology to achieve remarkable levels of data processing and bandwidth handling. Its design incorporates high-speed transceivers and extensive logic capabilities, suited for applications in data centers and communications. The embedded system-on-chip (SoC) form factor ensures efficient data management and processing within compact spaces. Supporting advanced connectivity options, including PCI Express and Ethernet, this module paves the way for rapid data transfer and enhanced computational tasks. With its focus on applications that demand high reliability and performance, the Stratix 10 SoC is a perfect fit for industries requiring robust embedded solutions.
The Nerve IIoT Platform is an advanced solution designed for machine builders and industrial operators looking to harness the benefits of digital connectivity and data-driven strategies. It operates as both an edge computing platform and a software management system that bridges the gap between industrial machinery and IT systems. Nerve enables users to collect, process, and utilize machine data on-site in real-time, enhancing operational efficiency and enabling predictive maintenance and digital twin applications. One of the standout features of the Nerve platform is its flexibility and scalability. Users can deploy it on standard industrial hardware, ranging from simple gateways to more complex IPCs, allowing businesses to start small and scale as needed without substantial infrastructure changes. The platform supports various industry-standard communication protocols, facilitating seamless data exchange and integration into existing setups. Docker, CODESYS, and other open-source technologies are leveraged to ensure that application deployment is both efficient and flexible. Security and real-time operation are at the forefront of Nerve's offerings. The platform is certified under IEC 62443-4-1, ensuring robust protection against cyber threats while maintaining system integrity and continuity. Furthermore, its real-time data processing capabilities ensure that critical operational decisions are made swiftly and accurately, empowering businesses to optimize production and reduce downtimes. Nerve’s architecture also allows for remote management and updates, which significantly reduces the need for on-site technical interventions.
The AMD Zynq Ultrascale+ MPSoC module offers a merger of multifaceted processing power with field-programmable capabilities, specially targeted towards intricate and defense-critical applications. It brings together the best of ARM computing and FPGA scalability, making it ideal for markets such as radio communication and electronic surveillance. The module's architecture maximizes efficiency and adaptability, highlighting its strengths in handling complex algorithms and tasks in real-time. It is particularly valued for its versatile application in precision-demanding sectors, providing unmatched control and implementation versatility.