All IPs > Platform Level IP > Processor Core Independent
In the ever-evolving landscape of semiconductor technologies, processor core independent IPs play a crucial role in designing flexible and scalable digital systems. These semiconductor technologies offer the versatility of enabling functionalities independent of a specific processor core, making them invaluable for a variety of applications where flexibility and reusability are paramount.
Processor core independent semiconductor IPs are tailored to function across different processor architectures, avoiding the constraints tied to any one specific core. This characteristic is particularly beneficial in embedded systems, where designers aim to balance cost, performance, and power efficiency while ensuring seamless integration. These IPs provide solutions that accommodate diverse processing requirements, from small-scale embedded controllers to large-scale data centers, making them essential components in the toolkit of semiconductor design engineers.
Products in this category often include memory controllers, I/O interfaces, and various digital signal processing blocks, each designed to operate autonomously from the central processor's architecture. This independence allows manufacturers to leverage these IPs in a broad array of devices, from consumer electronics to automotive systems, without the need for extensive redesigns for different processor families. Moreover, this flexibility championed by processor core independent IPs significantly accelerates the time-to-market for many devices, offering a competitive edge in high-paced industry environments.
Furthermore, the adoption of processor core independent IPs supports the development of customized, application-specific integrated circuits (ASICs) and system-on-chips (SoCs) that require unique configurations, without the overhead of processor-specific dependencies. By embracing these advanced semiconductor IPs, businesses can ensure that their devices are future-proof, scalable, and capable of integrating new functionalities as technologies advance without being hindered by processor-specific limitations. This adaptability positions processor core independent IPs as a vital cog in the machine of modern semiconductor design and innovation.
KPIT provides state-of-the-art solutions for vehicle diagnostics and aftersales service, essential for the maintenance of software-intensive vehicles. The iDART framework offers comprehensive diagnostic functions and enhances service operations through AI-guided systems. This framework facilitates the transition to a unified, future-proof diagnostic ecosystem, reducing downtime and ensuring optimal vehicle performance. KPIT's solutions streamline complex diagnostic processes, making vehicles easier to manage and repair over their lifespans, enhancing customer satisfaction and loyalty.
The Metis AIPU PCIe AI Accelerator Card provides an unparalleled performance boost for AI tasks by leveraging multiple Metis AIPUs within a single setup. This card is capable of delivering up to 856 TOPS, supporting complex AI workloads such as computer vision applications that require rapid and efficient data processing. Its design allows for handling both small-scale and extensive applications with ease, ensuring versatility across different scenarios. By utilizing a range of deep learning models, including YOLOv5 and ResNet-50, this AI accelerator card processes up to 12,800 FPS for ResNet-50 and an impressive 38,884 FPS for MobileNet V2-1.0. The card’s architecture enables high throughput, making it particularly suited for video analytics tasks where speed is crucial. The card also excels in scenarios that demand high energy efficiency, providing best-in-class performance at a significantly reduced operational cost. Coupled with the Voyager SDK, the Metis PCIe card integrates seamlessly into existing AI systems, enhancing development speed and deployment efficiency.
The ORC3990 is a sophisticated System on Chip (SoC) solution designed for low-power sensor-to-satellite communication within the LEO satellite spectrum. Utilizing Totum's DMSS technology, it achieves superior doppler performance, facilitating robust connectivity for IoT devices. The integration of an RF transceiver, power amplifiers, ARM CPUs, and memory components makes it a highly versatile module. Leveraging advanced power management technology, this SoC supports a battery life that exceeds ten years, even within industrial temperature ranges from -40 to +85°C. It's optimized for usage with Totum's global LEO satellite network, ensuring substantial indoor signal coverage without the need for additional GNSS components. Efficiency is a key feature, with the chip operating in the 2.4 GHz ISM band, providing unparalleled connectivity regardless of location. Compact in design, comparable in size to a business card, and designed for easy mounting, the ORC3990 offers sought-after versatility for IoT applications. The ability to function with excellent TCO in terms of cost compared to terrestrial IoT solutions makes it a valuable asset for any IoT deployment focused on sustainability and longevity.
KPIT's engineering and design solutions focus on accelerating vehicle development through new-age design and simulation techniques. This approach enables cost-efficient transformation and adherence to sustainability standards, offering integrated electrification solutions and cutting-edge design methodologies. KPIT's solutions in vehicle engineering support electric and hybrid vehicle innovation with advanced CAD tools, virtual prototyping, and AI augmentation.
Origin E1 neural engines are expertly adjusted for networks that are typically employed in always-on applications. These include devices such as home appliances, smartphones, and edge nodes requiring around 1 TOPS performance. This focused optimization makes the E1 LittleNPU processors particularly suitable for cost- and area-sensitive applications, making efficient use of energy and reducing processing latency to negligible levels. The design also incorporates a power-efficient architecture that maintains low power consumption while handling always-sensing data operations. This enables continuous sampling and analysis of visual information without compromising on efficiency or user privacy. Additionally, the architecture is rooted in Expedera's packet-based design which allows for parallel execution across layers, optimizing performance and resource utilization. Market-leading efficiency with up to 18 TOPS/W further underlines Origin E1's capacity to deliver outstanding AI performance with minimal resources. The processor supports standard and proprietary neural network operations, ensuring versatility in its applications. Importantly, it accommodates a comprehensive software stack that includes an array of tools such as compilers and quantizers to facilitate deployment in diverse use cases without requiring extensive re-designs. Its application has already seen it deployed in over 10 million devices worldwide, in various consumer technology formats.
Designed for high-performance environments such as data centers and automotive systems, the Origin E8 NPU cores push the limits of AI inference, achieving up to 128 TOPS on a single core. Its architecture supports concurrent running of multiple neural networks without context switching lag, making it a top choice for performance-intensive tasks like computer vision and large-scale model deployments. The E8's flexibility in deployment ensures that AI applications can be optimized post-silicon, bringing performance efficiencies previously unattainable in its category. The E8's architecture and sustained performance, alongside its ability to operate within strict power envelopes (18 TOPS/W), make it suitable for passive cooling environments, which is crucial for cutting-edge AI applications. It stands out by offering PetaOps performance scaling through its customizable design that avoids penalties typically faced by tiled architectures. The E8 maintains exemplary determinism and resource utilization, essential for running advanced neural models like LLMs and intricate ADAS tasks. Furthermore, this core integrates easily with existing development frameworks and supports a full TVM-based software stack, allowing for seamless deployment of trained models. The expansive support for both current and emerging AI workloads makes the Origin E8 a robust solution for the most demanding computational challenges in AI.
The Origin E2 family of NPU cores is tailored for power-sensitive devices like smartphones and edge nodes that seek to balance power, performance, and area efficiency. These cores are engineered to handle video resolutions up to 4K, as well as audio and text-based neural networks. Utilizing Expedera’s packet-based architecture, the Origin E2 ensures efficient parallel processing, reducing the need for device-specific optimizations, thus maintaining high model accuracy and adaptability. The E2 is flexible and can be customized to fit specific use cases, aiding in mitigating dark silicon and enhancing power efficiency. Its performance capacity ranges from 1 to 20 TOPS and supports an extensive array of neural network types including CNNs, RNNs, DNNs, and LSTMs. With impressive power efficiency rated at up to 18 TOPS/W, this NPU core keeps power consumption low while delivering high performance that suits a variety of applications. As part of a full TVM-based software stack, it provides developers with tools to efficiently implement their neural networks across different hardware configurations, supporting frameworks such as TensorFlow and ONNX. Successfully applied in smartphones and other consumer electronics, the E2 has proved its capabilities in real-world scenarios, significantly enhancing the functionality and feature set of devices.
The AndeShape platform supports AndesCore processor system development by providing a versatile infrastructure composed of Platform IP, hardware development platforms, and an ICE Debugger. This allows for efficient integration and rapid prototyping, offering flexibility in design and development across a comprehensive set of hardware options. It aims to reduce design risk and accelerate time-to-market.
The H-Series PHY supports the latest in high-speed memory interfaces, specifically engineered for comprehensive compatibility with a range of memory standards. By generating extensive support ecosystems including Design Acceleration Kits, this PHY aims to streamline integration and enhance performance for high-demand applications. With significant emphasis on minimizing die size, while optimizing both performance and latency, this PHY is particularly useful for graphics and compute-intensive operations where speed and reliability are paramount.
The AndesCore range includes high-performance 32-bit and 64-bit CPU core families tailored for emerging market segments. These processors, adhering to the RISC-V technology and AndeStar V5 ISA, span across several series such as the Compact, 25-Series, 27-Series, 40-Series, and 60-Series. Each series is designed for specific applications, offering features like high per-MHz performance, vector processing units (VPUs), branch prediction, and memory management enhancements like MemBoost, which optimizes memory bandwidth and latency.
Origin E6 NPU cores are cutting-edge solutions designed to handle the complex demands of modern AI models, specializing in generative and traditional networks such as RNN, CNN, and LSTM. Ranging from 16 to 32 TOPS, these cores offer an optimal balance of performance, power efficiency, and feature set, making them particularly suitable for premium edge inference applications. Utilizing Expedera’s innovative packet-based architecture, the Origin E6 allows for streamlined multi-layer parallel processing, ensuring sustained performance and reduced hardware load. This helps developers maintain network adaptability without incurring latency penalties or the need for hardware-specific optimizations. Additionally, the Origin E6 provides a fully scalable solution perfect for demanding environments like next-generation smartphones, automotive systems, and consumer electronics. Thanks to a comprehensive software suite based around TVM, the E6 supports a broad span of AI models, including transformers and large language models, offering unparalleled scalability and efficiency. Whether for use in AR/VR platforms or advanced driver assistance systems, the E6 NPU cores provide robust solutions for high-performance computing needs, facilitating numerous real-world applications.
The RISC-V Core-hub Generators by InCore Semiconductors provide an advanced level of customization for developing processor cores. These generators are tailored to support configuration at both the Instruction Set Architecture (ISA) and the microarchitecture levels, enabling designers to create cores that meet specific functional and performance needs. By allowing detailed customization, these generators support a wide range of applications, from simple embedded devices to complex industrial systems. The Core-hub Generators are designed to streamline the SoC development process by integrating optimized SoC fabrics and UnCore components such as programming interfaces, debugging tools, and interrupt controllers. This comprehensive integration facilitates efficient communication between different processing units and peripheral devices, thereby enhancing overall system performance. InCore's generators leverage the flexibility and scalability of RISC-V technology, promoting innovation and accelerating the deployment of custom silicon solutions. This makes them an ideal choice for designers looking to build cutting-edge SoCs with enhanced capabilities and reduced development times.
The Chimera GPNPU series stands as a pivotal innovation in the realm of on-device artificial intelligence computing. These processors are engineered to address the challenges faced in machine learning inference deployment, offering a unified architecture that integrates matrix, vector, and scalar operations seamlessly. By consolidating what traditionally required multiple processors, such as NPUs, DSPs, and real-time CPUs, into a single processing core, Chimera GPNPU reduces system complexity and optimizes performance. This series is designed with a focus on handling diverse, data-parallel workloads, including traditional C++ code and the latest machine learning models like vision transformers and large language models. The fully programmable nature of Chimera GPNPUs allows developers to adapt and optimize model performance continuously, providing a significant uplift in productivity and flexibility. This capability ensures that as new neural network models emerge, they can be supported without the necessity of hardware redesign. A remarkable feature of these processors is their scalability, accommodating intensive workloads up to 864 TOPs and being particularly suited for high-demand applications like automotive safety systems. The integration of ASIL-ready cores allows them to meet stringent automotive safety standards, positioning Chimera GPNPU as an ideal solution for ADAS and other automotive use cases. The architecture's emphasis on reducing memory bandwidth constraints and energy consumption further enhances its suitability for a wide range of high-performance, power-sensitive applications, making it a versatile solution for modern automotive and edge computing.
The Ultra-Low-Power 64-Bit RISC-V Core by Micro Magic, Inc. is a groundbreaking processor core designed for efficiency in both power consumption and performance. Operating at a mere 10mW at 1GHz, this core leverages advanced design techniques to run at reduced voltages without sacrificing performance, achieving clock speeds up to 5 GHz. This innovation is particularly valuable for applications requiring high-speed processing while maintaining low power usage, making it ideal for portable and battery-operated devices. Micro Magic's 64-bit RISC-V architecture embraces a streamlined design that minimizes energy consumption and maximizes processing throughput. The core's architecture is optimized for high performance under low-power conditions, which is essential for modern electronics that require prolonged battery life and environmental sustainability. This core supports a wide range of applications from consumer electronics to automotive systems where energy efficiency and computational power are paramount. The RISC-V core also benefits from Micro Magic's suite of integrated design tools, which streamline the development process and enable seamless integration into larger systems. With a focus on reducing total ownership costs and enhancing product life cycle, Micro Magic's RISC-V core stands out as a versatile and eco-friendly solution in the semiconductor market.
The Dynamic Neural Accelerator II Architecture (DNA-II) by EdgeCortix is a sophisticated neural network IP core structured for extensive parallelism and efficiency enhancement. Distinguished by its run-time reconfigurable interconnects between computing elements, DNA-II supports a broad spectrum of AI models, including both convolutional and transformer networks, making it suitable for diverse edge AI applications. With its scalable performance starting from 1K MACs, the DNA-II architecture integrates easily with many SoC and FPGA applications. This architecture provides a foundation for the SAKURA-II AI Accelerator, supporting up to 240 TOPS in processing capacity. The unique aspect of DNA-II is its utilization of advanced data path configurations to optimize processing parallelism and resource allocation, thereby minimizing on-chip memory bandwidth limitations. The DNA-II is particularly noted for its superior computational capabilities, ensuring that AI models operate with maximum efficiency and speed. Leveraging its patented run-time reconfigurable data paths, it significantly increases hardware performance metrics and energy efficiency. This capability not only enhances the compute power available for complex inference tasks but also reduces the power footprint, which is critical for edge-based deployments.
GSHARK is a family of GPU cores targeted for embedded devices, such as digital cameras and automotive systems. Known for its high performance and low power consumption, GSHARK effectively minimizes the CPU load while maintaining outstanding graphic rendering capabilities. This solution supports high reliability, proven by millions of shipments within commercial silicon. The architecture of GSHARK adapts PC, smartphone, and console-grade graphics technologies to embedded systems, enhancing the user experience in human-machine interfaces. Its capability to handle dynamic graphics with low resource usage makes it an ideal choice for embedded systems.
The software-defined High PHY from AccelerComm is tailored for ARM processor architectures, offering flexibility to accommodate a wide array of platforms. This configurable solution can operate independently or, if needed, with hardware acceleration, depending on the application's specific power and performance needs. It's suitable for use in situations where adaptability is paramount and is optimized to minimize latency and maximize efficiency across different platforms, adhering to O-RAN standards, and enhancing system capability by integrating with other IP offerings such as accelerators.
DMP’s ZIA Stereo Vision solution is engineered for depth perception and environmental sensing, leveraging stereo image inputs to compute real-time distance maps. This technology applies stereo matching techniques such as Semi-Global Matching (SGM) to accurately deduce depth from 4K resolution images, paving the way for precision applications in autonomous vehicles and robotic systems. The system employs pre- and post-processing techniques to optimize image alignment and refine depth calculations, achieving high accuracy with low latency. By interfacing through the AMBA AXI4 protocol, it ensures easy integration into existing processing chains, requiring minimal reconfiguration for operation. DMP’s expertise in small footprint, high-performance IP allows the ZIA Stereo Vision to deliver industry-leading depth perception capabilities while maintaining a compact profile, suitable for embedded applications needing robust environmental mapping.
The Arria 10 System on Module (SoM) is designed with a focus on embedded and automotive vision applications, leveraging the robust capabilities of the Arria 10 SoC devices. Packed in a compact form factor of 8 cm by 6.5 cm, this module incorporates a multitude of interfaces, offering immense flexibility and a wide array of functionalities suitable for high-performance tasks. This SoM integrates an Altera Arria 10 FPGA with 160 to 480 KLEs along with a Cortex A9 Dual Core CPU, ensuring efficient computational performance. It features a sophisticated power management system and support for dual DDR4 memory interfaces, optimizing power distribution and memory efficiency for safety-critical applications which demand precision and reliability. The Arria 10 SoM is crafted to maximize data throughput, with capabilities such as PCIe Gen3 x8 and 10/40 GBit/s Ethernet interfaces, alongside dedicated clocking arrangements for minimized jitter. Supporting high-speed data transmissions via multiple LVDS lanes and USB interfaces, it's engineered to handle demanding operations in sophisticated systems requiring rapid processing speeds and expansive interfacing.
Time-Triggered Ethernet (TTEthernet) represents a cutting-edge networking solution, engineered for applications requiring deterministic real-time communication. By implementing time scheduling methods, TTEthernet ensures high precision and fault-tolerant communication over Ethernet, catering to the needs of cyber-physical systems across aerospace, automotive, and industrial sectors. The protocol is distinguished by its capability to handle safety and high availability requirements directly at the network level, thus bypassing application layers. This level of assurance is attained through a robust system of redundancy management and fault-tolerant clock synchronization, as standardized in SAE AS6802.\n\nThe protocol promotes a standardized approach to network design, facilitating seamless integration with a wide array of Ethernet components and maintaining compatibility with IEEE 802.3 standards. This feature is crucial for simplifying the complexities of high-availability and fault-tolerant systems. By allowing for precise scheduling and replicated packet transmission, TTEthernet significantly enhances network reliability. In cases of network faults, this feature ensures that communication is maintained without interruption, supporting fail-operational safety systems.\n\nAdditionally, TTEthernet is scalable from smaller networks to expansive systems, maintaining optimal safety, performance, and security levels. The platform's ability to partition traffic classes permits the convergence of different protocols within a single network, enhancing its adaptability and application range. As a result, TTEthernet underpins numerous critical applications by ensuring both real-time responsiveness and robust data handling capabilities, ultimately reducing time-to-market for integrated solutions.
The NeuroSense AI Chip, an ultra-low power neuromorphic frontend, is engineered for wearables to address the challenges of power efficiency and data accuracy in health monitoring applications. This tiny AI chip is designed to process data directly at the sensor level, which includes tasks like heart rate measurement and human activity recognition. By performing computations locally, NeuroSense minimizes the need for cloud connections, thereby ensuring privacy and prolonging battery life. The chip excels in accuracy, significantly outperforming conventional algorithm-based solutions by offering three times better heart rate accuracy. This is achieved through its ability to reduce power consumption to below 100µW, allowing users to experience extended device operation without frequent recharging. The NeuroSense supports a simple configuration setup, making it suitable for integration into a variety of wearable devices such as fitness trackers, smartwatches, and health monitors. Its capabilities extend to advanced features like activity matrices, enabling devices to learn new human activities and classify tasks according to intensity levels. Additional functions include monitoring parameters like oxygen saturation and arrhythmia, enhancing the utility of wearable devices in providing comprehensive health insights. The chip's integration leads to reduced manufacturing costs, a smaller IC footprint, and a rapid time-to-market for new products.
The NeuroVoice AI Chip offers a revolutionary solution for voice processing, harnessing neuromorphic frontend technology to provide ultra-low power consumption and superior noise resilience. It is designed for hearables and smart voice-controlled devices, ensuring efficient operation even in high-noise environments. This chip processes audio data on-device, eliminating the need for continuous cloud connectivity while enhancing user privacy. By integrating NASP technology, the NeuroVoice chip excels in voice activity detection, smart voice control, and voice extraction, making it ideal for applications in earbuds, voice access systems, and smart home devices. Its ability to only transmit or recognize human voice while muting background sounds significantly improves command clarity and user interactions, especially in environments prone to irregular noises. The chip is designed to adapt to various audio inputs, providing capabilities for clear communication, enhancing speech intelligibility, and offering features like voice passthrough in hearing aids. With power consumption kept below 150µW, it allows for prolonged device usage and efficient battery management, making it an ideal component for modern voice-activated devices and hearing assistance technologies.
The Tyr Superchip is engineered to facilitate high performance computing in AI and data processing domains, with a focus on scalability and power efficiency. Designed around a revolutionary multi-core architecture, it features fully programmable cores that are suitable for any AI or general-purpose algorithms, ensuring high flexibility and adaptability. This product is crucial for industries requiring cutting-edge processing capabilities without the overhead of traditional systems, thanks to its support for CUDA-free operations and efficient algorithm execution that minimizes energy consumption.
The SiFive Essential family is all about customization and configurability, meeting diverse market conditions with a range from low-power embedded systems to high-performance application processors. SiFive's Essential processors boast scalability in performance, allowing them to cater to applications like IoT devices and real-time control. This customization extends to their architecture, facilitating specific configurations to match exact needs, highlighting their utility in varied industrial applications.
Efinix's Titanium Ti375 FPGA is a high-density device designed for applications demanding low power consumption alongside robust processing capabilities. This FPGA is embedded with the Quantum® compute fabric, an architecture that delivers significant power, performance, and area benefits. Notably, the Ti375 incorporates a hardened quad-core RISC-V block, various high-speed transceivers for protocols like PCIe Gen4, and supports LPDDR4 DRAM for efficient memory operations. The Ti375 excels in its ability to facilitate high-speed communications and sophisticated data processing, owing in part to its multiple full-duplex transceivers. These transceivers support a swath of industries by enabling data rates up to 16 Gbps for PCIe interfaces or up to 10 Gbps for Ethernet links. Additionally, the FPGA is equipped with advanced MIPI D-PHY functionalities, crucial for applications in the fields of imaging and vision. This versatile FPGA supports the development of complex systems, from industrial automation to advanced consumer electronics, by offering features like extensive I/O configurations and on-board debugging capabilities. With the comprehensive Efinity software suite, developers can streamline the transition from RTL design to bitstream generation, enhancing project timelines significantly. Whether used as a standalone solution or integrated into a larger system, the Ti375 provides an adaptable framework for modern design challenges.
The General Purpose Accelerator, known as Aptos, from Ascenium is a state-of-the-art innovation designed to redefine computing efficiency. Unlike traditional CPUs, Aptos is an integrated solution that enhances performance across all generic software applications without requiring modifications to the code. This technology utilizes a unique compiler-driven approach and simplifies CPU architecture, making it adept at executing a wide range of computational tasks with significant energy efficiency. At the heart of the Aptos design is the capability to handle tasks typically managed by out-of-order RISC CPUs, yet it does so with a streamlined and parallel approach, allowing data centers to move past current performance barriers. The architecture is aligned with the LLVM compiler, ensuring that it remains source-code compatible with numerous programming languages, an advantage when future-proofing investments in software infrastructure. The efficiency gains from Aptos are notably due to its ability to handle standard high-level language software in a more efficient manner, achieving nearly four times the efficiency compared to existing state-of-the-art CPUs. This is instrumental in reducing the energy footprint of data centers globally, aligning with broader sustainability goals by cutting carbon emissions and operational costs. Moreover, this makes the technology extremely appealing to organizations seeking tangible ROI through energy savings and performance enhancements.
ChipJuice is an innovative tool for reverse engineering integrated circuits, uniquely designed for comprehensive IC analysis and security evaluation. This versatile software tool supports digital forensics, backdoor research, and IP infringement investigations, making it indispensable for labs, government entities, and semiconductor companies. ChipJuice operates efficiently across various IC architectures, allowing users to extract internal architecture details and generate detailed reports, including netlists and hardware description language files. The tool's intuitive user interface and high-performance processing algorithms make it accessible to users of different expertise levels, from beginners to advanced professionals. It is capable of handling a wide range of chips, regardless of their size, technology node, or complexity, providing a scalable solution for diverse reverse engineering tasks. ChipJuice's automated standard cell research feature further enhances its analytic capabilities, enabling efficient identification and cataloging of IC components. Moreover, ChipJuice facilitates a seamless analysis process by simply using electronic images of a chip's digital core. This allows for precise signal tracing and thorough IC evaluation, supporting its users' strategic objectives in security audits and architectural exploration. ChipJuice is an essential tool for those seeking to delve deep into ICs for security validation and developmental insights.
SystemBIST is a revolutionary product within Intellitech’s IP portfolio, providing unparalleled capabilities for FPGA configuration and JTAG-based embedded testing. As a flexible plug-and-play device, SystemBIST allows the configuration of a wide range of IEEE 1532 or IEEE 1149.1 compliant FPGAs and CPLDs. This makes it highly versatile for design engineers looking to develop high-quality, self-testable products that can be reconfigured in the field, extending product life and adaptability. Built on patented architectures, SystemBIST simplifies typical configuration challenges by embedding built-in self-test (BIST) capabilities, thereby eliminating the need for complex software-driven BIT solutions. This device effectively compresses and stores test patterns and scripts within FLASH memory, allowing for comprehensive PCB testing wherever power is available. SystemBIST caters to a broad spectrum of applications, from normal operation reconfigurations to safe field updates, ensuring that the underlying firmware remains secure against potential threats like trojan bitstreams. Its user-friendly development tools facilitate rapid deployment and debugging, offering developers an efficient means of maintaining system integrity and performance over time.
The TySOM Boards family, developed by Aldec, is a range of versatile embedded system prototyping boards tailored to support rapid development of complex applications. With options featuring FPGAs like the Xilinx Zynq UltraScale+, Zynq-7000, and the Microchip PolarFire SoC, these prototyping boards cater to a wide array of sectors from automotive to industrial automation. These boards are distinguished by their compatibility with industry standard interfaces such as FMC and BPX, allowing for flexible expansion through Aldec's extensive range of daughter cards. This adaptability makes TySOM boards an asset for projects in artificial intelligence, machine learning, and Internet of Things (IoT), especially where complex, high-performance embedded systems are in demand. Providing a robust platform for both prototyping and real-world deployment, TySOM boards ensure developers can move swiftly from concept to prototype, achieving efficiency in the design lifecycle. This practicality extends to applications such as automotive ADAS, embedded vision, and edge-processing, making the family integral to contemporary embedded solution projects.
The 1000 Series by Akeana offers high-performance processing capabilities designed to tackle data-heavy computational tasks. With features aimed at enhancing throughput and power efficiency, these processors are suitable for environments that require robust processing power like AI on the edge, industrial automation, and automotive sensing. Supporting rich operating systems like Android and Linux, the 1000 Series is crafted to ensure superior performance with efficient power management, making it a prime choice for modern high-demand applications.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
The Altera Agilex 7 F-Series SoC offers unparalleled flexibility and high-performance capabilities, enabling the seamless implementation of complex algorithms into a single chip. Targeting sectors like bioscience and radar systems, this SoC optimizes system performance while minimizing power consumption. Its design includes a heatsink with an integrated fan for effective thermal management, ensuring reliable operation in demanding applications. The integration capabilities of the Agilex 7 F-Series make it a versatile choice for developers seeking efficient system solutions.
Built around the Intel Stratix 10 FPGA, the Altera Stratix 10 SoC delivers robust transceiver bandwidth ideal for applications requiring high-performance processing. Suitable for complex computing environments, such as analytic and video processing, this SoC ensures enhanced control and integration through its internal system-on-chip structure. The potent combination of FPGA architecture and integrated circuits makes it a prime choice for agile deployments across various high-demand sectors.
The D68000 is a modern 16/32-bit processor core, binary-compatible with the historical M68000 series, ensuring a seamless integration into a wide array of legacy designs and new applications. It maintains a 16-bit data bus architecture, featuring the DoCD-BDM on-chip debugger, which facilitates extensive debug capabilities essential for complex system development. With compatibility extending to the 68020's efficient CPU32 version, the D68000 caters to industries needing sophisticated processing solutions merged with the reliability of well-known standards. Its seamless functionality in systems handling sophisticated digital computation, such as industrial controls and automated instrumentation, makes it a prime candidate for modern systems requiring both compatibility and innovation. As industries seek robust, tested solutions, the D68000 shines with its robust design and the ability to maintain precise functionalities while transitioning modern architecture demands. It is particularly suited for businesses striving for reliability in fields like robotics, telecommunications, and precision machinery.
EFLX eFPGA is a cutting-edge embedded FPGA solution that offers unprecedented flexibility and adaptability for SoC designs. It allows developers to enhance their chip designs by incorporating reconfigurable logic that can be adjusted even post-production. This capability enables shorter time-to-market and reduced costs by allowing rapid prototyping and customization without full chip redesigns. The EFLX eFPGA is particularly beneficial for applications requiring frequent updates or where multiple variants of a product are needed. By integrating reprogrammable logic into an SoC, it provides a scalable solution adaptable to various applications, from consumer electronics to complex communication systems. Its architecture is optimized for fast configuration and supports a wide range of processes and nodes, ensuring compatibility with major foundries. Moreover, the EFLX eFPGA's innovative approach reduces latency and power consumption compared to traditional FPGA solutions. Its seamless integration into existing hardware platforms makes it an ideal choice for upgrading legacy systems with new functionalities, giving companies a competitive edge in rapidly evolving markets.
The RISC-V CPU IP U Class offers advanced capabilities suited for Linux and edge computing applications with its enhanced 32-bit architecture and MMU support. This IP extends its flexibility and configurability, making it a strategic fit for environments that require robust data processing and management. The U Class IP is designed to cater to computationally demanding tasks, delivering exceptional performance and efficiency. It integrates security features and functional safety options, aligning with industry standards to ensure secure and reliable operations. Developers utilizing the U Class IP benefit from access to a rich ecosystem of tools, including comprehensive SDKs and operating systems like Linux, which aid in expedited development and deployment processes. This makes it an optimal choice for projects aiming to leverage the full potential of edge computing.
The SiFive Performance family is designed for superior compute density and performance efficiency, particularly for datacenter and AI workloads. The family includes 64-bit out-of-order cores ranging from 3 wide to 6 wide configurations, supported by dedicated vector engines for AI tasks. This design ensures a blend of energy efficiency and area optimization, making these cores ideal for handling complex, data-intensive tasks while maintaining a compact footprint.
Developed to support various standard and custom applications, these ASICs are based on ARM's M-Class architecture, which is renowned for its high performance and low power consumption. Suitable for use in embedded systems, they offer efficient processing capabilities while maintaining minimal power utilization, making them ideal for a wide array of applications. The versatility and adaptability of these ASICs make them perfect for industries ranging from consumer electronics to industrial automation.
Extoll’s Network on Chip (NOC-X) technology is intricately designed to optimize on-chip data routing, facilitating high-performance communication and processing capabilities within semiconductor devices. This IP solution is essential for developers seeking to create dynamic, scalable microarchitectures that demand efficient data traffic management. NOC-X is crafted to align with the needs of complex SoC designs, ensuring seamless data flow and reduced bottlenecks. NOC-X demonstrates remarkable efficiency in handling diverse data loads, making it suitable for a wide range of applications, including high-performance computing and advanced communication technologies. It integrates efficiently with Extoll's suite of IPs, ensuring compatibility and performance enhancements across devices. The technology is compatible with modern process nodes from 12nm to 28nm, showcasing its adaptability and relevance in contemporary semiconductor design. With its robust architecture and scalability, NOC-X aids in achieving superior system performance and reliability, enabling developers to push the boundaries of their chip designs. Extoll provides robust support and documentation for integrating NOC-X into your systems, reflecting their commitment to facilitating innovation through powerful interconnect solutions.
The SAKURA-II AI Accelerator represents the pinnacle of EdgeCortix's innovation, offering cutting-edge efficiency in AI inferencing tasks particularly suited for generative AI applications. This high-performance accelerator is powered by the low-latency Dynamic Neural Architecture (DNA), handling multi-billion parameters with remarkable adequacy. Its adaptability allows it to transform inputs across various modalities such as vision, language, and audio. Particularly distinguished for its compactness and minimal power consumption, the SAKURA-II is engineered to deliver excellent results even in constrained physical environments. It supports vast model complexities with impressive DRAM bandwidth and is equipped for low-latency operations, ensuring fast real-time Batch=1 processing. Notably, its hardware capacity efficiently approximates activation functions, extending substantial support for structures like Llama 2, Stable Diffusion, and ViT. Critically, the SAKURA-II is designed for flexibility, offering robust processing of vision and generative AI workloads in an 8W power envelope. It features a highly-operative memory infrastructure that enhances its performance with sophisticated DRAM bandwidths and ample memory capacity for handling complex data streams and facilitating superior AI compute utility. Its intelligent design aligns with the current move towards sophisticated, low-power AI applications.
The AI Inference Platform by SEMIFIVE is designed to facilitate cutting-edge AI computations within custom SoC designs. This platform is particularly structured to meet the high-performance needs of AI-driven applications, powered by a quad-core SiFive U74 RISC-V CPU, supported by a high-speed LPDDR4x memory interface. It integrates PCIe Gen4 for enhanced data transfer capabilities and comes equipped with dedicated vision processing and DC acceleration functionalities. This platform offers a robust infrastructure for developing AI applications, with a significant emphasis on delivering rapid deployment and efficient operations. It makes AI integration seamless through pre-verified components and a flexible architecture, reducing the overall time from concept to deployment. The platform promises a configuration that minimizes risks while maintaining the potential for scalability and future enhancements. SEMIFIVE’s AI Inference Platform is ideally suited for applications like big data analytics and high-performance AI workloads. By leveraging a finely tuned ecosystem and a constellation of pre-integrated IPs, the platform not only speeds up the development process but also ensures reliability and robustness in delivering AI-based solutions.
The AIoT Platform engineered by SEMIFIVE is meticulously crafted to cater to the burgeoning demands of AI-powered IoT applications. It is built on the efficient and versatile SiFive dual-core U54 RISC-V architecture, paired with the LPDDR4x memory interface to ensure robust data handling and processing. Complemented by a comprehensive range of connectivity options, including USB3.0 and MIPI CSI, this platform is primed for edge compute applications. Specifically designed for smart home, robotics, and other AIoT applications, the platform aims to fuse intelligence with connectivity. It empowers developers by offering ready-to-use components that speed up development cycles, thereby facilitating quicker market entry strategies. These features are combined with an ideal balance of power consumption and performance to accommodate the typical requirements of IoT devices. The platform's flexibility in integrating various sensors and peripherals, alongside its strong processing capabilities, positions it perfectly for tasks that require real-time processing and responsiveness, working seamlessly in networked environments to provide intelligent, connected experiences.
The Digital Radio (GDR) from GIRD Systems is a sophisticated, adaptable, and multi-channel software-defined radio platform. It boasts high-speed signal processing capabilities, making it suitable for both embedded and standalone applications. Built on a flexible single board design, the GDR can be tailored to meet diverse requirements. This ranges from single-channel operations to complex MIMO configurations, all while supporting full or half duplex transceivers across a wide frequency spectrum. Such versatility makes it an ideal choice for a myriad of communication scenarios, ensuring robust performance even in demanding conditions.
eSi-ADAS is a comprehensive suite of radar processing IP aimed at enhancing the performance of Advanced Driver Assistance Systems (ADAS). Engineered to work efficiently in automotive and UAV applications, this radar accelerator IP offers significant improvements in situational awareness. Its functionality extends to a wide array of radar systems, integrating smoothly with automotive Tier 1 and 2 suppliers.\n\nThe suite excels with its diverse range of hardware accelerator functions, from FFT engines designed for radar systems to configurable Constant False Alarm Rate (CFAR) engines and a robust Kalman Filter engine. These components improve tracking capabilities and integrate smoothly into existing systems, offering recalibration flexibility and high precision across multiple radar applications.\n\nMoreover, eSi-ADAS offers superior object tracking abilities, allowing for real-time tracking of hundreds of objects while managing radar target processing effortlessly. Its compact design supports low power consumption, which optimizes processing loads on main ADAS ECUs, CPUs, or DSPs. The IP meets the stringent demands of modern ADAS by incorporating advanced processing techniques such as 3D Fast Fourier Transforms and Kalman Filtering, facilitating real-time data processing for enhanced object tracking.
The hypr_risc Radar DSP Accelerator distinguishes itself as a high-efficiency signal processor tailored for advanced radar applications. Built around a custom RISC-V core, hypr_risc achieves optimal processing speeds necessary for time-sensitive applications like advanced driver-assistance systems (ADAS). This DSP accelerator serves as a crucial interface between radar front-end modules and data management systems, ensuring high-performance processing with minimal latency. hypr_risc's adaptability allows it to integrate seamlessly with various RF front-end manufacturers, thanks to its highly configurable architecture. This flexibility extends to the core level, offering customization in power consumption, core sizing, cache configurations, and more. As a result, hypr_risc provides a cost-effective, scalable solution for complex radar processing tasks. The technology behind hypr_risc is particularly beneficial for imaging radar systems requiring precise object range and motion tracking. By leveraging open-source RISC-V technology, it lowers development costs and accelerates time-to-market, positioning itself as a valuable asset in the rapidly evolving radar technology landscape.
Ncore Cache Coherent Interconnect represents a robust solution for managing cache coherency in multi-core ASICs, offering high bandwidth and low-latency communication fabric suitable for both legacy and modern processors. Specialized for handling the challenges associated with multi-core system integration, this interconnect simplifies the complexities of synchronization and verification while optimizing power efficiency. Its comprehensive suite of features includes support for true heterogeneous coherency with AMBA CHI and ACE protocols, empowering developers to create efficient, coherent SoCs that cater to a variety of architectures including ARM and RISC-V. Designed with scalability in mind, Ncore is accommodating of small embedded systems as well as extensive designs. Its mesh topology and network configurations enable flexible and scalable integration, allowing seamless adoption in various industrial and consumer applications. Ncore's functional safety capabilities are certified under ISO 26262, ensuring compliance with safety-critical standards, making it suitable for automotive and other high-assurance sectors. Ncore enhances overall performance by reducing off-chip memory access, leveraging advanced snoop filters to provide seamless data transport and optimized cache utilization. Its capacity to automate Fault Modes Effects and Diagnostic Analysis (FMEDA) and maintain configurability for different initiator IPs makes it an essential tool for modern SoC developers wanting to achieve market differentiation through advanced system integration.
These derivatives are designed to provide exceptional interface capabilities for various sensor-based applications. With an emphasis on precision and efficiency, they enable seamless integration of sensors into larger systems, ensuring accurate data acquisition and processing. The IP supports a broad spectrum of sensor types, making it flexible for applications that require real-time monitoring and feedback. This adaptability is crucial for sectors like IoT, where sensor integration is critical.
TUNGA is an innovative multi-core RISC-V SoC designed to advance high-performance computing and AI workflows using posit arithmetic. This SoC is equipped with multiple CRISP-cores, enabling efficient real-number computation with the integration of posit numerical representations. The TUNGA system exploits the power of the posit data type, known for offering enhanced computational precision and reduced bit-utilization compared to traditional formats. A standout feature of TUNGA is its fixed-point accumulator structure, QUIRE, which ensures exact calculation of dot products for vector lengths extending to approximately 2 billion elements. This precision makes it highly suitable for tasks in cryptography, AI, and data-intensive computations that require high accuracy. In addition, TUNGA leverages a pool of FPGA gates designed for hardware reconfiguration, facilitating the acceleration of processes such as data center services by optimizing task execution paths and supporting non-standard data types. TUNGA is fully programmable and supports various arithmetic operations for specialized computational needs, particularly within high-demand sectors like AI and machine learning, where processing speed and accuracy are critical. By integrating programmability through FPGA gates, users can tailor the SoC for specific workloads, thereby allowing Calligo's TUNGA to stand out as an adaptable element of next-generation cloud and edge computing solutions.
The Vega eFPGA from Rapid Silicon represents an innovative leap in providing customizable FPGA capabilities to System-on-Chip (SoC) designs. This eFPGA is designed to deliver flexibility and efficiency, allowing a seamless integration that enhances performance without raising costs. By embedding programmability directly into SoCs, Vega eFPGA facilitates diverse and adaptable computing needs. Structured with three configurable tile types – CLB, BRAM, and DSP – the Vega eFPGA is engineered for optimal performance. The CLB comprises eight 6-input lookup tables (LUTs), each offering dual independent outputs. It includes features like fast adders with carry chains and programmable registers, ensuring computational versatility. The BRAM component supports 36Kb dual-port memory, adaptable as 18Kb split memory configurations. The DSP tile incorporates an 18×20 multiplier with a 64-bit accumulator, supporting complex mathematical processing. Rapid Silicon's Vega eFPGA is optimized for scalability, providing flexibility in tile configurations to meet varied application requirements. It ensures ample compatibility with existing systems through seamless SoC integration, proprietary Raptor EDA tools, and robust IP libraries. These capabilities enable Vega to offer bespoke solutions tailored to specific end-user needs.
Monolithic Microsystems by IMEC represent the frontier of microelectronics, where advanced functionalities are integrated directly on top of CMOS technology. This innovation allows for high-performance and miniaturization within a single compact package. Utilizing diverse process modules, including silicon photonics and MEMS, these microsystems offer vast potential across industries from healthcare to automotive. These systems combine multiple technologies such as photonics, optics, and electronics co-integrated into a singular structure, leading to enhanced operational efficiency and reduced costs in mass manufacturing.