All IPs > Platform Level IP > Processor Core Dependent
In the realm of semiconductor IP, the Processor Core Dependent category encompasses a variety of intellectual properties specifically designed to enhance and support processor cores. These IPs are tailored to work in harmony with core processors to optimize their performance, adding value by reducing time-to-market and improving efficiency in modern integrated circuits. This category is crucial for the customization and adaptation of processors to meet specific application needs, addressing both performance optimization and system complexity management.
Processor Core Dependent IPs are integral components, typically found in applications that require robust data processing capabilities such as smartphones, tablets, and high-performance computing systems. They can also be implemented in embedded systems for automotive, industrial, and IoT applications, where precision and reliability are paramount. By providing foundational building blocks that are pre-verified and configurable, these semiconductor IPs significantly simplify the integration process within larger digital systems, enabling a seamless enhancement of processor capabilities.
Products in this category may include cache controllers, memory management units, security hardware, and specialized processing units, all designed to complement and extend the functionality of processor cores. These solutions enable system architects to leverage existing processor designs while incorporating cutting-edge features and optimizations tailored to specific application demands. Such customizations can significantly boost the performance, energy efficiency, and functionality of end-user devices, translating into better user experiences and competitive advantages.
In essence, Processor Core Dependent semiconductor IPs represent a strategic approach to processor design, providing a toolkit for customization and optimization. By focusing on interdependencies within processing units, these IPs allow for the creation of specialized solutions that cater to the needs of various industries, ensuring the delivery of high-performance, reliable, and efficient computing solutions. As the demand for sophisticated digital systems continues to grow, the importance of these IPs in maintaining competitive edge cannot be overstated.
The NMP-750 is engineered as a performance accelerator tailored for edge computing applications that demand robust processing power and versatility. It is ideally deployed in environments such as automotive, AMR and UAV systems, AR/VR applications, as well as smart infrastructure projects like smart buildings, factories, and cities. Its design principles aim to enhance security and surveillance systems while supporting advanced telecommunications solutions. This comprehensive IP can attain up to 16 TOPS, thereby addressing needs for high throughput and efficiency in data processing tasks. The NMP-750 includes up to 16 MB of local memory, utilizing either RISC-V or Arm Cortex-R or A 32-bit CPUs to manage operational complexity through three 128-bit AXI4 interfaces for host, CPU, and data processes. This infrastructure not only ensures rapid data-handling capabilities but also optimizes system-level operations for various emerging technologies. Ideal for managing multi-camera stream processing and enhancing spectral efficiency, it is equally suited for mobility and autonomous control systems—key to future smart city and factory applications. The NMP-750's support for comprehensive automation and data analytics offers companies the potential to develop cutting-edge technologies, driving industry standards across domains.
KPIT's Connected Vehicle Solutions leverage modern cloud and edge computing to enhance the connectivity features of today’s vehicles. This technology supports secure data management, advanced analytics, and comprehensive solutions for real-time vehicle connectivity. The platform is engineered to provide enriched data-driven insights, enabling OEMs to better handle vehicle data, improve cybersecurity measures, and ensure compliance with emerging regulatory standards. By transforming data into strategic advantages, KPIT aids automotive manufacturers in delivering enhanced user experiences and operational efficiencies.
The NMP-350 is a low-power and cost-effective end-point accelerator designed to cater to applications across various industries. This accelerator finds its niche in markets such as automotive, AIoT, and Industry 4.0, where efficiency and scalability are critical. With potential applications in driver authentication, digital mirrors, and personalized user experiences, it is also applicable in predictive maintenance systems, machine automation, and health monitoring. Technically, the NMP-350 boasts an impressive capacity of up to 1 TOPS (Tera Operations Per Second), supported by up to 1 MB of local memory. The system is based on a flexible architecture utilizing either RISC-V or Arm Cortex-M 32-bit CPUs, accommodating three AXI4 interfaces with 128 bits each dedicated to host, CPU, and data processes. This composition assures its capability to handle a multitude of tasks efficiently while maintaining a low power profile. Its integration into smart appliances and wearable technologies showcases its versatility, providing industry players with a robust solution for building smarter and more reliable products. As industries move towards more interconnected and intelligent systems, the NMP-350 provides the necessary technology to drive innovation forward.
The NMP-550 stands as a performance efficiency accelerator, particularly crafted for applications that demand high computational power combined with energy efficiency. This IP is especially suited for markets including automotive, mobile devices, AR/VR, and security-focused technologies. Its applicability spares a wide spectrum, fostering innovation in driver monitoring, fleet management, and advanced image or video analytics. Along with intruder detection and compliance systems, it bolsters its utility in medical devices for enhanced diagnostic capabilities. Technologically, the NMP-550 delivers up to 6 TOPS, which provides a significant boost in data processing capability. It features up to 6 MB of local memory, ensuring swift and effective data management. The design is underpinned by a choice of RISC-V or Arm Cortex-M or A 32-bit CPUs, along with three AXI4 interfaces supporting 128 bits each, allocated for host, CPU, and data handling. Such specification allows this accelerator to proficiently tackle tasks of various computational demands with resilience and efficiency. Its design caters to cross-disciplinary needs, making it an excellent fit for drone operations, robotics, and security systems requiring real-time processing and decision-making capabilities. With the inherent ability to process substantially more data at improved efficiencies, this IP aligns well with the future of immersive and interactive application deployments.
Cortus's High Performance RISC-V Processor represents the pinnacle of processing capability, designed for demanding applications that require high-speed computing and efficient task handling. It features the world’s fastest RISC-V 64-bit instruction set architecture, implemented in an Out-of-Order (OoO) execution core, supporting both single-core and multi-core configurations for unparalleled processing throughput. This processor is particularly suited for high-end computing tasks in environments ranging from desktop computing to artificial intelligence workloads. With integrated features such as a multi-socket cache coherent system and an on-chip vector plus AI accelerator, it delivers exceptional computation power, essential for tasks such as bioinformatics and complex machine learning models. Moreover, the processor includes coherent off-chip accelerators, such as CNN accelerators, enhancing its utility in AI-driven applications. The design flexibility extends its application to consumer electronics like laptops and supercomputers, positioning the High Performance RISC-V Processor as an integral part of next-gen technology solutions across multiple domains.
The Automotive AI Inference SoC by Cortus is a cutting-edge chip designed to revolutionize image processing and artificial intelligence applications in advanced driver-assistance systems (ADAS). Leveraging RISC-V expertise, this SoC is engineered for low power and high performance, particularly suited to the rigorous demands of autonomous driving and smart city infrastructures. Built to support Level 2 to Level 4 autonomous driving standards, this AI Inference SoC features powerful processing capabilities, enabling complex image processing algorithms akin to those used in advanced visual recognition tasks. Designed for mid to high-end automotive markets, it offers adaptability and precision, key to enhancing the safety and efficiency of driver support systems. The chip's architecture allows it to handle a tremendous amount of data throughput, crucial for real-time decision-making required in dynamic automotive environments. With its advanced processing efficiency and low power consumption, the Automotive AI Inference SoC stands as a pivotal component in the evolution of intelligent transportation systems.
The AndeShape Platforms include a range of systems designed for developing with AndesCore processors. These platforms are split into categories such as microcontroller platforms and FPGA development kits. They offer integrated solutions with pre-configured IP blocks to simplify the design process for complex systems. Through its assortment of hardware development tools, AndeShape platforms cater to various stages of product development from inception to demonstration, making it easier for engineers to create efficient, scalable solutions.
NeuroMosAIc Studio is a comprehensive software platform designed to accelerate AI development and deployment across various domains. This platform serves as an essential toolkit for transforming neural network models into hardware-optimized formats specific for AiM Future's accelerators. With broad functionalities including conversion, quantization, compression, and optimization of neural networks, it empowers AI developers to enhance model performance and efficiency. The studio facilitates advanced precision analysis and adjustment, ensuring models are tuned to operate optimally within hardware constraints while maintaining accuracy. Its capability to generate C code and provide runtime libraries aids in seamless integration within target environments, enhancing the capability of developers to leverage AI accelerators fully. Through this suite, companies gain access to an array of tools including an NMP compiler, simulator, and support for NMP-aware training. These tools allow for optimized training stages and quantization of models, providing significant operational benefits in AI-powered solutions. NeuroMosAIc Studio, therefore, contributes to reducing development cycles and costs while ensuring top-notch performance of deployed AI applications.
Certus Semiconductor specializes in advanced RF/analog designs that encompass a broad range of solutions, from individual components to complete wireless transceivers. Their expertise extends to developing cutting-edge low-power wireless front-end technologies. They offer silicon-proven RF IP, full-chip RF products, and next-generation wireless IPs that support high-quality communication standards, including LTE, WiFi, and GNSS. Equipped with custom PLLs capable of operating at frequencies up to 6GHz, these solutions ensure low phase noise and minimal jitter for precise applications.
The Metis AIPU PCIe AI Accelerator Card represents a powerful computing solution for high-demand AI applications. This card, equipped with a single Metis AI Processing Unit, delivers extraordinary processing capabilities, reaching up to 214 Tera Operations Per Second (TOPS). Designed to handle intensive computing tasks, it is particularly suited for applications requiring substantial computational power and rapid data processing, such as real-time video analytics and AI-driven operations in various industrial and retail environments. This accelerator card integrates seamlessly into PCIe slots, providing developers with an easy-to-deploy solution enhanced by Axelera AI's Voyager Software Development Kit. The kit simplifies the deployment of neural networks, making it a practical tool for both seasoned developers and newcomers to AI technology. The card's power efficiency is a standout feature, aimed at reducing operational costs while ensuring optimal performance. With its innovative architecture, the Metis AIPU PCIe AI Accelerator Card not only meets but exceeds the needs of modern AI applications, ensuring users can harness significant processing power without the overheads associated with traditional systems.
The Cortus Lotus 1 is a multifaceted microcontroller that packs a robust set of features for a range of applications. This cost-effective, low-power SoC boasts RISC-V architecture, making it suitable for advanced control systems such as motor control, sensor interfacing, and battery-operated devices. Operating up to 40 MHz, its RV32IMAFC CPU architecture supports floating-point operations and hardware-accelerated integer processing, optimizing performance for computationally demanding applications. Designed to enhance code density and reduce memory footprint, Lotus 1 incorporates 256 KBytes of Flash memory and 24 KBytes of RAM, enabling the execution of complex applications without external memory components. Its six independent 16-bit timers with PWM capabilities are perfectly suited for controlling multi-phase motors, positioning it as an ideal choice for power-sensitive embedded systems. This microcontroller's connectivity options, including multiple UARTs, SPI, and TWI controllers, ensure seamless integration within a myriad of systems. Lotus 1 is thus equipped to serve a wide range of market needs, from personal electronics to industrial automation, ensuring flexibility and extended battery life across sectors.
Bluespec's Portable RISC-V Cores are crafted to provide extensive flexibility and compatibility across numerous FPGA platforms, including industry leaders such as Achronix, Xilinx, and Lattice. These cores are designed to support both Linux and FreeRTOS, offering developers a broad range of applications in system development and software integration. Leveraging standard open-source development tools, these cores allow engineers to adopt, modify, and deploy RISC-V solutions with minimal friction. This simplifies the development process and enhances compatibility with various hardware scenarios, promoting an ecosystem where innovation can thrive without proprietary constraints. The Portable RISC-V Cores cater to developers who require adaptable and scalable solutions for diverse projects. By accommodating different FPGA platforms and supporting a wide range of development environments, they represent a versatile choice for implementing cutting-edge designs in the RISC-V architecture space.
VisualSim Architect is a sophisticated software platform dedicated to the modeling and simulation of system performance, power, and functionality. It empowers system engineers to explore designs virtually, measuring potential bottlenecks and power consumption before actual production begins. The platform aids in validating different hardware and software architectures, ensuring that the system is designed for optimal efficiency and performance. It also enables users to create virtual prototypes that mimic real-life system behaviors, thus facilitating a deeper understanding of potential implementation challenges. This preemptive approach allows companies to fine-tune their designs, ensuring that all components work harmoniously, thereby reducing risk and accelerating time-to-market. Furthermore, the platform's flexible system-level modeling capabilities cater to a diverse range of application fields, from automotive to consumer electronics.
Positioned for entry-level server and computing use, the SCR9 packs a high-performance 64-bit RISC-V design with server-level features. Its dual-issue 12-stage pipeline combines with sophisticated memory systems and a network-on-chip L3 cache, allowing for enhanced processing across demanding applications. With support for advanced security, vector operations, and robust multitask environments, SCR9 is fit for servers, video processing, and high-end embedded computing, reinforcing flexibility with AOSP and Linux compatibility.
The SiFive Performance family of processors is crafted to address the demands of data center workloads, multimedia processing, networking, and storage applications. Featuring 64-bit, out-of-order cores, they provide a wide range of design options tailored to workload necessities. This family includes processors ranging from three to six-wide out-of-order cores, equipped with dedicated vector engines optimized for AI workloads. These processors deliver top-tier performance within energy-efficient parameters, making them highly suitable for mobile devices, consumer electronics, and edge computing infrastructure.
The Time-Triggered Protocol (TTP) is a communication protocol engineered to address the growing complexity and safety requirements of distributed electronic networks. TTP facilitates reliable network operation for modern vehicle systems, reducing lifecycle costs and supporting seamless integration. This protocol offers significant improvements in communication bandwidth compared to traditional systems such as ARINC 429 and CAN. TTP's capacity for deterministic communication aids in designing advanced integrated systems, offering robust solutions for time- and safety-critical applications, backed by mature development tools and standard components.
The iniDSP is a versatile 16-bit fixed-point digital signal processor core crafted for system-on-chip applications. Emphasizing adaptability and performance, this DSP is suitable for power-sensitive applications such as hearing aids to more demanding processing tasks in audio compression and signal conditioning. It benefits from a 100% technology-independent design, aligning it well with both FPGA and ASIC environments.<br/><br/>The core is based on the architecture of the CD2450A from Clarkspur Inc., ensuring a high degree of reusability and performance optimization. It features a 16x16 signed/unsigned multiplier with a 40-bit accumulator, tailoring it for efficient algorithm implementation while minimizing power consumption.<br/><br/>Supporting a comprehensive development ecosystem, the iniDSP provides support for assembly, linking, and debugging, enabling efficient development and deployment of DSP applications. Its robust design makes it a compelling alternative to off-chip DSPs for embedded systems, enhancing the overall system efficiency and reducing latency.
The Prodigy Universal Processor by Tachyum Inc. is engineered to integrate the functionalities of CPUs, GPGPUs, and TPUs into a unified, efficient architecture. This makes it an ideal candidate for applications demanding high performance, such as AI, high-performance computing (HPC), and hyperscale data centers. The processor stands out with its capacity to offer unparalleled performance while maintaining reduced energy consumption and maximizing utilization rates within server environments. Prodigy processors boast multiple SKUs offering configurations like 64-bit cores per socket running at speeds beyond 5 GHz, support for numerous DDR5 memory channels, and extensive PCI Express 5.0 lanes for high data throughput. These features enable the Prodigy to handle diverse and intensive computational tasks with ease, reducing the necessity for separate heterogeneous processing units. One of the key advantages of the Prodigy architecture is its ability to execute existing x86 applications without any modifications through a robust emulation layer. This capability simplifies transitions for enterprises looking to consolidate their systems under the Prodigy umbrella, allowing for significant operational efficiencies and cost savings. The Prodigy processor thus positions itself as a future-proof choice for enterprises aiming to modernize their data processing capabilities.
Dyumnin Semiconductors' RISCV SoC is a powerful, 64-bit quad-core server-class processor tailored for demanding applications, integrating a multifaceted array of subsystems. Key features include an AI/ML subsystem equipped with a tensor flow unit for optimized AI operations, and a robust automotive subsystem supporting CAN, CAN-FD, and SafeSPI interfaces.\n\nAdditionally, it includes a multimedia subsystem comprising HDMI, Display Port, MIPI, camera subsystems, Gfx accelerators, and digital audio, offering comprehensive multimedia processing capabilities. The memory subsystem connects to various prevalent memory protocols like DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring vast compatibility.\n\nThe RISCV SoC's design is modular, allowing for customization to meet specific end-user applications, offering a flexible platform for creating SoC solutions with bespoke peripherals. It also doubles as a test chip available as an FPGA for evaluative purposes, making it ideal for efficient prototyping and development workflows.
The Menta eFPGA IP Cores v5 are designed to be highly versatile, high-density programmable logic blocks embedded within SoCs or ASICs. These cores help designers define precise resource requirements to meet application-specific needs, available in both Soft RTL and Hard GDSII options. The key advantages of these cores include significant cost reduction, improved performance, and lower power consumption compared to traditional on-board FPGAs. One of the main features of Menta's eFPGA is its architecture, which conserves board space and drastically reduces power usage, as much as 50% less than comparable FPGA-based solutions. Integration directly on-chip reduces I/O latency and overcomes the limitations of traditional chip-to-chip communication interfaces. Additionally, Menta's eFPGA supports a broad range of technology nodes, from 350nm to less than 5nm, offering unparalleled silicon process portability. Menta's eFPGA architecture is easy to integrate, verified at various stages including formal verification and system simulation. It features trusted controls over bitstream loading and offers customization options for logic blocks, DSP arithmetic functions, and power-saving features. The standard-cell designed eFPGAs cater to unique application needs while being platform adaptive, ensuring broad compatibility and design flexibility.
ADICSYS Soft eFPGA provides a flexible and scalable embedded FPGA solution for ASICs and SoCs, ensuring seamless integration with standard RTL design flows. This synthesizable IP supports a rapid design cycle, enabling users to implement custom logic configurations post-production. The eFPGA is particularly beneficial in applications requiring adaptability and programmability, such as prototyping, design validation, and custom processing solutions. With its technology-independent architecture, it offers an excellent balance of power, performance, and area (PPA), suited for diverse fields like aerospace and telecommunications.
TUNGA is an innovative multi-core RISC-V SoC designed to advance high-performance computing and AI workflows using posit arithmetic. This SoC is equipped with multiple CRISP-cores, enabling efficient real-number computation with the integration of posit numerical representations. The TUNGA system exploits the power of the posit data type, known for offering enhanced computational precision and reduced bit-utilization compared to traditional formats. A standout feature of TUNGA is its fixed-point accumulator structure, QUIRE, which ensures exact calculation of dot products for vector lengths extending to approximately 2 billion elements. This precision makes it highly suitable for tasks in cryptography, AI, and data-intensive computations that require high accuracy. In addition, TUNGA leverages a pool of FPGA gates designed for hardware reconfiguration, facilitating the acceleration of processes such as data center services by optimizing task execution paths and supporting non-standard data types. TUNGA is fully programmable and supports various arithmetic operations for specialized computational needs, particularly within high-demand sectors like AI and machine learning, where processing speed and accuracy are critical. By integrating programmability through FPGA gates, users can tailor the SoC for specific workloads, thereby allowing Calligo's TUNGA to stand out as an adaptable element of next-generation cloud and edge computing solutions.
The Metis AIPU M.2 Accelerator Module by Axelera AI is a cutting-edge AI acceleration tool designed for edge applications. Its compact form factor, combined with powerful AI processing technology, enables real-time data processing and analysis. Equipped with 512MB of dedicated LPDDR4x memory, this module is capable of handling multiple data streams simultaneously. Its breakthrough digital in-memory compute architecture facilitates remarkable energy efficiency, consuming far less power than traditional GPUs while maintaining top-notch performance standards. This module is ideal for applications requiring high-speed computation, such as computer vision tasks involving multi-channel video analytics and quality inspections, thereby enhancing operational efficiency and reducing latency in decision-making processes. Whether deployed in retail, security, or industrial settings, the Metis AIPU M.2 Accelerator Module provides users with significant performance gains at a lower cost, facilitating seamless integration into existing systems. With a practical design for next-generation form factor M.2 sockets, this accelerator module opens the way for innovative AI-enabled solutions in diverse contexts, promising scalability and adaptability to future technological advancements.
The RAIV is a flexible and high-performing General Purpose GPU (GPGPU), fundamental for industries experiencing rapid transformation due to the fourth industrial revolution—autonomous vehicles, IoT, and VR/AR sectors. Built with a SIMT (Single Instruction Multiple Threads) architecture, the RAIV enhances AI workloads with high-speed processing capabilities while maintaining a low-cost construct. This semiconductor IP supports diverse machine learning and neural network applications, optimizing high-speed calculations across multiple threads. Its high scalability allows tailored configurations in core units, effectively balancing performance with power efficiency dependent on application needs. The RAIV is equipped to handle 3D graphics processing and AI integration for edge computing devices, reinforcing its place in advanced technological development. Additionally, the RAIV's support for OpenCL offers compatibility across various heterogeneous computing platforms, facilitating versatile system configurations. Its optimal performance in AI tasks is further extended for use in metaverse applications, presenting a comprehensive solution that unifies graphics acceleration with AI-enhanced computational operations.
The General Purpose Accelerator, known as Aptos, from Ascenium is a state-of-the-art innovation designed to redefine computing efficiency. Unlike traditional CPUs, Aptos is an integrated solution that enhances performance across all generic software applications without requiring modifications to the code. This technology utilizes a unique compiler-driven approach and simplifies CPU architecture, making it adept at executing a wide range of computational tasks with significant energy efficiency. At the heart of the Aptos design is the capability to handle tasks typically managed by out-of-order RISC CPUs, yet it does so with a streamlined and parallel approach, allowing data centers to move past current performance barriers. The architecture is aligned with the LLVM compiler, ensuring that it remains source-code compatible with numerous programming languages, an advantage when future-proofing investments in software infrastructure. The efficiency gains from Aptos are notably due to its ability to handle standard high-level language software in a more efficient manner, achieving nearly four times the efficiency compared to existing state-of-the-art CPUs. This is instrumental in reducing the energy footprint of data centers globally, aligning with broader sustainability goals by cutting carbon emissions and operational costs. Moreover, this makes the technology extremely appealing to organizations seeking tangible ROI through energy savings and performance enhancements.
The P8700 Series stands at the forefront of processing technology, emphasizing RISC-V architecture to target rapidly growing fields like automotive and autonomous vehicle applications. Implementing a 4-wide out-of-order execution with dual simultaneous multi-threading, the P8700 delivers superior performance due to its ability to run up to eight cores per cluster. This significantly enhances automotive system capabilities, addressing the ASIL-B safety standard with an emphasis on reliability and precise data control. Designed to integrate seamlessly with heterogeneous system components, the P8700 Series features an architecture conducive to real-time processing efficiency and system responsiveness. This is critical for maintaining operational integrity in safety-intensive environments such as advanced driver-assistance systems (ADAS) and autonomous functionality. It uniquely provides developers with the flexibility to configure its interconnect and cache coherence, facilitating a more tailored system design approach. These processors are built to reduce complexity and enhance computing density, ensuring robust performance across multiple workloads. Their architecture supports seamless communication with co-processors and specialized accelerators, optimally handling AI stack software, which can significantly boost AI workload efficiency by up to 30%. Designed for automotive-grade reliability, these processors also adapt to the specific demands of cloud data centers, enabling high performance while respecting the energy and capacity limitations inherent in these environments.
The Processor and Microcontroller Cores offered by So-Logic include a diverse range of popular microprocessor and microcontroller components, designed to meet the needs of modern electronic applications. These cores provide the essential computational capabilities required across various industries and are engineered for optimal performance in embedded systems. So-Logic's portfolio includes cores for widely used microprocessors and microcontrollers, ensuring that developers have the tools they need to build efficient and reliable computing systems. These cores simplify the development process, offering compatibility with a range of development environments and tools. With complete verification and a full suite of supportive resources, the cores facilitate straightforward integration into FPGA platforms. They also come with detailed design notes, comprehensive datasheets, and sample applications that aid in the ease of system development and deployment. Extensive technical support ensures that developers can navigate any challenges that arise during their project implementation, making these Processor and Microcontroller Cores a valuable asset in the creation of advanced electronic systems.
Boasting a robust 64-bit architecture, the UX Class processor is adept at handling sophisticated applications such as data center operations and networking solutions. This processor includes an MMU, providing advanced memory management capabilities which are crucial for high-end computing environments. The UX Class supports a wide array of RISC-V extensions, offering developers the capability to configure the processor with specific features that enhance performance and security features. This allows it to be highly adaptable to a variety of demanding applications. Additionally, this processor is designed with scalability and robustness in mind, paving the way for improved computing solutions in both enterprise and consumer sectors. Its extensive ecosystem includes toolchains, development kits, and robust security protocols, promoting innovation and rapid deployment across versatile uses.
iCEVision is a development board enabling quick evaluation and rapid prototyping of key connectivity features for the iCE40 UltraPlus FPGA. It supports a range of camera interfaces such as ArduCam CSI and PMOD, facilitating broad compatibility and ease of use. By exposing I/Os, designers can seamlessly implement and test their custom designs. The board features an iCE40 UltraPlus device in an SG48 package, coupled with multiple user LED indicators for RGB LED applications, making it suitable for prototyping user functions. Accompanied by 8Mb of SPI programmable flash and 1Mb of SRAM, the board supports flexible programming and storage capabilities, allowing for complex design implementations. Connectivity is further enhanced by the inclusion of a 20MHz Pmod connector and multiple ArduCam connectors, allowing for expanded interfacing options. The board comes pre-loaded with an RGB demo application and bootloader for straightforward programming via a USB cable, ensuring user convenience and readiness for development.
UltraRISC Technology's UR-E Processor Core is engineered for high-efficiency computation, especially suited for edge computing scenarios. It harnesses RISC-V architecture's advantages, ensuring a high degree of efficiency for power-sensitive applications. This core focuses on delivering optimum performance across different application domains, accommodating specific computational requirements with its customizable configuration. Offering compatibility with the RISC-V instruction set, the UR-E core can be tailored to specific needs, thus optimizing the processing capability for edge devices. It's designed to support essential processor core resources and SoC-level IP, thereby enabling robust systems that require efficient processing power. The UR-E core exemplifies UltraRISC's dedication to delivering versatile, high-performance computing solutions.
The Azurite Core-hub is crafted to offer a highly efficient RISC-V implementation, specifically aimed at minimizing both area and power consumption. This core-hub is ideally suited for embedded applications, where space and power efficiency are paramount. It demonstrates InCore's commitment to high-efficiency solutions that do not compromise on performance, making it an excellent choice for systems requiring compact and power-conservative designs. This particular Core-hub is characterized by its proficiency in integrating standard RISC-V UnCore components such as interrupt controllers and debugging tools, ensuring broad functionality within a streamlined architecture. Designed with a focus on sustaining excellent performance with reduced resources, the Azurite Core-hub stands as a benchmark for RISC-V cores capable of delivering top-notch performance while conserving energy and space. Azurite's versatility is a key feature, allowing it to be a foundational component in systems that need efficient computation in controlled environments. Its ability to seamlessly integrate into broader systems makes it a preferred choice for industries that value robust yet compact solutions.
The GenAI v1 is a cutting-edge hardware core developed by RaiderChip specifically engineered to meet the rigorous demands of generative AI workloads, often considered the most challenging. This IP core excels in optimizing efficiency for AI inference, breaking through traditional limitations by improving memory utilization and processing speed. Designed for deployment across a wide range of FPGA devices, particularly the AMD Versal series, it offers impressive speed in AI processing while maintaining low power consumption. The GenAI v1 has been proven effective in various cloud environments, notably on AWS F1 instances, where it demonstrates superior capabilities running complex LLM models like Meta's Llama series. Its architecture, which incorporates advanced parallel processing and optimized memory bandwidth utilization, promises enhanced performance metrics, ensuring it outpaces competitors significantly.
Eliyan’s NuLink Die-to-Die (D2D) PHY technology is designed to revolutionize the interconnection of chiplets using industry-standard packaging techniques. This technology offers low power consumption while maintaining high-performance metrics, seamlessly integrating into both standard and advanced packaging options. Eliyan's D2D IP allows for significant flexibility in application design and reduces the dependency on complex silicon interposer technologies. By using standard organic/laminate packages, the NuLink technology enhances system-level design optimizations, cost savings, and thermal performance. Support for numerous industry standards, including UCIe and BoW, ensures a versatile application in a wide array of semiconductor designs. The tailored PHY IP cores facilitate the incorporation of high-bandwidth interconnected systems within ASICs without the necessity of proprietary packaging methods. With up to 64 data lanes and bump map layouts adaptable to specific protocols, the NuLink D2D PHY exemplifies adaptable technology suitable for various semiconductor applications. This unique approach allows for greater design flexibility, mixing and matching chiplets with different dimensions, which is particularly beneficial in applications involving high bandwidth and low latency requirements. The ability of the NuLink D2D technology to deliver interposer-like bandwidth and power without high-cost advanced packaging makes it a remarkable solution in cutting-edge chip design.
The Altera Agilex 7 F-Series SoC is a versatile module that blends the strengths of Intel's Agilex FPGAs with an integrated system-on-chip (SoC). Built on Intel's 10nm SuperFin process technology, this FPGA is optimized for a variety of applications across multiple sectors, including bioscience, quantum computing, and electronic warfare. It features advanced high-performance capabilities, enabling system designers to implement complex functions with efficiency. The system-on-module (SoM) configuration is equipped with heat management components like active heatsinks and fans, making it ideal for embedded applications. The integration of various processing elements within a single silicon platform enhances the module's efficiency, offering reduced power consumption and improved performance. By providing pre-validated and tested modules, the Agilex 7 F-Series SoC facilitates ease of use and accelerates time-to-market for developers. This module is complemented by compatible carrier boards, which expand its utility in diverse applications while allowing seamless integration for complex embedded designs.
The Altera Stratix 10 SoC is a powerful module utilizing Intel's Stratix FPGA technology to achieve remarkable levels of data processing and bandwidth handling. Its design incorporates high-speed transceivers and extensive logic capabilities, suited for applications in data centers and communications. The embedded system-on-chip (SoC) form factor ensures efficient data management and processing within compact spaces. Supporting advanced connectivity options, including PCI Express and Ethernet, this module paves the way for rapid data transfer and enhanced computational tasks. With its focus on applications that demand high reliability and performance, the Stratix 10 SoC is a perfect fit for industries requiring robust embedded solutions.
The I8500 Series from MIPS exemplifies a strategic advancement in processing capabilities, leveraging the RISC-V architecture to address modern computational challenges. It features a triple-issue, in-order execution pathway and up to 4-way simultaneous multi-threading, making it ideally suited for both embedded and high-demand automotive systems that require enhanced computational responsiveness. Built with scalability in mind, the I8500 Series supports up to eight cores per cluster, promoting improved computational throughput for complex, parallelized tasks. This capability allows it to efficiently handle advanced automotive applications requiring strict compliance with ASIL-B standards, ensuring safety and reliability. Its design incorporates coherent last-level cache architecture supporting data coherence across diverse processor environments, essential for high fidelity system operations. Designed with a focus on customization, the I8500 provides a platform for RISC-V compliant core and peripheral development, making it adaptable to various market needs, from automotive control systems to next-generation data centers. Incorporating MIPS' unique innovation of flexibility, the I8500 allows for seamless integration with custom accelerators, providing an opened path to future technological adaptability and robustness in multi-core processor environments.
The NoISA processor is a revolutionary design aimed at mitigating the limitations of traditional instruction set architectures. Typical processors use a fixed ALU, register file, and hardware controller, dividing operations into multiple instructions. In contrast, the NoISA processor capitalizes on the Hotstate machine's capabilities, employing a runtime-loadable, microcoded algorithmic state machine that mimics the hardware controller's functions across diverse architectures. Particularly useful when traditional softcore CPUs are inefficient, the NoISA processor is energy-efficient and highly adaptable, ideal for IoT applications where power conservation is paramount. The NoISA processor shines in environments where quick and compact controller deployments are required. It excels in configuring systolic arrays and altering FPGA functionalities without modifying the physical setup. Its flexibility allows for powerful microcode reloading, offering a versatile alternative to conventional ISAs. As a result, users benefit from maximized performance potential, addressing the constraints imposed by fixed instruction sets. Overall, the NoISA processor empowers systems with enhanced speed and flexibility, making it an optimal choice for various applications demanding dynamic scalability and reduced energy consumption.
The AMD Zynq Ultrascale+ MPSoC module offers a merger of multifaceted processing power with field-programmable capabilities, specially targeted towards intricate and defense-critical applications. It brings together the best of ARM computing and FPGA scalability, making it ideal for markets such as radio communication and electronic surveillance. The module's architecture maximizes efficiency and adaptability, highlighting its strengths in handling complex algorithms and tasks in real-time. It is particularly valued for its versatile application in precision-demanding sectors, providing unmatched control and implementation versatility.
The Calcite Core-hub strikes a harmonious balance between area, power consumption, and performance, making it suitable for a range of applications including those requiring full-featured Linux OS support. It caters to embedded and industrial segments, emphasizing InCore's drive toward delivering flexible, high-performance RISC-V solutions that can adapt to various operational needs. Designed to handle diverse computational workloads, the Calcite Core-hub performs adeptly across both embedded environments and larger industrial applications. It supports an extensive array of features, bolstered by its compatibility with full-function operating systems. This adaptability extends its usability across different industry verticals, providing an edge where robust processing capability married with power efficiency is critical. Leveraging innovative design methodologies, this core-hub includes comprehensive interconnect fabrics ensuring seamless communication across system components. By integrating both hardware and software efficiencies, the Calcite Core-hub is well-positioned to meet the demands of industries that require sophisticated yet energy-conscious solutions.
The GateMate FPGA is a powerful and versatile semiconductor solution designed to bring cost-effective solutions across numerous industries. Manufactured using a 28nm process in Europe, it ensures a robust supply chain and complies with high-quality standards. Featuring comprehensive multi-node support, GateMate is perfect for low- to mid-range applications, offering exceptional power efficiency and versatility. The architecture of GateMate combines CPE programmable elements with an innovative routing engine, allowing it to perform complex computation tasks efficiently. It offers 20,480 logical elements, ideal for applications requiring streamlined multiprocessing capabilities. These elements can be configured as 8-input LUT trees, supporting both combinatorial and sequential logic functions. The device can handle flexible power management, with low power, economy, and speed modes available. Engineered to meet various application requirements, GateMate provides SerDes interfaces, multiple clock configurations, and GPIO configurations for both single-ended and differential signals. It is supported by the Yosys framework for design synthesis and integrates a static timing analysis tool for designing critical paths. Compatible with free Cologne Chip software for configuration, it can perform real-time updates to adapt to dynamic consumer needs.
Designed for AI-on-chips, the ONNC Compiler is a comprehensive bundle of C++ libraries and tools tailored to enhance compiler development for deep learning accelerators. It efficiently transforms neural networks into machine instructions suitable for diverse SoC architectures, from single core systems to more complex layouts with multi-level memory hierarchies. The compiler allows seamless connectivity to leading deep learning frameworks such as PyTorch and TensorFlow. It enables the scaling of deep learning tasks across heterogeneous multicore AI SoCs by utilizing both single backend and multiple backend modes to optimize computing resources. Additionally, it supports intricate features like multiple view address maps, ensuring effective memory allocation and data movement across fragmented memory spaces. Known for performance optimization, the ONNC Compiler employs hardware/software co-optimization techniques to reduce data movement overhead, thereby improving system throughput and efficiency.
Tachyum’s Prodigy FPGA-Based Emulator offers a sophisticated platform for developers and system architects aiming to evaluate and optimize performance metrics of upcoming products. This emulator stands as a crucial step within the development lifecycle, providing hardware emulation through a comprehensive system of interconnected FPGA and IO boards designed to replicate full processor capabilities. The design encompasses multiple FPGAs on a single board, each capable of emulating complete processor cores including vector and matrix operations. This setup is paramount for conducting accurate and reliable product evaluations, software debugging, and ensuring compatibility with anticipated operational environments. Customers and partners have the ability to leverage Tachyum’s FPGA-based emulation system for a wide range of scenarios, from performance testing to advanced software development. The emulator supports an extensive list of applications and configurations, allowing developers to closely mirror potential real-world use cases in a secure, controlled setting.
Ceva-XC16 stands out as one of the most powerful baseband processors available, designed to meet the demands of the next-generation wireless infrastructure and mobile devices. This DSP is built on the revolutionary Gen4 multi-thread architecture by Ceva, which enhances the processor's speed and efficiency. It is well-suited for use in various wireless communication devices, offering a balanced mix of performance, flexibility, and energy efficiency.
The XC4500 is Ceva's versatile communication processor, engineered to handle a variety of wireless communication tasks with high efficiency. It is part of a series of DSPs known for their powerful vector processing capabilities, enabling developers to build agile and resource-efficient systems. The processor supports a range of complex signal processing tasks, making it an ideal choice for applications in both telecommunications and IoT devices.
aiWare is aiMotive's trailblazing hardware solution for automotive AI, providing industry-leading neural network acceleration tailored to meet the challenges of next-generation automotive applications. The aiWare architecture achieves remarkable efficiency and scalability, supporting implementations from edge processing to high-performance centralized systems, and delivers up to 256 effective TOPS per core. Consistent with automotive-grade standards, aiWare's hardware has received ISO 26262 ASIL B certification, ensuring safety and reliability in automotive environments. Its deterministic architecture minimizes external memory traffic, optimizing power consumption and system performance. aiWare's embedded capabilities extend across a wide range of neural network models, including CNNs, LSTMs, RNNs, and Transformer Networks, making it a versatile core for varied AI workloads. Distinctive features like aiWare Studio offer a sophisticated SDK for NN optimization, empowering designers with greater flexibility in neural network implementations. The platform encourages adaptability through its offline performance estimation, allowing 90% of workload optimizations to occur without immediate hardware access. aiWare thus stands out as an invaluable asset for achieving efficient, rapid AI deployments in the automotive sector.
The GenAI v1-Q represents an enhancement over the basic GenAI v1 core, with added support for quantization capabilities, specifically 4-bit and 5-bit quantization. This significantly reduces memory requirements, potentially by as much as 75%, facilitating the execution of large language models within smaller, more cost-effective systems without sacrificing speed or accuracy. The reduced memory usage translates to lower overall costs and diminished energy consumption while maintaining the integrity and intelligence of the models. Designed for seamless integration into various devices, the GenAI v1-Q also ensures compatibility with diverse memory technologies, making it a versatile choice for applications demanding efficient AI performance.
The SEMIFIVE SoC Platform offers tailored solutions for the rapid design and deployment of system-on-chip products, focusing on cost-effectiveness, reduced risk, and quicker market introduction. By utilizing domain-specific architectures and silicon-proven IPs, the platform lowers development costs significantly, thanks to its optimized infrastructure and methodology, outperforming industry averages by up to 50%. The SoC Platform is designed to accommodate various needs, including AI Inference, AIoT, and HPC applications. This is achieved through the integration of pre-configured and verified IP pools and the ability to utilize high-efficiency models. These models support extensive component reusability and facilitate faster prototyping and design verification cycles, essential for staying ahead in rapidly evolving markets. Customers benefit from lower prototyping costs via non-recurring engineering savings, substantial reduction in design and verification timelines, and an organization of pre-selected, configured, and implemented IPs that are ready for rapid deployment. By managing the entire silicon design and manufacturing process from start to finish, SEMIFIVE ensures innovative products are brought to market swiftly and effectively.
The Tyr Superchip represents a scalable, unified processing solution engineered for cutting-edge applications in edge AI, autonomous driving, and decentralized AIoT systems. Capable of delivering exceptional compute power, the Tyr Superchip is designed to support high-level AI tasks and DSP operations with remarkable energy efficiency. This chip stands out due to its ability to manage complex processing loads with lower energy demands, optimizing system performance and reducing carbon footprint, which is crucial for modern sustainable applications. <br><br> The architecture of the Tyr Superchip allows seamless integration into existing systems and new designs, offering up to 1+ petaFLOPS of processing power with an implementation efficiency of 70-80%. It is programmable using high-level languages, making it adaptable to a wide array of algorithms and applications without requiring extensive redevelopment efforts. <br><br> By focusing on minimal latency and energy consumption, the Tyr Superchip is particularly suited for high-demand applications in autonomous vehicles and AI-driven IoT networks. Its ability to handle both AI and DSP effortlessly, in conjunction with its in-field programmability, positions it as a forefront solution for achieving highly autonomous operations.
The UR-A Processor Core by UltraRISC Technology is a state-of-the-art processor designed for high-performance computing needs, using the RISC-V architecture. It is ideal for desktop, AI, DPU, and cloud computing applications, delivering exceptional performance while maintaining power efficiency. This processor core is configurable and compatible with the RISC-V instruction set, providing a flexible solution tailored to meet the demands of target application domains. With a focus on performance, power, and area optimization, the UR-A core supports major processor core resources and SoC system-level IPs. The core leverages various low-power design technologies to enhance processor efficiency, making it suitable for applications requiring high computational capabilities. UltraRISC's UR-A core represents a robust solution for engineers and developers looking to implement cutting-edge technology in their projects.
Adaptive Remaining Useful Life Estimator (ARULE) is a sophisticated tool designed for predictive analytics in complex systems. It accurately estimates prognostic quantities such as Remaining Useful Life (RUL), State-of-Health (SoH), and Prognostic Horizon (PH) by processing condition-based feature data. This allows maintenance teams to preemptively schedule repairs, reducing the risk of operational failures. ARULE leverages advanced prediction methods linked to Extended Kalman Filtering, making it versatile across electrical, mechanical, and electro-mechanical systems. ARULE's intuitive graphical user interface (GUI) supports Condition-based Maintenance (CBM), Prognostic Health Management (PHM), and Integrated Vehicle Health Management (IVHM) applications. Users can easily upload and process condition-based data (CBD) to generate essential prognostics, which help in evidence-based system replacements. This approach streamlines maintenance, reduces costs, and promotes system reliability. This estimator is part of the broader Sentinel Suite solution from Ridgetop Group, which integrates seamlessly with other components like sensors and application software. ARULE's utility is wide-ranging, applicable in power supply systems, battery management, industrial automation, and more, making it a cornerstone of effective health management strategies.