All IPs > Platform Level IP > Multiprocessor / DSP
In the realm of semiconductor IP, the Multiprocessor and Digital Signal Processor (DSP) category plays a crucial role in enhancing the processing performance and efficiency of a vast array of modern electronic devices. Semiconductor IPs in this category are designed to support complex computational tasks, enabling sophisticated functionalities in consumer electronics, automotive systems, telecommunications, and more. With the growing need for high-performance processing in a compact and energy-efficient form, multiprocessor and DSP IPs have become integral to product development across industries.
The multiprocessor IPs are tailored to provide parallel processing capabilities, which significantly boost the computational power required for intensive applications. By employing multiple processing cores, these IPs allow for the concurrent execution of multiple tasks, leading to faster data processing and improved system performance. This is especially vital in applications such as gaming consoles, smartphones, and advanced driver-assistance systems (ADAS) in vehicles, where seamless and rapid processing is essential.
Digital Signal Processors are specialized semiconductor IPs used to perform mathematical operations on signals, allowing for efficient processing of audio, video, and other types of data streams. DSPs are indispensable in applications where real-time data processing is critical, such as noise cancellation in audio devices, image processing in cameras, and signal modulation in communication systems. By providing dedicated hardware structures optimized for these tasks, DSP IPs deliver superior performance and lower power consumption compared to general-purpose processors.
Products in the multiprocessor and DSP semiconductor IP category range from core subsystems and configurable processors to specialized accelerators and integrated solutions that combine processing elements with other essential components. These IPs are designed to help developers create cutting-edge solutions that meet the demands of today’s technology-driven world, offering flexibility and scalability to adapt to different performance and power requirements. As technology evolves, the importance of multiprocessor and DSP IPs will continue to grow, driving innovation and efficiency across various sectors.
Continuing the evolution of AI at the edge, the 2nd Generation Akida provides enhanced capabilities for modern applications. This upgrade implements 8-bit quantization for increased precision and introduces support for Vision Transformers and temporal event-based neural networks. The platform handles advanced cognitive tasks seamlessly with heightened accuracy and significantly reduced energy consumption. Designed for high-performance AI tasks, it supports complex network models and utilizes skip connections to enhance speed and efficiency.
The NMP-750 serves as a high-performance accelerator IP for edge computing solutions across various sectors, including automotive, smart cities, and telecommunications. It supports sophisticated applications such as mobility control, factory automation, and energy management, making it a versatile choice for complex computational tasks. With a high throughput of up to 16 TOPS and a memory capacity scaling up to 16 MB, this IP ensures substantial computing power for edge devices. It is configured with a RISC-V or Arm Cortex-R/A 32-bit CPU and incorporates multiple AXI4 interfaces, optimizing data exchanges between Host, CPU, and peripherals. Optimized for edge environments, the NMP-750 enhances spectral efficiency and supports multi-camera stream processing, paving the way for innovation in smart infrastructure management. Its scalable architecture and energy-efficient design make it an ideal component for next-generation smart technologies.
The NMP-750 serves as a high-performance accelerator IP for edge computing solutions across various sectors, including automotive, smart cities, and telecommunications. It supports sophisticated applications such as mobility control, factory automation, and energy management, making it a versatile choice for complex computational tasks. With a high throughput of up to 16 TOPS and a memory capacity scaling up to 16 MB, this IP ensures substantial computing power for edge devices. It is configured with a RISC-V or Arm Cortex-R/A 32-bit CPU and incorporates multiple AXI4 interfaces, optimizing data exchanges between Host, CPU, and peripherals. Optimized for edge environments, the NMP-750 enhances spectral efficiency and supports multi-camera stream processing, paving the way for innovation in smart infrastructure management. Its scalable architecture and energy-efficient design make it an ideal component for next-generation smart technologies.
The NMP-350 is designed to offer exceptional efficiency in AI processing, specifically targeting endpoint accelerations. This IP is well-suited for markets that require minimal power consumption and cost-effectiveness, such as automotive, AIoT/Sensors, Industry 4.0, smart appliances, and wearables. It enables a wide variety of applications, including driver authentication, digital mirrors, machine automation, and health monitoring. Technically, it delivers up to 1 TOPS and supports up to 1 MB local memory. The architecture is based on the RISC-V or Arm Cortex-M 32-bit CPU, ensuring effective processing capabilities for diverse tasks. Communication is managed via three AXI4 interfaces, each 128 bits wide, to handle Host, CPU, and Data interactions efficiently. The NMP-350 provides a robust foundation for developing advanced AI applications at the edge. Designed for ultimate flexibility, it aids in predictive maintenance and personalization processes in smart environments. With its streamlined architecture, it provides unmatched performance for embedded solutions, enabling seamless integration into existing hardware ecosystems.
KPIT's engineering and design solutions focus on accelerating vehicle development through new-age design and simulation techniques. This approach enables cost-efficient transformation and adherence to sustainability standards, offering integrated electrification solutions and cutting-edge design methodologies. KPIT's solutions in vehicle engineering support electric and hybrid vehicle innovation with advanced CAD tools, virtual prototyping, and AI augmentation.
WAVE6 is a sophisticated multi-standard video codec designed to handle an array of video standards such as AV1, HEVC, AVC, and VP9. Capable of efficiently managing high-resolution video encoding and decoding processes, WAVE6 offers unmatched performance for applications demanding 4K and 8K resolutions. The technology incorporates a dual-core architecture that doubles operational efficiency and is crucial for high-throughput sectors like data centers and surveillance systems. Key features include support for color depth adaptations ranging from 8-bit to 10-bit and advanced power efficiency mechanisms. The WAVE6 codec is notable for incorporating features such as Chips&Media’s unique lossless frame buffer compression technology, CFrame™, to significantly minimize external memory bandwidth usage. With a streamlined architecture that simplifies video processing tasks, this codec supports multiple interface standards, enhancing your system's scalability and integration. High versatility makes WAVE6 a preferred choice for modern multimedia processing units, providing effective solutions for bandwidth challenges while maintaining superior image quality. WAVE6's efficient resource management and multi-instance capabilities make it a standout product in environments requiring low power consumption and high output precision. It facilitates color space conversion, bit-depth switching, and offers secondary interface options, tailoring it for a diverse range of implementation scenarios, from mobile technology to media broadcasting facilities.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores are designed to offer superior video compression capabilities, ensuring minimal latency with a remarkable sub-1ms delay for 1080p30. This licensable core is notable for its compliance with ITAR standards, making it adaptable for various strategic applications. It facilitates 1080p60 baseline support with a single compact core that's touted as the fastest and smallest in its class. These cores are customizable, allowing for tailored pixel depths and unique resolutions that can be modified based on the specific requirements of a project. Moreover, the flexibility of these cores extends to various encoding flavors, including H.264 Encoder, CODEC, and I-Frame Only Encoder, which further enhances their usage in a wide range of applications. A low-cost evaluation license is also available, making the cores accessible for diverse testing and development scenarios.
Cortus's High Performance RISC-V Processor represents the pinnacle of processing capability, designed for demanding applications that require high-speed computing and efficient task handling. It features the world’s fastest RISC-V 64-bit instruction set architecture, implemented in an Out-of-Order (OoO) execution core, supporting both single-core and multi-core configurations for unparalleled processing throughput. This processor is particularly suited for high-end computing tasks in environments ranging from desktop computing to artificial intelligence workloads. With integrated features such as a multi-socket cache coherent system and an on-chip vector plus AI accelerator, it delivers exceptional computation power, essential for tasks such as bioinformatics and complex machine learning models. Moreover, the processor includes coherent off-chip accelerators, such as CNN accelerators, enhancing its utility in AI-driven applications. The design flexibility extends its application to consumer electronics like laptops and supercomputers, positioning the High Performance RISC-V Processor as an integral part of next-gen technology solutions across multiple domains.
Aimed at performance-driven environments, the NMP-550 is an efficient accelerator IP optimized for diverse markets, including automotive, mobile, AR/VR, drones, and medical devices. This IP is crucial for applications such as driver monitoring, fleet management, image and video analytics, and compliance in security systems. The NMP-550 boasts a processing power of up to 6 TOPS and integrates up to 6 MB of local memory, empowering it to handle complex tasks with ease. It runs on a RISC-V or Arm Cortex-M/A 32-bit CPU and supports multiple high-speed interfaces, specifically three AXI4, 128-bit connections that manage Host, CPU, and Data traffic. This IP is engineered for environments demanding high performance with efficient power use, addressing modern technological challenges in real-time analytics and surveillance. The NMP-550 is adept at improving system intelligence, allowing for enhanced decision-making processes in connected devices.
The Automotive AI Inference SoC by Cortus is a cutting-edge chip designed to revolutionize image processing and artificial intelligence applications in advanced driver-assistance systems (ADAS). Leveraging RISC-V expertise, this SoC is engineered for low power and high performance, particularly suited to the rigorous demands of autonomous driving and smart city infrastructures. Built to support Level 2 to Level 4 autonomous driving standards, this AI Inference SoC features powerful processing capabilities, enabling complex image processing algorithms akin to those used in advanced visual recognition tasks. Designed for mid to high-end automotive markets, it offers adaptability and precision, key to enhancing the safety and efficiency of driver support systems. The chip's architecture allows it to handle a tremendous amount of data throughput, crucial for real-time decision-making required in dynamic automotive environments. With its advanced processing efficiency and low power consumption, the Automotive AI Inference SoC stands as a pivotal component in the evolution of intelligent transportation systems.
The PolarFire FPGA Family is designed to deliver cost-efficient and ultra-low power solutions across a spectrum of mid-range applications. It is ideal for a variety of markets that include industrial automation, communications, and automotive sectors. These FPGAs are equipped with transceivers that range from 250 Mbps to 12.7 Gbps, which enables flexibility in handling diverse data throughput requirements efficiently. With capacities ranging from 100K to 500K Logic Elements (LEs) and up to 33 Mbits of RAM, the PolarFire FPGAs provide the perfect balance of power efficiency and performance. These characteristics make them suitable for use in applications that demand strong computational power and data processing while maintaining energy consumption at minimal levels. Additionally, the PolarFire FPGA Family is known for integrating best-in-class security features, offering exceptional reliability which is crucial for critical applications. The architecture is built to facilitate easy incorporation into various infrastructure setups, enhancing scalability and adaptability for future technological advancements. This flexibility ensures that the PolarFire FPGAs remain at the forefront of the semiconductor industry, providing solutions that meet the evolving needs of customers worldwide.
The RISC-V Core-hub Generators by InCore Semiconductors provide an advanced level of customization for developing processor cores. These generators are tailored to support configuration at both the Instruction Set Architecture (ISA) and the microarchitecture levels, enabling designers to create cores that meet specific functional and performance needs. By allowing detailed customization, these generators support a wide range of applications, from simple embedded devices to complex industrial systems. The Core-hub Generators are designed to streamline the SoC development process by integrating optimized SoC fabrics and UnCore components such as programming interfaces, debugging tools, and interrupt controllers. This comprehensive integration facilitates efficient communication between different processing units and peripheral devices, thereby enhancing overall system performance. InCore's generators leverage the flexibility and scalability of RISC-V technology, promoting innovation and accelerating the deployment of custom silicon solutions. This makes them an ideal choice for designers looking to build cutting-edge SoCs with enhanced capabilities and reduced development times.
The Dynamic Neural Accelerator II Architecture (DNA-II) by EdgeCortix is a sophisticated neural network IP core structured for extensive parallelism and efficiency enhancement. Distinguished by its run-time reconfigurable interconnects between computing elements, DNA-II supports a broad spectrum of AI models, including both convolutional and transformer networks, making it suitable for diverse edge AI applications. With its scalable performance starting from 1K MACs, the DNA-II architecture integrates easily with many SoC and FPGA applications. This architecture provides a foundation for the SAKURA-II AI Accelerator, supporting up to 240 TOPS in processing capacity. The unique aspect of DNA-II is its utilization of advanced data path configurations to optimize processing parallelism and resource allocation, thereby minimizing on-chip memory bandwidth limitations. The DNA-II is particularly noted for its superior computational capabilities, ensuring that AI models operate with maximum efficiency and speed. Leveraging its patented run-time reconfigurable data paths, it significantly increases hardware performance metrics and energy efficiency. This capability not only enhances the compute power available for complex inference tasks but also reduces the power footprint, which is critical for edge-based deployments.
WAVE5 is a mature multi-standard video codec IP designed to meet the demands of high-performance multimedia processing. Supporting AV1, HEVC, AVC, and VP9 decoding, WAVE5 delivers exceptional speed and efficiency, making it suitable for various applications including data centers, surveillance, and set-top boxes. This codec achieves stunning high-resolution performance with 4K and 8K video streams, providing a comprehensive suite of virtualization and encoding tools that maximize resource utility. The WAVE5 architecture is optimized for both power and bandwidth efficiency, thanks to its dual-core setup and state-of-the-art clock gating techniques. It supports extensive pixel depth options and advanced features such as multi-instance support and frame buffer compression. This can considerably reduce latency while simultaneously optimizing image quality across diverse platforms. Applications that require reliable, high-speed video processing benefit greatly from WAVE5’s dependable multi-format compatibility and robust interface options. Equipped with extensive video formatting options and features, WAVE5 allows color format conversions, deep pixel manipulations, and effective data handling functionalities. These features create a seamless operation for developers aiming to integrate high-performing video codec solutions with broad compatibility across modern video standards.
The 3D Imaging Chip from Altek is a sophisticated piece of technology designed to enhance depth perception in imaging applications. This chip is deeply rooted in Altek's extensive expertise in 3D sensing technology, developed over several years to provide optimal solutions for various devices requiring mid to long-range detection capabilities. It's particularly effective in enhancing accuracy in depth recognition, crucial for applications such as autonomous vehicles and complex robotics. With its integration capabilities, the 3D Imaging Chip stands out by seamlessly combining hardware and software solutions, offering a comprehensive package from modules to complete chip solutions. This versatility allows the chip to be employed across various industries, wherever precision and depth detection are paramount. It facilitates improved human-machine interaction, making it ideal for sectors like virtual reality and advanced surveillance systems. Engineered to support sophisticated algorithms, the 3D Imaging Chip optimizes performance in real-time image processing. This makes it a pivotal sensor solution that addresses the growing demand for 3D imaging applications, providing clarity and reliability essential for next-generation technology.
The NPU by OPENEDGES, known as ENLIGHT, is a cutting-edge neural processing unit tailored for deep learning applications requiring high computational efficiency. It introduces an innovative approach by utilizing mixed-precision computation (4/8-bit), heavily optimizing processing power and reducing DRAM traffic through advanced scheduling and layer partitioning techniques. This NPU offers superior energy efficiency and compute density, making it significantly more effective than competing alternatives. It is highly customizable, accommodating varying core sizes to meet specific market demands, ensuring a broad application reach from AI and ML tasks to edge computing requirements. ENLIGHT enhances performance with its DNN-optimized vector engine and advanced algorithm supports, including convolution and non-linear activation functions. Its toolkit supports popular formats like ONNX and TFLite, simplifying integration and accelerating the development process for complex neural network models in high-performance environments.
The Talamo SDK is a powerful development toolkit engineered to advance the creation of sophisticated spiking neural network-based applications. It melds seamlessly with PyTorch, offering developers an accessible workflow for model building and deployment. This SDK extends the PyTorch ecosystem by providing the necessary infrastructure to construct, train, and implement spiking neural networks effectively. A distinguishing feature of Talamo SDK lies in its ability to map trained neural models onto the diverse computing layers inherent in the spiking neural processor hardware. This is complemented by an architecture simulator enabling fast validation, which accelerates the iterative design process by simulating hardware behavior and helping optimize power and performance metrics. Developers will appreciate the end-to-end application support within Talamo SDK, including the integration of standard neural network operations alongside spiking models, allowing for a comprehensive application pipeline. With ready-to-use models, even those without detailed SNN knowledge can develop powerful AI-driven applications swiftly, benefiting from high-level profiling and optimization tools.
The Tyr Superchip is engineered to facilitate high performance computing in AI and data processing domains, with a focus on scalability and power efficiency. Designed around a revolutionary multi-core architecture, it features fully programmable cores that are suitable for any AI or general-purpose algorithms, ensuring high flexibility and adaptability. This product is crucial for industries requiring cutting-edge processing capabilities without the overhead of traditional systems, thanks to its support for CUDA-free operations and efficient algorithm execution that minimizes energy consumption.
The ULYSS MCU range from Cortus is a powerful suite of automotive microcontrollers designed to address the complex demands of modern automotive applications. These MCUs are anchored by a highly optimized 32/64-bit RISC-V architecture, delivering impressive performance levels from 120MHz to 1.5GHz, making them suitable for a variety of automotive functions such as body control, safety systems, and infotainment. ULYSS MCUs are engineered to accommodate extensive application domains, providing reliability and efficiency within harsh automotive environments. They feature advanced processing capabilities and are designed to integrate seamlessly into various automotive systems, offering developers a versatile platform for building next-generation automotive solutions. The ULYSS MCU family stands out for its scalability and adaptability, enabling manufacturers to design robust automotive electronics tailored to specific needs while ensuring cost-effectiveness. With their support for a wide range of automotive networking and control applications, ULYSS MCUs are pivotal in the development of reliable, state-of-the-art automotive systems.
The NX Class of RISC-V CPU IP is crafted to serve the needs of applications such as storage, AR/VR, and AI with its potent 64-bit architecture. Its design focus lies in offering enhanced computing capabilities and data throughput, pivotal for tasks demanding high-efficiency processing. With features that support advanced data handling and computational tasks, the NX Class IP is well-suited for environments where large datasets and complex algorithms are at play. This makes it an excellent fit for AR/VR applications, where real-time data processing is paramount. The IP is complemented by an extensive development ecosystem, including SDKs and support for various RTOS/Linux environments. Its design ensures compatibility with state-of-the-art technologies, providing a reliable foundation for innovative industry solutions.
The 1000 Series by Akeana offers high-performance processing capabilities designed to tackle data-heavy computational tasks. With features aimed at enhancing throughput and power efficiency, these processors are suitable for environments that require robust processing power like AI on the edge, industrial automation, and automotive sensing. Supporting rich operating systems like Android and Linux, the 1000 Series is crafted to ensure superior performance with efficient power management, making it a prime choice for modern high-demand applications.
The SiFive Automotive E6-A processor is crafted to meet the burgeoning demands of the automotive sector, offering a suite of RISC-V safety processors that comply with ISO26262 standards. Featuring balanced performance and efficiency, the E6-A series supports automotive safety functions across ASIL B and D ratings. This processor is ideal for advanced driver-assistance systems (ADAS), in-vehicle infotainment, and automotive body control, emphasizing low power consumption and compact design, all while ensuring high reliability and system security.
The Altera Agilex 7 F-Series SoC offers unparalleled flexibility and high-performance capabilities, enabling the seamless implementation of complex algorithms into a single chip. Targeting sectors like bioscience and radar systems, this SoC optimizes system performance while minimizing power consumption. Its design includes a heatsink with an integrated fan for effective thermal management, ensuring reliable operation in demanding applications. The integration capabilities of the Agilex 7 F-Series make it a versatile choice for developers seeking efficient system solutions.
Built around the Intel Stratix 10 FPGA, the Altera Stratix 10 SoC delivers robust transceiver bandwidth ideal for applications requiring high-performance processing. Suitable for complex computing environments, such as analytic and video processing, this SoC ensures enhanced control and integration through its internal system-on-chip structure. The potent combination of FPGA architecture and integrated circuits makes it a prime choice for agile deployments across various high-demand sectors.
The Origami Programmer from Menta is a sophisticated software tool designed to facilitate the synthesis, placement, and routing of designs onto Menta’s eFPGA architecture. This robust programming software is optimized specifically for Menta's eFPGA, allowing users to tailor their RTL for optimal functionality and performance outcomes.\n\nSupporting multiple design formats such as IEEE VHDL, Verilog, and System-Verilog, the Origami Programmer is equipped with a user-friendly interface that supports aspects like manual floor planning and precise resource utilization summaries. This toolset also provides extensive ">static timing analysis and performance estimation capabilities, catering to the needs of both iterative design refinement and high-stakes application execution.\n\nBy making use of proprietary algorithms that are free from export-control and patent entanglements, Menta ensures that the Origami Programmer delivers an unparalleled synthesis experience. This ensures high accuracy in timing and I/O constraints adherence, ultimately leading to logic that is perfectly adapted to the targeted embedded FPGA architecture.
The SiFive Automotive suite provides optimized RISC-V processors tailored for automotive applications, ensuring not only performance but also adherence to industry safety standards like ISO26262 and ISO/SAE 21434. These processors cater to advanced automotive systems, offering scalability, low power consumption, and robust security measures. They're designed to handle the high demands of next-generation vehicles, covering everything from safety islands to central computing requirements while being flexible enough to adapt to emerging automotive challenges.
The SiFive Performance family is designed for superior compute density and performance efficiency, particularly for datacenter and AI workloads. The family includes 64-bit out-of-order cores ranging from 3 wide to 6 wide configurations, supported by dedicated vector engines for AI tasks. This design ensures a blend of energy efficiency and area optimization, making these cores ideal for handling complex, data-intensive tasks while maintaining a compact footprint.
The Yitian 710 Processor, a hallmark product of T-Head, is a high-performance Arm-based server chip. Developed by T-Head, it is designed with advanced architecture, featuring 128 Armv9 CPU cores and 2.75 GHz of frequency. The processor is engineered with cutting-edge 2.5D packaging, integrating 60 billion transistors. This makes it capable of exceptional computational tasks, catering to demands in AI reasoning, big data, and cloud computing applications.\n\nBeyond its core processing prowess, the Yitian 710 boasts a comprehensive I/O subsystem that includes 96 PCIe 5.0 lanes for high-speed data transfer, enhancing its utility for data-intensive applications. It supports up to eight DDR5 memory channels, delivering a bandwidth peak of 281 GB/s, thus ensuring fast and reliable performance for modern data centers.\n\nThis processor stands out for its ability to handle high throughput workloads efficiently, leading to superior performance in distributed computing environments. It supports scalable cloud service applications, making it ideal for complex computations and large datasets, which are fundamental to many modern enterprises.
The SAKURA-II AI Accelerator represents the pinnacle of EdgeCortix's innovation, offering cutting-edge efficiency in AI inferencing tasks particularly suited for generative AI applications. This high-performance accelerator is powered by the low-latency Dynamic Neural Architecture (DNA), handling multi-billion parameters with remarkable adequacy. Its adaptability allows it to transform inputs across various modalities such as vision, language, and audio. Particularly distinguished for its compactness and minimal power consumption, the SAKURA-II is engineered to deliver excellent results even in constrained physical environments. It supports vast model complexities with impressive DRAM bandwidth and is equipped for low-latency operations, ensuring fast real-time Batch=1 processing. Notably, its hardware capacity efficiently approximates activation functions, extending substantial support for structures like Llama 2, Stable Diffusion, and ViT. Critically, the SAKURA-II is designed for flexibility, offering robust processing of vision and generative AI workloads in an 8W power envelope. It features a highly-operative memory infrastructure that enhances its performance with sophisticated DRAM bandwidths and ample memory capacity for handling complex data streams and facilitating superior AI compute utility. Its intelligent design aligns with the current move towards sophisticated, low-power AI applications.
The AI Inference Platform by SEMIFIVE is designed to facilitate cutting-edge AI computations within custom SoC designs. This platform is particularly structured to meet the high-performance needs of AI-driven applications, powered by a quad-core SiFive U74 RISC-V CPU, supported by a high-speed LPDDR4x memory interface. It integrates PCIe Gen4 for enhanced data transfer capabilities and comes equipped with dedicated vision processing and DC acceleration functionalities. This platform offers a robust infrastructure for developing AI applications, with a significant emphasis on delivering rapid deployment and efficient operations. It makes AI integration seamless through pre-verified components and a flexible architecture, reducing the overall time from concept to deployment. The platform promises a configuration that minimizes risks while maintaining the potential for scalability and future enhancements. SEMIFIVE’s AI Inference Platform is ideally suited for applications like big data analytics and high-performance AI workloads. By leveraging a finely tuned ecosystem and a constellation of pre-integrated IPs, the platform not only speeds up the development process but also ensures reliability and robustness in delivering AI-based solutions.
The AIoT Platform engineered by SEMIFIVE is meticulously crafted to cater to the burgeoning demands of AI-powered IoT applications. It is built on the efficient and versatile SiFive dual-core U54 RISC-V architecture, paired with the LPDDR4x memory interface to ensure robust data handling and processing. Complemented by a comprehensive range of connectivity options, including USB3.0 and MIPI CSI, this platform is primed for edge compute applications. Specifically designed for smart home, robotics, and other AIoT applications, the platform aims to fuse intelligence with connectivity. It empowers developers by offering ready-to-use components that speed up development cycles, thereby facilitating quicker market entry strategies. These features are combined with an ideal balance of power consumption and performance to accommodate the typical requirements of IoT devices. The platform's flexibility in integrating various sensors and peripherals, alongside its strong processing capabilities, positions it perfectly for tasks that require real-time processing and responsiveness, working seamlessly in networked environments to provide intelligent, connected experiences.
eSi-ADAS is a comprehensive suite of radar processing IP aimed at enhancing the performance of Advanced Driver Assistance Systems (ADAS). Engineered to work efficiently in automotive and UAV applications, this radar accelerator IP offers significant improvements in situational awareness. Its functionality extends to a wide array of radar systems, integrating smoothly with automotive Tier 1 and 2 suppliers.\n\nThe suite excels with its diverse range of hardware accelerator functions, from FFT engines designed for radar systems to configurable Constant False Alarm Rate (CFAR) engines and a robust Kalman Filter engine. These components improve tracking capabilities and integrate smoothly into existing systems, offering recalibration flexibility and high precision across multiple radar applications.\n\nMoreover, eSi-ADAS offers superior object tracking abilities, allowing for real-time tracking of hundreds of objects while managing radar target processing effortlessly. Its compact design supports low power consumption, which optimizes processing loads on main ADAS ECUs, CPUs, or DSPs. The IP meets the stringent demands of modern ADAS by incorporating advanced processing techniques such as 3D Fast Fourier Transforms and Kalman Filtering, facilitating real-time data processing for enhanced object tracking.
The hypr_risc Radar DSP Accelerator distinguishes itself as a high-efficiency signal processor tailored for advanced radar applications. Built around a custom RISC-V core, hypr_risc achieves optimal processing speeds necessary for time-sensitive applications like advanced driver-assistance systems (ADAS). This DSP accelerator serves as a crucial interface between radar front-end modules and data management systems, ensuring high-performance processing with minimal latency. hypr_risc's adaptability allows it to integrate seamlessly with various RF front-end manufacturers, thanks to its highly configurable architecture. This flexibility extends to the core level, offering customization in power consumption, core sizing, cache configurations, and more. As a result, hypr_risc provides a cost-effective, scalable solution for complex radar processing tasks. The technology behind hypr_risc is particularly beneficial for imaging radar systems requiring precise object range and motion tracking. By leveraging open-source RISC-V technology, it lowers development costs and accelerates time-to-market, positioning itself as a valuable asset in the rapidly evolving radar technology landscape.
TUNGA is an innovative multi-core RISC-V SoC designed to advance high-performance computing and AI workflows using posit arithmetic. This SoC is equipped with multiple CRISP-cores, enabling efficient real-number computation with the integration of posit numerical representations. The TUNGA system exploits the power of the posit data type, known for offering enhanced computational precision and reduced bit-utilization compared to traditional formats. A standout feature of TUNGA is its fixed-point accumulator structure, QUIRE, which ensures exact calculation of dot products for vector lengths extending to approximately 2 billion elements. This precision makes it highly suitable for tasks in cryptography, AI, and data-intensive computations that require high accuracy. In addition, TUNGA leverages a pool of FPGA gates designed for hardware reconfiguration, facilitating the acceleration of processes such as data center services by optimizing task execution paths and supporting non-standard data types. TUNGA is fully programmable and supports various arithmetic operations for specialized computational needs, particularly within high-demand sectors like AI and machine learning, where processing speed and accuracy are critical. By integrating programmability through FPGA gates, users can tailor the SoC for specific workloads, thereby allowing Calligo's TUNGA to stand out as an adaptable element of next-generation cloud and edge computing solutions.
The Vega eFPGA from Rapid Silicon represents an innovative leap in providing customizable FPGA capabilities to System-on-Chip (SoC) designs. This eFPGA is designed to deliver flexibility and efficiency, allowing a seamless integration that enhances performance without raising costs. By embedding programmability directly into SoCs, Vega eFPGA facilitates diverse and adaptable computing needs. Structured with three configurable tile types – CLB, BRAM, and DSP – the Vega eFPGA is engineered for optimal performance. The CLB comprises eight 6-input lookup tables (LUTs), each offering dual independent outputs. It includes features like fast adders with carry chains and programmable registers, ensuring computational versatility. The BRAM component supports 36Kb dual-port memory, adaptable as 18Kb split memory configurations. The DSP tile incorporates an 18×20 multiplier with a 64-bit accumulator, supporting complex mathematical processing. Rapid Silicon's Vega eFPGA is optimized for scalability, providing flexibility in tile configurations to meet varied application requirements. It ensures ample compatibility with existing systems through seamless SoC integration, proprietary Raptor EDA tools, and robust IP libraries. These capabilities enable Vega to offer bespoke solutions tailored to specific end-user needs.
The ZIA DV700 Series by DMP is an advanced neural inference processor line, known for its high precision and robustness in executing deep learning workloads. These processors offer floating-point operations at FP16 precision, enabling efficient inference execution without requiring re-training, easing the incorporation of AI models trained on conventional servers into edge devices. The DV700 series is crafted to handle a diverse array of deep neural network models, excelling particularly in applications like object detection, semantic segmentation, and spatial recognition. The architecture's unique configuration supports uninterrupted learning and inferencing essential for high-reliability AI applications such as autonomous driving and robotics where precision is paramount. Development is streamlined through comprehensive SDKs which align with standard AI frameworks, ensuring ease of adaptation for developers migrating models from environments like TensorFlow or Keras to the DV700 platform. This has established the series as an optimal choice for developers looking to implement sophisticated AI functionalities in real time.
The Spiking Neural Processor T1 is a groundbreaking ultra-low power microcontroller designed for sensing applications that require continuous monitoring and rapid data processing while maintaining minimal energy consumption. At its core, it fuses an event-driven spiking neural network engine with a RISC-V processor, creating a hybrid chip that effectively processes sensor inputs in real-time. By boosting the power-performance efficiency in dealing with intricate AI tasks, the T1 chip allows for a wide range of applications even in battery-limited environments. In terms of capabilities, the T1 is equipped with a 32-bit RISC-V core and a substantial 384 KB embedded SRAM, which together facilitate fast recognition of patterns within sensor data such as audio signals. The processor draws on the inherent advantages of spiking neural networks, which are adept at task handling through time-sensitive events. This aspect of SNNs enables them to operate with impressive speed and with significantly reduced power requirements compared to conventional architectures. Additional features include numerous interfaces such as QSPI, I2C, UART, and JTAG, providing versatile connectivity options for various sensors. Housed in a compact 2.16mm x 3mm package, the T1 is an ideal candidate for space-constrained applications. It stands out with its ability to execute both spiking and classical neural network models, facilitating complex signal processing tasks ranging from audio processing to inertial measurement unit data handling.
Menta's Adaptive Digital Signal Processor (DSP) is a versatile solution designed to offer adaptable signal processing capabilities within embedded FPGA frameworks. Enabled by the Origami tool suite, this DSP solution allows for dynamic configuration, ensuring that each design is perfectly aligned with distinct hardware requirements.\n\nKey to its functionality is the ability to tailor operand sizes for both the multiplier and ALU, and the programmable nature of DSP block operating modes via the bitstream. This adaptability not only empowers designers with fine control over processing architecture but also offers the ability to fine-tune performance metrics such as frequency, area, and latency.\n\nBuilt with robust support for fast inference, the Adaptive DSP's architecture can be configured at a clock-cycle level. This design model allows for real-time adjustments in DSP block operations, perfect for applications demanding high computational loads across diverse environments. The DSP's ease of integration is facilitated by an intuitive software interface, making it an indispensable tool for engineers seeking to implement comprehensive signal processing within constrained embedded systems.
Akeana offers the 100 Series, a compact and energy-efficient processor line optimized for applications demanding minimal power consumption and compact design. These processors are ideal for deeply embedded controllers across electronics that value low size, low cost, and real-time processing, such as smart home appliances, drones, and wearable technology. Designed for ultra-low power real-time processing, these processors stand out for their adaptability to small-scale, cost-sensitive environments, enabling smarter consumer electronics with efficient power management.
A 32-bit, embedded RISC-V processor core designed with functional safety in mind. This processor is tailored for applications requiring reliability and compliance with safety standards. By incorporating safety features, it supports both deeply embedded and general-purpose processing needs. Its architecture is optimized for energy efficiency, making it suitable for IoT devices and other low-power applications.
The RAIV is a flexible and high-performing General Purpose GPU (GPGPU), fundamental for industries experiencing rapid transformation due to the fourth industrial revolution—autonomous vehicles, IoT, and VR/AR sectors. Built with a SIMT (Single Instruction Multiple Threads) architecture, the RAIV enhances AI workloads with high-speed processing capabilities while maintaining a low-cost construct. This semiconductor IP supports diverse machine learning and neural network applications, optimizing high-speed calculations across multiple threads. Its high scalability allows tailored configurations in core units, effectively balancing performance with power efficiency dependent on application needs. The RAIV is equipped to handle 3D graphics processing and AI integration for edge computing devices, reinforcing its place in advanced technological development. Additionally, the RAIV's support for OpenCL offers compatibility across various heterogeneous computing platforms, facilitating versatile system configurations. Its optimal performance in AI tasks is further extended for use in metaverse applications, presenting a comprehensive solution that unifies graphics acceleration with AI-enhanced computational operations.
The 32-bit RISC CPU Core from VinChip Systems is engineered to provide a high-performance, cost-effective central processing block for various applications. It incorporates a streamlined instruction set architecture, enabling efficient processing power while minimizing silicon footprint, power consumption, and heat generation. This makes it suitable for embedded systems requiring agility and efficiency. Offering robust computational capabilities, this RISC CPU Core excels in both general-purpose and application-specific systems. Its architectural design supports rapid task execution and concurrent processes, which is critical for handling complex computations and multitasking environments. Additionally, its scalable architecture allows developers to tailor the solution to specific needs, optimizing system performance and energy efficiency. The 32-bit RISC CPU Core is easy to integrate into systems, providing seamless interoperability with other components. Extensive support for development tools and software stacks simplifies the design process, making it ideal for consumer electronics, automotive applications, and industrial controls where precision and reliability are paramount.
The eFPGA IP Cores v5 from Menta represent a high-density, programmable logic solution designed for integration within SoCs or ASICs. These embedded FPGAs are crafted to meet diverse market needs, offering designers the flexibility to tailor the exact resources required for their applications. Available in both Soft RTL and Hard GDSII formats, these eFPGAs provide unprecedented design clarity and control.\n\nOne of the key advantages of Menta's eFPGA is its ability to minimize costs and enhance performance. By embedding FPGA functionality on-chip, designers can bypass the limitations of traditional onboard FPGAs, which often pose challenges related to cost and power consumption at high production volumes. Furthermore, integrated eFPGA solutions eliminate the overhead related to I/O pad count and external chip communication, resulting in reduced latency and enhanced efficiency.\n\nMenta underscores the process-portability of its eFPGA cores, having been silicon-proven on more technology nodes than any other provider. Their standard-cell based approach facilitates rapid porting across various semiconductor foundries and node sizes, ensuring maximum adaptability to the latest technological advancements. Security and field-upgradability are integral to Menta's offerings, allowing companies to protect their most sensitive IP throughout the product lifecycle.
The Jotunn8 AI Accelerator is engineered for the demands of large scale, generative AI models like GPT-4. It stands out in the market by significantly improving computational efficiencies, reaching over 50% algorithm efficiency even with large model parameters. This product targets reducing deployment costs to less than $0.002 per query, making advanced AI applications more accessible and affordable. Featuring 6,400 Tflops of fp8 performance and 1,600 Tflops of fp16 capability, Jotunn8's architecture is built to deliver maximum data throughput to its processing cores, avoiding traditional bottlenecks in memory access. The Jotunn8 is fully programmable and designed for seamless performance in cloud and on-premise infrastructures, all while minimizing latency and keeping power consumption in check.
The P8700 Series represents a high-performance multi-core processor family that leverages the RISC-V instruction set architecture to deliver unprecedented flexibility and scalability. Designed for applications that require significant compute power and memory, it offers 4-wide out-of-order pipelines with 2-way simultaneous multi-threading, and can support up to 8 cores per cluster. The processor is tailored for applications in automotive, primarily targeting ASIL B safety standards and ISO 26262 compliance, facilitating its use in safety-critical systems such as ADAS. Incorporating advanced multi-threading capabilities, the P8700 Series enhances bandwidth and power efficiency, crucial for high-performance compute tasks. Its architecture is built to facilitate deterministic latency in heterogeneous computing environments, which is essential for real-time data processing in automotive and cloud data center applications. Moreover, the P8700 Series supports robust system designs with fast data movement capabilities, ensuring optimal performance under varied workload conditions. This processor's configurability is a key advantage, as it allows users to customize it to their specific design requirements while maintaining the benefits of the open RISC-V ecosystem. With its ability to seamlessly integrate with other computing subsystems and accelerators, the P8700 Series empowers developers to construct highly optimized systems that can meet demanding power and capacity constraints across diverse industry applications.
The SiFive Intelligence X280 processor is engineered for high-performance AI dataflow applications, providing scalable vector computing abilities tailored for AI, data management, and inference operations. This RISC-V-based solution integrates a high-performance control processor with vector compute resources, making it ideal for managing AI workloads efficiently. The X280 is equipped with SiFive Intelligence Extensions that enable it to address machine learning operations with enhanced performance and minimal power consumption.
The Tyr AI Processor Family offers a scalable multi-core architecture ideal for any AI or DSP application. It integrates ASIL-D safety standards, making it suitable for advanced driver assistance systems (ADAS) and autonomous driving. Each chip in the Tyr family supports high-level programming and seamless over-the-air updates, providing developers with flexibility and ease of development. The processors achieve near-theoretical efficiency via unique algorithm support, including newer models like BEVformer and Transformers. Additionally, the fully programmable nature of Tyr chips allows them to handle diverse algorithms efficiently, meeting the stringent power and cost requirements of automotive applications.
The Chimera SDK is an advanced software development toolkit providing a comprehensive environment for developers working on complex application codes targeting the Chimera GPNPU processors. This toolkit facilitates the integration of both machine learning graphs and traditional C++ code, empowering developers to optimize applications across different frameworks and work environments. The SDK is accessible through Quadric's DevStudio, enabling seamless simulation and profiling of AI software. Developers can utilize a visual interface to experiment with optimized libraries and pre-configured machine learning models. This user-friendly platform supports online access or can be deployed within private clouds or on-premises, offering flexibility in development environments. Key to its utility is the Chimera Graph Compiler which extracts machine learning models into efficient, optimized C++ code. This process involves converting ML models from popular frameworks like TensorFlow and PyTorch, ensuring compatibility and performance optimization. This compiler, along with the LLVM C++ compiler integration, assures that applications can be fine-tuned to meet high-performance expectations while reducing development time.
The GateMate FPGA series from Cologne Chip AG is crafted to support a variety of FPGAs applications, especially in small to medium-sized enterprises. These field-programmable gate arrays excel in offering first-rate performance regarding logic capacity, power efficiency, and compatibility with PCB designs. Notably, GateMate FPGAs are recognized for delivering industry-leading low costs, rendering them accessible for diverse uses from academic initiatives to extensive production lines. These FPGAs can leverage innovative architecture integrating line programmable elements and a sophisticated routing mechanism, facilitating efficient multiplier constructions. Additionally, memory-intensive applications enjoy block RAM benefits, while the versatile General Purpose IOs allow configurations as single-ended or differential pairs, enhanced by a SerDes interface for high-speed communications.
The JPEG FPGA Cores offer robust and highly customizable JPEG compression and decompression capabilities, ideal for numerous applications requiring high-resolution image processing. These cores are fully ITAR-compliant, catering to a broad spectrum of industrial and strategic applications. With functionalities that support true grayscale processing, these cores present a versatile solution by accommodating diverse image formats and requirements. The ease of customization allows users to fine-tune the cores to align with specific project needs, ensuring optimized performance for varied imaging applications. The JPEG FPGA Cores have undergone meticulous design to provide seamless integration into different FPGA ecosystems, ensuring flexibility across projects. The cores support both baseline JPEG encoding and decoding, enabling efficient handling of large image files without significant loss of quality. Furthermore, these cores offer a balance between high efficiency and adaptability, making them a valuable asset for developers and engineers focusing on image-rich content. With an emphasis on accessibility, A2e Technologies provides a low-cost evaluation license, which allows potential users to explore the capabilities of the cores and assess their suitability before full-scale implementation. This initiative reflects the enterprise's commitment to fostering innovation and supporting developers in achieving precise and reliable image processing outputs through its solutions.