All IPs > Platform Level IP
Platform Level IP is a critical category within the semiconductor IP ecosystem, offering a wide array of solutions that are fundamental to the design and efficiency of semiconductor devices. This category includes various IP blocks and cores tailored for enhancing system-level performance, whether in consumer electronics, automotive systems, or networking applications. Suitable for both embedded control and advanced data processing tasks, Platform Level IP encompasses versatile components necessary for building sophisticated, multicore systems and other complex designs.
Subcategories within Platform Level IP cover a broad spectrum of integration needs:
1. **Multiprocessor/DSP (Digital Signal Processing)**: This includes specialized semiconductor IPs for handling tasks that require multiple processor cores working in tandem. These IPs are essential for applications needing high parallelism and performance, such as media processing, telecommunications, and high-performance computing.
2. **Processor Core Dependent**: These semiconductor IPs are designed to be tightly coupled with specific processor cores, ensuring optimal compatibility and performance. They include enhancements that provide seamless integration with one or more predetermined processor architectures, often used in specific applications like embedded systems or custom computing solutions.
3. **Processor Core Independent**: Unlike core-dependent IPs, these are flexible solutions that can integrate with a wide range of processor cores. This adaptability makes them ideal for designers looking to future-proof their technological investments or who are working with diverse processing environments.
Overall, Platform Level IP offers a robust foundation for developing flexible, efficient, and scalable semiconductor devices, catering to a variety of industries and technological requirements. Whether enhancing existing architectures or pioneering new designs, semiconductor IPs in this category play a pivotal role in the innovation and evolution of electronic devices.
The 2nd Generation Akida platform is a substantial advancement in Brainchip's neuromorphic processing technology, expanding its efficiency and applicability across more complex neural network models. This advanced platform introduces support for Temporal Event-Based Neural Nets and Vision Transformers, aiming to enhance AI performance for various spatio-temporal and sensory applications. It's designed to drastically cut model size and required computations while boosting accuracy. Akida 2nd Generation continues to enable Edge AI solutions by integrating features that improve energy efficiency and processing speed while keeping model storage requirements low. This makes it an ideal choice for applications that demand high-performance AI in Edge devices without needing cloud connectivity. Additionally, it incorporates on-chip learning, which eliminates the need to send sensitive data to the cloud, thus enhancing security and privacy. The platform is highly flexible and scalable, accommodating a wide array of sensory data types and applications, from real-time robotics to healthcare monitoring. It's specifically crafted to run independently of the host CPU, enabling efficient processing in compact hardware setups. With this generation, Brainchip sets a new standard for intelligent, power-efficient solutions at the edge.
The NMP-750 is engineered as a performance accelerator tailored for edge computing applications that demand robust processing power and versatility. It is ideally deployed in environments such as automotive, AMR and UAV systems, AR/VR applications, as well as smart infrastructure projects like smart buildings, factories, and cities. Its design principles aim to enhance security and surveillance systems while supporting advanced telecommunications solutions. This comprehensive IP can attain up to 16 TOPS, thereby addressing needs for high throughput and efficiency in data processing tasks. The NMP-750 includes up to 16 MB of local memory, utilizing either RISC-V or Arm Cortex-R or A 32-bit CPUs to manage operational complexity through three 128-bit AXI4 interfaces for host, CPU, and data processes. This infrastructure not only ensures rapid data-handling capabilities but also optimizes system-level operations for various emerging technologies. Ideal for managing multi-camera stream processing and enhancing spectral efficiency, it is equally suited for mobility and autonomous control systems—key to future smart city and factory applications. The NMP-750's support for comprehensive automation and data analytics offers companies the potential to develop cutting-edge technologies, driving industry standards across domains.
KPIT's Connected Vehicle Solutions leverage modern cloud and edge computing to enhance the connectivity features of today’s vehicles. This technology supports secure data management, advanced analytics, and comprehensive solutions for real-time vehicle connectivity. The platform is engineered to provide enriched data-driven insights, enabling OEMs to better handle vehicle data, improve cybersecurity measures, and ensure compliance with emerging regulatory standards. By transforming data into strategic advantages, KPIT aids automotive manufacturers in delivering enhanced user experiences and operational efficiencies.
KPIT's iDART platform addresses the challenges posed by software-defined vehicles, focusing on optimizing diagnostics, maintenance, and aftersales services. By deploying advanced AI-driven diagnostics and self-learning systems, the platform enhances the reliability of vehicle servicing and improves the overall customer experience. This transformation embraces legacy system integration while advancing toward fully automated, predictive, and customer-centered service models that support the evolving demands of the automotive market.
Vehicle Engineering & Design Solutions by KPIT revolve around transforming vehicle development through cutting-edge design and simulation technologies. By employing advanced Computer Aided Design (CAD) and virtual prototyping, KPIT enhances product development and market entry speed. The focus is on aligning vehicle aesthetics with functional performance, ensuring that vehicles not only appeal to modern consumers but also comply with modern sustainability mandates. KPIT’s holistic approach offers comprehensive solutions that simplify the design and validation processes, fostering innovation in both conventional and electric vehicle configurations.
The NMP-350 is a low-power and cost-effective end-point accelerator designed to cater to applications across various industries. This accelerator finds its niche in markets such as automotive, AIoT, and Industry 4.0, where efficiency and scalability are critical. With potential applications in driver authentication, digital mirrors, and personalized user experiences, it is also applicable in predictive maintenance systems, machine automation, and health monitoring. Technically, the NMP-350 boasts an impressive capacity of up to 1 TOPS (Tera Operations Per Second), supported by up to 1 MB of local memory. The system is based on a flexible architecture utilizing either RISC-V or Arm Cortex-M 32-bit CPUs, accommodating three AXI4 interfaces with 128 bits each dedicated to host, CPU, and data processes. This composition assures its capability to handle a multitude of tasks efficiently while maintaining a low power profile. Its integration into smart appliances and wearable technologies showcases its versatility, providing industry players with a robust solution for building smarter and more reliable products. As industries move towards more interconnected and intelligent systems, the NMP-350 provides the necessary technology to drive innovation forward.
The WAVE6 codec series by Chips&Media is a versatile solution offering multi-standard video encoding and decoding capabilities, tailored for high-resolution content delivery. Integrating AV1 encoding, it ensures superior streaming and bandwidth optimization. This solution is especially viable for devices requiring high efficiency and low power consumption, such as data centers and surveillance cameras. With its dual-core architecture, the WAVE6 achieves better processing speeds, supporting up to 8K resolution at 60 frames per second. Engineered with an optimized architecture, WAVE6 includes features like frame buffer compression and color space conversion, which enhance the overall performance while minimizing power use. Its design is straightforward, with a single-clock domain facilitating on-the-fly processes for various codec engines. This codec is not only efficient in terms of power usage but also capable of supporting a range of YUV formats and bit depths, maintaining high image quality with features like rotate/mirror and down-scaling functionalities. The WAVE6's specification supports a broad array of applications, from data centers needing robust processing power to automotive systems where efficiency and reliability are paramount. Its compatibility with multiple industry standards, including HEVC, AVC, and VP9, ensures that it meets diverse customer requirements while optimizing usage of external memory bandwidth through advanced compression technologies.
The ORC3990 is a sophisticated System on Chip (SoC) solution designed for low-power sensor-to-satellite communication within the LEO satellite spectrum. Utilizing Totum's DMSS technology, it achieves superior doppler performance, facilitating robust connectivity for IoT devices. The integration of an RF transceiver, power amplifiers, ARM CPUs, and memory components makes it a highly versatile module. Leveraging advanced power management technology, this SoC supports a battery life that exceeds ten years, even within industrial temperature ranges from -40 to +85°C. It's optimized for usage with Totum's global LEO satellite network, ensuring substantial indoor signal coverage without the need for additional GNSS components. Efficiency is a key feature, with the chip operating in the 2.4 GHz ISM band, providing unparalleled connectivity regardless of location. Compact in design, comparable in size to a business card, and designed for easy mounting, the ORC3990 offers sought-after versatility for IoT applications. The ability to function with excellent TCO in terms of cost compared to terrestrial IoT solutions makes it a valuable asset for any IoT deployment focused on sustainability and longevity.
The H-Series PHY offers a groundbreaking approach to high bandwidth memory solutions, specifically fine-tuned for applications in AI, ML, graphics, and high-performance computing. This PHY IP core is engineered to deliver top-notch performance, accommodating challenging demands with optimized area and power consumption. It supports HBM2 and HBM2E standards with a robust data rate capability of up to 3200 MB/sec, allowing seamless integration with advanced systems. This PHY leverages a 2.5D interposer level design and supports up to 16 channels, providing substantial bandwidth in competitive environments. Notably, it is compatible with pseudo-channel configurations and manages up to 8 stacked HBM2E memories, delivering exceptional memory performance. The DFI 5.0 interface ensures smooth connectivity, making it ideal for AI, ML, graphics, and networking applications, delivering peak performance in various scenarios. Optimized for areas of low power and high efficiency, the H-Series PHY is crafted to reduce latency intricately. Its structural efficiency is underscored by its ability to balance performance with minimalistic design requirements, setting a benchmark for PHY implementations in demanding settings.
Cortus's High Performance RISC-V Processor represents the pinnacle of processing capability, designed for demanding applications that require high-speed computing and efficient task handling. It features the world’s fastest RISC-V 64-bit instruction set architecture, implemented in an Out-of-Order (OoO) execution core, supporting both single-core and multi-core configurations for unparalleled processing throughput. This processor is particularly suited for high-end computing tasks in environments ranging from desktop computing to artificial intelligence workloads. With integrated features such as a multi-socket cache coherent system and an on-chip vector plus AI accelerator, it delivers exceptional computation power, essential for tasks such as bioinformatics and complex machine learning models. Moreover, the processor includes coherent off-chip accelerators, such as CNN accelerators, enhancing its utility in AI-driven applications. The design flexibility extends its application to consumer electronics like laptops and supercomputers, positioning the High Performance RISC-V Processor as an integral part of next-gen technology solutions across multiple domains.
The NMP-550 stands as a performance efficiency accelerator, particularly crafted for applications that demand high computational power combined with energy efficiency. This IP is especially suited for markets including automotive, mobile devices, AR/VR, and security-focused technologies. Its applicability spares a wide spectrum, fostering innovation in driver monitoring, fleet management, and advanced image or video analytics. Along with intruder detection and compliance systems, it bolsters its utility in medical devices for enhanced diagnostic capabilities. Technologically, the NMP-550 delivers up to 6 TOPS, which provides a significant boost in data processing capability. It features up to 6 MB of local memory, ensuring swift and effective data management. The design is underpinned by a choice of RISC-V or Arm Cortex-M or A 32-bit CPUs, along with three AXI4 interfaces supporting 128 bits each, allocated for host, CPU, and data handling. Such specification allows this accelerator to proficiently tackle tasks of various computational demands with resilience and efficiency. Its design caters to cross-disciplinary needs, making it an excellent fit for drone operations, robotics, and security systems requiring real-time processing and decision-making capabilities. With the inherent ability to process substantially more data at improved efficiencies, this IP aligns well with the future of immersive and interactive application deployments.
The PolarFire FPGA Family by Microsemi is engineered to deliver cost-effectiveness alongside exceptional power efficiency, positioning itself as the optimal choice for mid-range FPGA applications. Crafted to offer transceivers ranging from 250 Mbps to a robust 12.7 Gbps, these FPGAs cater to diverse bandwidth requirements. With logic elements spanning 100K to 500K and incorporating up to 33 Mbits of RAM, the PolarFire series seamlessly addresses demanding processing needs while ensuring secure and reliable performance. At the heart of its design philosophy is a focus on best-in-class security features combined with high reliability, making it particularly relevant for industries like automotive, industrial, and communication infrastructures where failure is not an option. It supports applications that require low power consumption without sacrificing performance, which is increasingly important in today's energy-conscious environments. These FPGAs find their versatility in a range of applications, from driving advancements in ADAS in the automotive industry to supporting broadband and 5G mobile infrastructures in telecommunications. The family also extends its use cases to data center technologies, highlighting its adaptability and efficiency in both digital and analog processing fields. With such a broad spectrum of applicability, the PolarFire FPGA Family stands as a shining example in Microsemi's product arsenal, delivering solutions tuned for innovation and performance.
The AndeShape Platforms include a range of systems designed for developing with AndesCore processors. These platforms are split into categories such as microcontroller platforms and FPGA development kits. They offer integrated solutions with pre-configured IP blocks to simplify the design process for complex systems. Through its assortment of hardware development tools, AndeShape platforms cater to various stages of product development from inception to demonstration, making it easier for engineers to create efficient, scalable solutions.
The Automotive AI Inference SoC by Cortus is a cutting-edge chip designed to revolutionize image processing and artificial intelligence applications in advanced driver-assistance systems (ADAS). Leveraging RISC-V expertise, this SoC is engineered for low power and high performance, particularly suited to the rigorous demands of autonomous driving and smart city infrastructures. Built to support Level 2 to Level 4 autonomous driving standards, this AI Inference SoC features powerful processing capabilities, enabling complex image processing algorithms akin to those used in advanced visual recognition tasks. Designed for mid to high-end automotive markets, it offers adaptability and precision, key to enhancing the safety and efficiency of driver support systems. The chip's architecture allows it to handle a tremendous amount of data throughput, crucial for real-time decision-making required in dynamic automotive environments. With its advanced processing efficiency and low power consumption, the Automotive AI Inference SoC stands as a pivotal component in the evolution of intelligent transportation systems.
The Chimera GPNPU stands as a powerful neural processing unit tailor-made for on-device AI computing. This processor architecture revolutionizes the landscape of SoC design, providing a unified execution pipeline that integrates both matrix and vector operations with control code typically handled by separate cores. Such integration boosts developer productivity and enhances performance significantly. The Chimera GPNPU's ability to run diverse AI models—including classical backbones, vision transformers, and large language models—demonstrates its adaptability to future AI developments. Its scalable design enables handling of extensive computational workloads reaching up to 864 TOPs, making it suitable for a wide array of applications including automotive-grade AI solutions. This licensable processor core is built with a unique hybrid architecture that combines Von Neuman and 2D SIMD matrix instructions, facilitating efficient execution of a myriad array of data processing tasks. The Chimera GPNPU has been optimized for integration, allowing seamless incorporation into modern SoC designs for high-speed and power-efficient computing. Key features include a robust instruction set tailored for ML tasks, effective memory optimization strategies, and a systematic approach to on-chip data handling, all working to minimize power usage while maximizing throughput and computational accuracy. Furthermore, the Chimera GPNPU not only meets contemporary demands of AI processing but is forward-compatible with potential advancements in machine learning models. Through comprehensive safety enhancements, it addresses stringent automotive safety requirements, ensuring reliable performance in critical applications like ADAS and enhanced in-cabin monitoring systems. This combination of performance, efficiency, and scalability positions the Chimera GPNPU as a pivotal tool in the advancement of AI-driven technologies within industries demanding high reliability and long-term support.
The GSHARK GPU IP accelerates graphics on embedded systems, delivering high performance with low power consumption while minimizing CPU load. Designed for embedded devices like digital cameras and automotive equipment, the GSHARK-IP leverages advanced proprietary architectures to achieve smooth graphics rendering akin to those seen on PCs and gaming consoles. Its proven track record with over a hundred million shipments highlights its reliability in commercial silicons.
The Neural Processing Unit (NPU) from OPENEDGES offers a state-of-the-art deep learning accelerator, optimized for edge computing with advanced mixed-precision computation. Featuring a powerful network compiler for efficient memory usage, it handles complex neural network operations while minimizing DRAM traffic. Its layered architecture supports modern algorithmic needs, including transformers, allowing for parallel processing of neural layers. The NPU provides significant improvements in compute density and energy efficiency, targeting applications from automotive to surveillance, where high-speed, low-power processing is critical.
AndesCore processors are designed as high-performance CPU cores targeting a variety of market segments. These processors, built on the RISC-V compatible AndeStar™ architecture, provide scalable solutions suitable for applications in AI, IoT, and more. The V5 core family is renowned for its performance efficiency and flexibility, featuring 32-bit and 64-bit cores that support an array of computing tasks. Each core is engineered to meet diverse application requirements, ranging from streamlined low-power designs to high-throughput models.
The Arria 10 System on Module (SoM) is designed with an emphasis on embedded and automotive vision applications. This compact module leverages Altera's Arria 10 SoC devices in a sleek 29x29 mm package, offering a plethora of interfaces while maintaining a small, efficient form factor. It features an Altera Arria 10 SoC FPGA with a range from 160 to 480 KLEs, coupled with a Cortex A9 Dual-Core CPU. This enables robust integration and performance for demanding applications. The module's power management system ensures a seamless power-up and -down sequence, requiring only a 12V supply from the baseboard. Its dual DDR4 memory interfaces provide up to 2.4 Gbit/s per pin, offering a total bandwidth of up to 230 Gbit/s for both CPU and FPGA memory systems. This module supports a wide array of high-speed interfaces, including PCIe Gen3 x8, 10/40 Gbit/s Ethernet, DisplayPort, and 12G SDI, making it suitable for complex imaging and communication tasks. Additional features include up to 32 LVDS lanes for configurable RX or TX, two USB interfaces with OTG support, and ARM I²C, SPI, and GPIO interface signals. Furthermore, the Arria 10 SoM includes pre-configured IP for memory controllers and an Angstrom Linux distribution, facilitating rapid development and deployment of applications.
NeuroMosAIc Studio is a comprehensive software platform designed to accelerate AI development and deployment across various domains. This platform serves as an essential toolkit for transforming neural network models into hardware-optimized formats specific for AiM Future's accelerators. With broad functionalities including conversion, quantization, compression, and optimization of neural networks, it empowers AI developers to enhance model performance and efficiency. The studio facilitates advanced precision analysis and adjustment, ensuring models are tuned to operate optimally within hardware constraints while maintaining accuracy. Its capability to generate C code and provide runtime libraries aids in seamless integration within target environments, enhancing the capability of developers to leverage AI accelerators fully. Through this suite, companies gain access to an array of tools including an NMP compiler, simulator, and support for NMP-aware training. These tools allow for optimized training stages and quantization of models, providing significant operational benefits in AI-powered solutions. NeuroMosAIc Studio, therefore, contributes to reducing development cycles and costs while ensuring top-notch performance of deployed AI applications.
Certus Semiconductor specializes in advanced RF/analog designs that encompass a broad range of solutions, from individual components to complete wireless transceivers. Their expertise extends to developing cutting-edge low-power wireless front-end technologies. They offer silicon-proven RF IP, full-chip RF products, and next-generation wireless IPs that support high-quality communication standards, including LTE, WiFi, and GNSS. Equipped with custom PLLs capable of operating at frequencies up to 6GHz, these solutions ensure low phase noise and minimal jitter for precise applications.
The Cortus Lotus 1 is a multifaceted microcontroller that packs a robust set of features for a range of applications. This cost-effective, low-power SoC boasts RISC-V architecture, making it suitable for advanced control systems such as motor control, sensor interfacing, and battery-operated devices. Operating up to 40 MHz, its RV32IMAFC CPU architecture supports floating-point operations and hardware-accelerated integer processing, optimizing performance for computationally demanding applications. Designed to enhance code density and reduce memory footprint, Lotus 1 incorporates 256 KBytes of Flash memory and 24 KBytes of RAM, enabling the execution of complex applications without external memory components. Its six independent 16-bit timers with PWM capabilities are perfectly suited for controlling multi-phase motors, positioning it as an ideal choice for power-sensitive embedded systems. This microcontroller's connectivity options, including multiple UARTs, SPI, and TWI controllers, ensure seamless integration within a myriad of systems. Lotus 1 is thus equipped to serve a wide range of market needs, from personal electronics to industrial automation, ensuring flexibility and extended battery life across sectors.
The Metis AIPU PCIe AI Accelerator Card represents a powerful computing solution for high-demand AI applications. This card, equipped with a single Metis AI Processing Unit, delivers extraordinary processing capabilities, reaching up to 214 Tera Operations Per Second (TOPS). Designed to handle intensive computing tasks, it is particularly suited for applications requiring substantial computational power and rapid data processing, such as real-time video analytics and AI-driven operations in various industrial and retail environments. This accelerator card integrates seamlessly into PCIe slots, providing developers with an easy-to-deploy solution enhanced by Axelera AI's Voyager Software Development Kit. The kit simplifies the deployment of neural networks, making it a practical tool for both seasoned developers and newcomers to AI technology. The card's power efficiency is a standout feature, aimed at reducing operational costs while ensuring optimal performance. With its innovative architecture, the Metis AIPU PCIe AI Accelerator Card not only meets but exceeds the needs of modern AI applications, ensuring users can harness significant processing power without the overheads associated with traditional systems.
The ULYSS MCU range from Cortus is a powerful suite of automotive microcontrollers designed to address the complex demands of modern automotive applications. These MCUs are anchored by a highly optimized 32/64-bit RISC-V architecture, delivering impressive performance levels from 120MHz to 1.5GHz, making them suitable for a variety of automotive functions such as body control, safety systems, and infotainment. ULYSS MCUs are engineered to accommodate extensive application domains, providing reliability and efficiency within harsh automotive environments. They feature advanced processing capabilities and are designed to integrate seamlessly into various automotive systems, offering developers a versatile platform for building next-generation automotive solutions. The ULYSS MCU family stands out for its scalability and adaptability, enabling manufacturers to design robust automotive electronics tailored to specific needs while ensuring cost-effectiveness. With their support for a wide range of automotive networking and control applications, ULYSS MCUs are pivotal in the development of reliable, state-of-the-art automotive systems.
Trimension SR200 is a single IC UWB chip designed for mobile applications, integrating both ranging and radar capabilities to facilitate enhanced device interactions. This chip is essential for mobile devices requiring high precision in location tracking and interaction detection. Benefiting from its compact integration, it supports seamless wireless communications, catering to the advancement of mobile technology through superior UWB features.
The Cobra platform is designed specifically for the Xilinx Kintex-7, delivering robust performance for development and prototyping within digital systems. This platform facilitates the rapid integration and testing of Trilinear's extended IP offerings, particularly for advanced DisplayPort applications. It provides essential tools for developers looking to streamline their design process and reduce project timelines.
Bluespec's Portable RISC-V Cores are crafted to provide extensive flexibility and compatibility across numerous FPGA platforms, including industry leaders such as Achronix, Xilinx, and Lattice. These cores are designed to support both Linux and FreeRTOS, offering developers a broad range of applications in system development and software integration. Leveraging standard open-source development tools, these cores allow engineers to adopt, modify, and deploy RISC-V solutions with minimal friction. This simplifies the development process and enhances compatibility with various hardware scenarios, promoting an ecosystem where innovation can thrive without proprietary constraints. The Portable RISC-V Cores cater to developers who require adaptable and scalable solutions for diverse projects. By accommodating different FPGA platforms and supporting a wide range of development environments, they represent a versatile choice for implementing cutting-edge designs in the RISC-V architecture space.
VisualSim Architect is a sophisticated software platform dedicated to the modeling and simulation of system performance, power, and functionality. It empowers system engineers to explore designs virtually, measuring potential bottlenecks and power consumption before actual production begins. The platform aids in validating different hardware and software architectures, ensuring that the system is designed for optimal efficiency and performance. It also enables users to create virtual prototypes that mimic real-life system behaviors, thus facilitating a deeper understanding of potential implementation challenges. This preemptive approach allows companies to fine-tune their designs, ensuring that all components work harmoniously, thereby reducing risk and accelerating time-to-market. Furthermore, the platform's flexible system-level modeling capabilities cater to a diverse range of application fields, from automotive to consumer electronics.
Chips&Media's WAVE5 is a proven multi-standard video codec IP renowned for its versatility in handling a broad spectrum of video formats. Designed for high-performance applications, it ensures efficient processing by utilizing dual-core technology, suitable for environments like data centers and surveillance setups. The WAVE5's capability to encode and decode at high resolutions and frame rates makes it a reliable choice for video-intensive operations. Incorporating sophisticated features such as frame buffer compression and multi-instance support, WAVE5 provides enhanced video quality while ensuring minimal latency. With support for industry standards like HEVC and AVC, it meets diverse demands within the multimedia domain, efficiently processing video streams at up to 8K60fps. The codec is optimized for power usage, allowing it to deliver excellent performance without excessive resource consumption. WAVE5's interface architecture supports robust data transfer and system control through AMBA3 APB and AXI protocols, ensuring seamless communication and operational efficiency. This is complemented by comprehensive support for bit-depth and YUV format conversions, enhancing compatibility with various media types and application needs. Its wide applicability in fields such as automotive, drones, and home entertainment underscores its adaptability and powerful processing capabilities.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores offer top-tier video compression capabilities, optimized for FPGA implementations. These cores are ITAR-compliant and customizable, supporting 1080p60 H.264 Baseline profiles with a single core. Notable for their compact size and high speed, these cores suit various configurations including H.264 Encoder, H.264 CODEC, and H.264 I-Frame Only Encoder variants. Their flexibility allows customization for specific pixel depths and resolutions, catering to unique project demands. An evaluation license is available for this high-performance core, designed to integrate seamlessly into FPGA environments, delivering minimal latency and high throughput that meets industry standards.
AccelerComm's Software-Defined High PHY is an adaptable O-RAN solution, optimized for the ARM processor architecture. This High PHY solution can operate with or without hardware acceleration, tailored to meet various capacity and power specifications. Developed to complement ASIC/SoC products, it supports a wide range of platforms, enhancing performance flexibility and integration simplicity. This solution is particularly beneficial in environments where dynamic computing capabilities are required and is pivotal in ensuring effective network scaling and performance delivery.
Trimension SR100 is focused on the mobile segment, enhancing devices through pre-installed FiRa stacks that provide dependable UWB functionality. Its design supports fundamental UWB tasks like ranging, making it an ideal choice for mobile platforms requiring robust and accurate positioning solutions. Integration into mobile devices allows for seamless communications with other UWB-enabled technologies, making it a staple in the evolution of interconnected consumer electronics.
ZIA Stereo Vision is an advanced stereoscopic vision module designed to provide precise distance estimation. By combining left and right camera inputs, it leverages semi-global matching algorithms to derive depth maps essential for applications like autonomous vehicles and robotic navigation. It operates under varying image resolutions and provides high-speed processing, ensuring integration into systems where rapid environmental mapping is crucial. Its hardware design optimizes power, space, and performance metrics, making it ideal for high-demand use cases that rely on accurate spatial awareness.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
The E6-A series in SiFive's automotive portfolio delivers an unrivaled combination of safety, security, and performance, built to satisfy complex and evolving vehicle requirements. With balanced power efficiency and area optimization, the E6-A processors are tailored for applications ranging from body and powertrain systems to central compute solutions in modern vehicles. Compliant with ISO 26262 ASIL and cybersecurity standards, E6-A processors ensure integration ease and functionality in diverse automotive settings, supporting the comprehensive utilization of SiFive’s RISC-V automotive innovations.
The SiFive Performance family of processors is crafted to address the demands of data center workloads, multimedia processing, networking, and storage applications. Featuring 64-bit, out-of-order cores, they provide a wide range of design options tailored to workload necessities. This family includes processors ranging from three to six-wide out-of-order cores, equipped with dedicated vector engines optimized for AI workloads. These processors deliver top-tier performance within energy-efficient parameters, making them highly suitable for mobile devices, consumer electronics, and edge computing infrastructure.
The Dynamic Neural Accelerator II (DNA-II) by EdgeCortix represents a new leap in neural network processing. This IP core is exceptionally efficient and provides scalable performance by reconfiguring runtime interconnects between its computing units. Supporting both convolutional and transformer models, DNA-II is tailored for edge AI tasks that demand high parallel processing. The modular DNA-II stands out by enhancing parallelism and optimizing on-chip memory bandwidth usage. Its symbiotic relationship with software solutions like the MERA compiler boosts its efficacy in deploying neural networks across varied applications, from smart cities to automotive systems.
The iniDSP is a versatile 16-bit fixed-point digital signal processor core crafted for system-on-chip applications. Emphasizing adaptability and performance, this DSP is suitable for power-sensitive applications such as hearing aids to more demanding processing tasks in audio compression and signal conditioning. It benefits from a 100% technology-independent design, aligning it well with both FPGA and ASIC environments.<br/><br/>The core is based on the architecture of the CD2450A from Clarkspur Inc., ensuring a high degree of reusability and performance optimization. It features a 16x16 signed/unsigned multiplier with a 40-bit accumulator, tailoring it for efficient algorithm implementation while minimizing power consumption.<br/><br/>Supporting a comprehensive development ecosystem, the iniDSP provides support for assembly, linking, and debugging, enabling efficient development and deployment of DSP applications. Its robust design makes it a compelling alternative to off-chip DSPs for embedded systems, enhancing the overall system efficiency and reducing latency.
Catering specifically to the automotive industry, SiFive Automotive solutions provide advanced applications and real-time processing architecture suited for the latest vehicle requirements. These processors deliver optimized power consumption and area efficiency, with a focus on functional safety, security, and performance. The automotive product line complies with ISO 26262 ASIL standards and ISO/SAE 21434:2021 cybersecurity requirements, which assists automotive OEMs in meeting global regulatory standards. SiFive's RISC-V safety processors meet the needs of diverse automotive segments, including ADAS, IVI, and powertrain systems.
TySOM Boards are a powerful solution in Aldec's line of embedded system prototyping tools, bringing the practicality of high-performance FPGA-based platforms to system design applications. These boards integrate a range of FPGAs like Xilinx’s Zynq UltraScale+, Zynq-7000, and Microchip's PolarFire SoC, catering to a broad spectrum of advanced computational needs. With industry standard interfaces such as FMC and BPX, these boards are not only versatile but also easily expandable with Aldec’s extensive daughter card selection. Thus, they stand out in facilitating the fast development of embedded applications spanning from automotive systems to AI, machine learning, and IoT. TySOM Boards provide a user-friendly platform that enables engineers to bridge the gap between conceptual design and physical implementation, fostering innovation in high-demand sectors like automotive advanced driver assistance systems (ADAS) and industrial automation. Their design supports a multitude of applications where performance and reliability are paramount, thus allowing designers unprecedented flexibility and capability in high-stakes development environments. As embedded system prototyping continues to grow in complexity, TySOM Boards offer a scalable path forward, meeting the challenges of next-generation technology design and deployment.
Positioned for entry-level server and computing use, the SCR9 packs a high-performance 64-bit RISC-V design with server-level features. Its dual-issue 12-stage pipeline combines with sophisticated memory systems and a network-on-chip L3 cache, allowing for enhanced processing across demanding applications. With support for advanced security, vector operations, and robust multitask environments, SCR9 is fit for servers, video processing, and high-end embedded computing, reinforcing flexibility with AOSP and Linux compatibility.
The Time-Triggered Protocol (TTP) is a communication protocol engineered to address the growing complexity and safety requirements of distributed electronic networks. TTP facilitates reliable network operation for modern vehicle systems, reducing lifecycle costs and supporting seamless integration. This protocol offers significant improvements in communication bandwidth compared to traditional systems such as ARINC 429 and CAN. TTP's capacity for deterministic communication aids in designing advanced integrated systems, offering robust solutions for time- and safety-critical applications, backed by mature development tools and standard components.
Trimension SR040 is designed specifically for UWB tagging in both industrial and IoT sectors. It supports FiRa stacks, offering reliable and secure communication across devices. Ideal for tracking systems, the SR040 is engineered to ensure precision in location-based applications and utilizes the secure FiRa protocol to maintain consistent performance.
Trimension SR250 is an innovative ultra-wideband solution designed for applications in industrial and IoT settings. It offers precise ranging capabilities and is an integral component in creating ultra-wideband-enabled devices and anchors. With the integration of both UWB ranging and radar technologies in a single chipset, the SR250 serves as a versatile tool in environments where precise location tracking and secure communications are necessary.
The ONNC Calibrator is crafted to optimize AI System-on-Chips by employing post-training quantization (PTQ) techniques to maintain high precision, especially in architectures using fixed-point formats like INT8. By leveraging architecture-aware quantization, it ensures chips retain 99.99% accuracy, offering unparalleled precision control across diverse hardware configurations. This calibrator supports configurable bit-width architectures, allowing the balance of precision and performance to be tailored for various applications. Capable of working with different AI frameworks such as ONNX and PyTorch, the calibrator aligns seamlessly with standard PTQ workflows without needing complex retraining. Its internal AI engine autonomously determines optimal scaling factors, making it an indispensable tool in maintaining model accuracy while reducing computational demand.
The NOC-X technology offers a revolutionary approach to interconnect chip architectures, enabling efficient communication pathways across multi-core processors. Aimed at high-demand data-centric applications, it optimizes signal transmission for enhanced processing efficacy and reduced bottlenecks across complex computational frameworks. NOC-X leverages a digital-centric approach to network on chip design, minimizing power consumption without compromising on data exchange speeds. This IP is crucial for scenarios where rapid, reliable communication across various cores is paramount, ensuring that all parts of the system efficiently interact in real-time. This capability is essential for data-heavy industries pushing the boundaries of technology. Supporting tech nodes from 12nm to 28nm, NOC-X is adaptable to a wide range of applications, from consumer electronics to high-performance computing solutions. Its introduction into chiplet technology opens avenues for scalable, adaptable systems that can evolve with advancing technological demands, delivering significant gains in speed and operational efficiency.
Dyumnin Semiconductors' RISCV SoC is a powerful, 64-bit quad-core server-class processor tailored for demanding applications, integrating a multifaceted array of subsystems. Key features include an AI/ML subsystem equipped with a tensor flow unit for optimized AI operations, and a robust automotive subsystem supporting CAN, CAN-FD, and SafeSPI interfaces.\n\nAdditionally, it includes a multimedia subsystem comprising HDMI, Display Port, MIPI, camera subsystems, Gfx accelerators, and digital audio, offering comprehensive multimedia processing capabilities. The memory subsystem connects to various prevalent memory protocols like DDR, MMC, ONFI, NorFlash, and SD/SDIO, ensuring vast compatibility.\n\nThe RISCV SoC's design is modular, allowing for customization to meet specific end-user applications, offering a flexible platform for creating SoC solutions with bespoke peripherals. It also doubles as a test chip available as an FPGA for evaluative purposes, making it ideal for efficient prototyping and development workflows.
The SiFive Essential processors offer a highly flexible IP platform, allowing customization to fit specific application needs. These processors span microcontrollers, IoT devices, real-time control, and general processing tasks. With options ranging from the most compact 2-3 stage MCUs to complex, superscalar designs suitable for Linux-based applications, the Essential series provides exceptional configurability. It caters to a wide range of market demands while maintaining a focus on power and area optimization, making it optimal for embedded systems and control plane processing.
Time-Triggered Ethernet (TTE) is a state-of-the-art networking technology designed for deterministic real-time communication over Ethernet. It integrates seamlessly with existing Ethernet infrastructure, providing fault-tolerant solutions for critical systems in aerospace, automotive, and industrial applications. TTE simplifies the design of networks by maintaining safety and redundancy at the network level, thus easing the application design processes. It ensures precise traffic scheduling, allowing for the integration of tight control loops and the certification of safety networks. TTE's ability to offer replicated packet communication guarantees message transmission even in fault scenarios, enhancing system availability and simplifying failure management.
The Vega eFPGA from Rapid Silicon represents an innovative leap in providing customizable FPGA capabilities to System-on-Chip (SoC) designs. This eFPGA is designed to deliver flexibility and efficiency, allowing a seamless integration that enhances performance without raising costs. By embedding programmability directly into SoCs, Vega eFPGA facilitates diverse and adaptable computing needs. Structured with three configurable tile types – CLB, BRAM, and DSP – the Vega eFPGA is engineered for optimal performance. The CLB comprises eight 6-input lookup tables (LUTs), each offering dual independent outputs. It includes features like fast adders with carry chains and programmable registers, ensuring computational versatility. The BRAM component supports 36Kb dual-port memory, adaptable as 18Kb split memory configurations. The DSP tile incorporates an 18×20 multiplier with a 64-bit accumulator, supporting complex mathematical processing. Rapid Silicon's Vega eFPGA is optimized for scalability, providing flexibility in tile configurations to meet varied application requirements. It ensures ample compatibility with existing systems through seamless SoC integration, proprietary Raptor EDA tools, and robust IP libraries. These capabilities enable Vega to offer bespoke solutions tailored to specific end-user needs.