All IPs > Network on Chip
Network on Chip (NoC) semiconductor IP is a pivotal element in the design and development of highly integrated electronic systems and chips. As devices become more complex and contain multiple processing units, effective communication through reliable interconnections is crucial. NoC IPs provide a scalable and efficient way to connect various intellectual properties (IPs) within a system on chip (SoC), enabling improved data transfer, performance, and power efficiency.
In modern multicore processor architectures, the traditional bus-based communication faces challenges with scalability, latency, and energy consumption. NoC IPs address these issues by offering packet-based communication paradigms, which are structured like networks to efficiently manage data flow between cores, memory controllers, and peripheral interfaces. This technology is vital for a range of applications including data centers, mobile processors, automotive systems, and beyond. It not only helps in breaking the bandwidth bottleneck but also enhances the overall performance of the system.
A detailed exploration of the Network on Chip category reveals various types of IPs designed to cater to different specific needs, including low-latency networks, high-bandwidth connections, and power-conserving interfaces. Developers and designers can choose from pre-verified solutions by leading vendors, ensuring reliability and reducing time to market. Functionalities offered by these IP solutions might include advanced routing algorithms, traffic prioritization, security features, and error correction mechanisms.
Furthermore, semiconductor IPs in the Network on Chip category are continuously evolving to support emerging technologies such as AI, IoT, and 5G. This makes NoC IPs not only a fundamental infrastructure element but also a key enabler of future technological advancements. Companies seeking to develop state-of-the-art, fully integrated SoCs will find the NoC IP category indispensable in constructing efficient and robust systems capable of meeting current and future demands.
SkyeChip's Coherent Network-on-Chip (NOC) is an innovative, scalable solution designed to support memory coherent systems. Engineered to decrease routing congestion in many-core systems, it effectively utilizes nodes like ACE4, ACE5, and CHI protocols. Operating efficiently at frequencies up to 2GHz, it complements SkyeChip’s Non-Coherent NOC for integrated and partitioned interconnect systems. The solution’s focus on reducing silicon usage makes it a prime candidate for applications where performance and area efficiency are paramount, ensuring seamless system integration with high coherency requirements.
The OPENEDGES Network on Chip (NoC) Bus Interconnect, OIC, is a high-performance solution designed to boost system-on-chip (SoC) design flexibility and efficiency. Leveraging the company's cutting-edge HyperPath technology, it offers double performance gains with extremely low latency, ensuring accelerated communication pathways within complex digital systems. Its ActiveQoS feature manages bandwidth and latency dynamically across the memory subsystem, enhancing the efficient transfer of signals within large and intricate systems. This is paired with asynchronous bridge technology, which resolves long-distance and narrow topology challenges in design, maintaining fidelity and high throughput. Engineered for low power operation, it uses advanced clocking methods to reduce idle power extensively. Given its automated end-to-end RTL generation and simplified SoC design capabilities, the NoC Bus Interconnect from OPENEDGES stands out as an optimal backbone solution for modern computing platforms requiring robust and efficient interconnections.
The Non-Coherent Network-on-Chip (NOC) by SkyeChip is designed to optimize bandwidth and latency for various ICs, focusing on reducing power and area needs while enhancing performance metrics. The solution supports a multitude of protocols such as AXI4, AXI5, and APB, thereby providing excellent routing and operation flexibility. It handles operating frequencies up to 2GHz, providing a robust platform for efficient IC interconnections. Its architecture supports both source synchronous and synchronous clocking models, making it suitable for high-frequency applications, while integrating seamlessly with SkyeChip's Coherent NOC.
Truechip's NoC Crossbar Silicon IP is designed to facilitate the connection of multiple devices supporting various protocol buses. By implementing a crossbar network, this IP seamlessly reduces latency and power consumption while maintaining low area usage in a design. It effectively enhances hardware and software cache coherency and significantly reduces the need for interconnecting wires, hence conserving chip resources. The NoC Crossbar Silicon IP is available in a native Verilog RTL, ensuring clean linting, synthesis, CDC, and RDC processes. Truechip backs its IP with thorough verification by an expert team utilizing comprehensive regression test suites. Consistency in interface, installation, operational procedures, and documentation ensures a smooth integration between the IP and existing systems. The IP provides ease of use through a GUI-based integration and configuration tool, backed by reliable 24X5 customer support. It supports multiple levels of interconnection with several master and slave ports, allowing for highly customizable configurations. Various protocols can be supported across individual ports, and data-width can vary to meet specific design requirements. Features like QoS support, back-to-back transfers, and different phase-shifted frequencies further bolster its performance in a network-on-chip design.
Eliyan’s NuLink technology revolutionizes die-to-die connections in the semiconductor landscape by delivering robust performance and energy efficiency using industry-standard packaging. The NuLink PHY is designed to optimize serial high-speed die-to-die links, accommodating custom and standard interconnect schemes like UCIe and BoW. It achieves significant benchmarks in terms of power efficiency, bandwidth, and scalability, providing the same benefits typical of advanced packaging techniques but within a standard packaging framework. This versatility enables broader cost-effective solutions by circumventing the high cost and complexity often associated with silicon interposers. NuLink Die-to-Die PHY stands out for its integration flexibility, supporting both silicon and organic substrate environments while maintaining superior data throughput and minimal latency. This innovation is particularly beneficial for system architects aiming to maximize performance within chiplet-based architectures, allowing the strategic incorporation of elements such as high-bandwidth memory and silicon photonics. NuLink further advances system integration by enabling simultaneous bidirectional signaling (SBD), doubling the effective data bandwidth on the same interface line. This singular feature is pivotal for intensive processing applications like AI and machine learning, where robust and rapid data interchange is critical. Eliyan’s NuLink can be implemented in diverse application scenarios, showcasing its ability to manage large-scale, multi-die integrations without the customary bottlenecks of area and mechanical structure. By leading system designs away from vendor-specific, cost-prohibitive supply chains, Eliyan empowers designers with increased freedom and efficiency, further underpinning its groundbreaking role in die-to-die connectivity and beyond.
The HUMMINGBIRD by Lightelligence is an innovative optical Network-on-Chip processor that integrates photonic and electronic dies through advanced vertically stacked packaging technologies. This architecture provides a pathway to overcome conventional digital network limitations, particularly the 'memory wall.' With a 64-core domain-specific AI processor, HUMMINGBIRD uses a cutting-edge waveguide system to propagate light-speed signals, drastically reducing latency and power requirements compared to traditional electronic networks. This high-performance device serves as the communication backbone for data centers, facilitating data management and interconnect topology innovations. HUMMINGBIRD exploits the power of silicon photonics to offer a dense all-to-all data broadcast network that enhances the performance and scalability of AI workloads. HUMMINGBIRD's robust integration into PCIe form factors allows easy deployment onto industry-standard servers, and when paired with the Lightelligence Software Development Kit, it can significantly optimize AI and machine learning processes. This integration fosters a higher utilization of computing power and alleviates complexities associated with mapping workloads to hardware.
Xinglian-500 serves as an advanced interconnect fabric IP, supporting coherency across multi-core CPU and SoC designs. This product ensures memory consistency through its network-on-chip (NoC) architecture, facilitating the connection of multiple CPU clusters, IO devices, and DDR, all within the confines of an SoC. This feature is crucial for maintaining synchronization across multiple processing units, thereby enhancing the scalability and performance of complex systems.
The nxFeed Market Data System leverages FPGA technology to deliver ultra-low latency market data handling. It serves as a comprehensive feed handler that decodes, normalizes, and builds order books with ease, significantly reducing processing resources and latency. The system provides a straightforward API, allowing seamless integration with existing trading algorithms or new in-house developments. By deploying on FPGA-based NICs, nxFeed minimizes network load and accelerates data throughput, enabling rapid algorithmic decision-making. Its design simplifies market data application development, making it a vital tool for traders requiring fast and efficient data processing at volatile exchange feeds.
The Bluetooth LE Audio Solutions by Packetcraft is a comprehensive package designed to simplify the transition to Bluetooth LE audio technologies. The solution comes pre-integrated and optimized with host and controller software, including the LC3 audio codec. This offering is tailored to port easily to popular chipsets, giving product developers the flexibility needed to quickly adapt to new technologies. The Bluetooth LE Audio Solutions include support for streamlining Auracast broadcast functionalities and True Wireless Stereo (TWS) audio. Packetcraft's package is particularly focused on providing a convenient pathway for incorporating cutting-edge audio technology with minimal development friction. This is essential for companies looking to enhance their products with state-of-the-art audio capabilities, ensuring a competitive edge in the rapidly evolving audio market. Beyond mere integration, Packetcraft's solution ensures that developers gain access to a suite of tools and resources for effortless implementation, including thorough support during product development. The software stack is designed to accommodate the latest Bluetooth specifications, cementing its place as an essential tool for engineers focused on audio innovation.
Extoll’s Network on Chip (NOC-X) technology is intricately designed to optimize on-chip data routing, facilitating high-performance communication and processing capabilities within semiconductor devices. This IP solution is essential for developers seeking to create dynamic, scalable microarchitectures that demand efficient data traffic management. NOC-X is crafted to align with the needs of complex SoC designs, ensuring seamless data flow and reduced bottlenecks. NOC-X demonstrates remarkable efficiency in handling diverse data loads, making it suitable for a wide range of applications, including high-performance computing and advanced communication technologies. It integrates efficiently with Extoll's suite of IPs, ensuring compatibility and performance enhancements across devices. The technology is compatible with modern process nodes from 12nm to 28nm, showcasing its adaptability and relevance in contemporary semiconductor design. With its robust architecture and scalability, NOC-X aids in achieving superior system performance and reliability, enabling developers to push the boundaries of their chip designs. Extoll provides robust support and documentation for integrating NOC-X into your systems, reflecting their commitment to facilitating innovation through powerful interconnect solutions.
The NoC Mesh Silicon IP by Truechip serves as a pivotal tool for designing efficient on-chip networks. This IP allows chip designers to connect multiple bus protocol-compliant devices with a focus on latency reduction, power efficiency, and area conservation. Its sophisticated architecture supports hardware cache coherency and provides a framework for effective inter-device communication, minimizing the physical resources required. Truechip offers this IP in native Verilog (RTL), ensuring thorough validation with features like 100% code coverage and regression testing by industry experts. This consistency in operations and documentation is present across all Truechip IPs, highlighting their commitment to quality and user satisfaction. The GUI-based integration simplifies the configuration process, enabling designers to tailor the network according to unique project needs with the additional support of 24X5 customer service. The mesh architecture supports complex connectivity with a robust routing algorithm, ensuring efficient data traversal and deadlock avoidance. Each node within the mesh can handle multiple simultaneous transactions, and features like node storage capacity configuration, memory maps, and varied protocol support per port add to its versatility. QoS support, configurable data channels, and flexible operation modes aim to provide comprehensive solutions for advanced network-on-chip applications.
The upgraded JH7110 model enhances upon its predecessor by offering improved graphical and AI processing capabilities. With a quad-core processor and integrated GPU, it supports a wide range of high-speed interfaces, making it ideal for modern AI and multimedia applications. Its optimized architecture ensures efficient resource management and low power consumption while delivering high performance.
FlexNoC Interconnect is designed to enhance the performance of system-on-chip (SoC) designs by optimizing the internal communication networks within the chip. This network-on-chip (NoC) solution stands out due to its physical awareness capabilities, drastically reducing turnaround time for timing closure compared to manual methods. By utilizing integrated automation and sophisticated tools, FlexNoC facilitates efficient place and route processes while minimizing interconnect area, thus improving both power consumption and overall system performance. It strikes a balance between high performance and low power consumption by supporting various architectures such as source-synchronous communications and virtual channels for efficient data transport across large SoCs. FlexNoC supports a vast array of configurations, including customizable topologies and scalable performance optimization. Its design allows seamless support for multiple protocol standards such as AMBA, with features like quality-of-service (QoS) management, ensuring reliable and efficient data transmission. The comprehensive performance monitoring and debugging capabilities, including trace tools and auto-timing closure assistance, ensure developers can optimize designs with minimal iterations. FlexNoC offers a user-friendly interface that enables engineering teams to concentrate on innovation rather than integration challenges, further reducing time-to-market and enhancing productivity. Particularly beneficial for developers targeting sectors like automotive and enterprise computing, the FlexNoC Interconnect is equipped to handle diverse and dynamic computing requirements. It offers robust security features with firewall interfaces and flexibility for advanced configurations, accommodating emerging technologies with ease. FlexNoC’s capabilities in managing complex routing scenarios make it a preferred choice for enterprises looking to deploy reliable and efficient SoCs with minimal risk and reduced costs.
The Speedster7t FPGAs are designed to handle high-bandwidth workloads, addressing limitations commonly found in traditional FPGAs. Built using TSMC's advanced 7nm FinFET technology, these FPGAs feature an innovative 2D network-on-chip (NoC) that offers a revolutionary approach to data transport across the chip. The NoC architecture connects various interfaces to an extensive number of access points within the FPGA fabric, providing unprecedented ASIC-like performance. The Speedster7t series incorporates machine learning processors, high-bandwidth GDDR6 interfaces, PCI Express Gen5, and 400G Ethernet interfaces, making them ideal for AI and ML workloads. These FPGAs ensure efficient routing of data, significantly reducing congestion compared to traditional methods, and streamlining the design complexity. This capability allows for high-speed interfaces and internal connections that facilitate the handling of massive data volumes, crucial for applications in 5G infrastructure, computational storage, network acceleration, and more. The enhanced performance and bandwidth capabilities are complemented by a robust set of features including multiple high-speed Ethernet lanes, advanced SerDes, and comprehensive memory support, positioning Speedster7t FPGAs as a versatile choice for various high-performance and data-intensive applications.
The JH7100 platform integrates dual-core U74 processors, combining strong computational abilities with efficient power usage. It is tailored for intelligent vision applications, incorporating video processing and AI capabilities due to its integrated Vision DSP and ISP systems. With support for various codecs and low power consumption, the JH7100 platform suits real-time edge computing demands.
Xinglian-700 is an advanced interconnect solution offering high scalability and performance. It's designed to connect up to 256 CPU cores while maintaining memory coherency across the SoC. This IP is particularly valuable for constructing large-scale processing networks that demand efficient and coherent memory systems. Its architecture supports enhanced scalability, making it an ideal choice for high-performance computing environments.
FlexWay Interconnect offers an efficient entry-level network-on-chip (NoC) solution ideal for cost-effective and low-power applications such as Internet-of-Things (IoT) edge devices and microcontrollers. It integrates seamlessly with Arteris’ suite of NoC technologies to provide a coherent and dynamic communication backbone for small to medium-scale SoC designs. The platform prioritizes power efficiency and performance, maintaining optimal on-chip data flow through its support for flexible topologies and seamless scaling between simple and more complex designs. This NoC solution is designed to optimize development processes by integrating extensive verification and simulation capabilities, including SystemC and UVM support. Such advancements enable developers to execute efficient mock-ups and debugging, guaranteeing high-quality SoC designs. FlexWay delivers these unique benefits while also supporting multi-protocol configurations and AMBA standards, ensuring interoperability between various IP blocks within the SoC. FlexWay's innovative architectural approach simplifies the handling of power management with features such as unit-level clock gating. It significantly reduces power consumption while conserving silicon area, making it ideal for edge devices where resource efficiency is crucial. FlexWay's automation tools ensure reduced time to market by streamlining the development pipeline, facilitating seamless hardware-software interaction, and maintaining design consistency through its flexible GUI.
ORBIT Memory Subsystem is a state-of-the-art memory solution by OPENEDGES, integrating sophisticated interconnect, memory controller, and PHY IPs designed to deliver superior performance and system efficiency. It's crafted to support the demands of next-generation AI chips, offering capabilities like reduced latency, high bandwidth, and multiple DRAM protocol support. This subsystem ensures excellent synergy between its components through a design that balances bandwidth and latency dynamically, improving the SoC's overall performance and reliability. It incorporates ActiveQoS technology, which finely tunes these parameters to prioritize latency-sensitive tasks, thereby avoiding potential congestion and ensuring smooth data flow. ORBIT's innovation lies in its ability to scale and adapt to emerging DRAM technologies quickly, which expands its application range and extends product cycles. This memory subsystem is especially suitable for industries requiring robust and adaptable memory solutions, such as AI markets, enabling versatile deployments and enhanced application competitiveness.
Magillem 5 Registers addresses hardware/software interface challenges by offering a streamlined solution for register management within large-scale SoCs. Utilizing the IP-XACT standard approach, it enables efficient register design across hardware, software, verification, and documentation domains. Magillem 5 Registers automates the development process, reducing time to market significantly by ensuring the correct and consistent generation of system memory maps and associated documentation. A single-source environment allows for compiling and managing registers and memory maps, ensuring synchronization across design teams. This automation minimizes human error, maintaining data integrity and consistency through the lifecycle of the SoC project. The support for various output formats, including RTL, firmware, and verification environments such as UVM, allows seamless integration with existing workflows, fostering collaboration between hardware and software teams. The tool's advanced feature set includes customizable generators, import capabilities from diverse data formats, and extensive error-checking mechanisms. These features ensure precise design architecture with minimal iterations and rework, enhancing the efficiency and accuracy of SoC projects. Magillem 5 Registers is particularly beneficial for projects involving complex memory configurations, helping teams achieve high-level productivity and performance.
The SoC Platform offered by SEMIFIVE is an advanced solution for rapid and efficient SoC development, utilizing silicon-proven IPs and optimized design methodologies. This platform is tailored for key applications, ensuring lower costs, reduced risks, and quicker time-to-market. It leverages a domain-specific architecture, a pre-configured IP pool, and brings up hardware and software quickly, catering to AI Inference, AIoT, and HPC scenarios. The platform facilitates significant cost savings in prototyping NRE expenses and design implementation, providing a reduction of up to 50% compared to industry norms. By utilizing SEMIFIVE's infrastructure and methodology, it accelerates time-to-market, achieving faster design and verification cycles than the industry average. Moreover, it minimizes engineering risks by using a pre-verified platform IP pool and silicon-proven SoC design components. Notably, the platform supports various engagement models. These models range from the Max Efficiency Model, which uses a competitive and comprehensive platform IPs architecture, to the Max Flexibility Model, allowing configuration changes for third-party IPs. These flexible solutions maximize customer IP integration, providing an optimal system tailored to specific needs.
Magillem Connectivity is a comprehensive solution designed to streamline and simplify the complex process of system-on-chip (SoC) integration, enhancing productivity and reducing time-to-market for large-scale and intricate designs. It automates the integration of IP blocks into SoC architectures, facilitating automatic instantiation and validation of design connectivity. This tool provides a user-friendly interface tailored for large designs, enabling efficient management of tens of thousands of instances. Designed to leverage the IP-XACT industry standard, Magillem Connectivity ensures effective IP packaging and seamless configurability across design platforms. The tool's dynamic API access allows for automatic IP instantiation and error-free connections, reducing manual intervention and potential design errors. It aligns memory and connectivity information in real-time, helping teams maintain consistency and leverage accurate design data throughout the integration process. By automating redundant and error-prone tasks, Magillem Connectivity significantly enhances productivity, facilitating rapid iteration cycles and debug runs. The system supports RTL restructuring by separating RTL and physical hierarchies, simplifying floorplanning, and permitting robust system design adjustments. With robust error-checking and built-in integrity validations, this solution ensures high-quality design flows, addressing the needs for scalability and flexibility in advanced SoC development projects.
CSRCompiler is a critical component in creating robust hardware/software interfaces, serving as the foundation for innovative design methodologies. By utilizing a unified specification format, the CSRCompiler platform creates a streamline for designing registers that supports hardware, software, and verification across the SoC lifecycle. This approach minimizes discrepancies and ensures data consistency and accuracy across all design stages, significantly boosting the quality and efficiency of register coding processes. The CSRCompiler uses the CSRSpec language to automate the generation of RTL, verification environments, firmware, and documentation, enabling rapid adaptation to design changes. This flexibility reduces development overhead and promotes a clean, error-free import of third-party IPs or legacy data, crucial in maintaining design integrity and reducing risk in SoC projects. Offering comprehensive support for industry-standard buses and providing extensive error/syntax checking, CSRCompiler enhances productivity, allowing teams to identify and resolve issues early in the design phase. With the capacity to manage millions of registers, it stands out as a high-capacity, high-efficiency tool necessary for contemporary large-scale SoC implementations, driving innovation and ensuring seamless integration across design and operational environments.
5G ORAN Base Station is designed to transition smoothly from 4G to 5G, with a focus on delivering exceptional connectivity and performance. This solution is rooted in domain knowledge and emerging technology trends, investing heavily in foundational 5G elements including Base Station, Core Network, and Radio Access Network (RAN). Faststream supports this with extensive lab setups for IP development, catering to both strategic and private investors eyeing the Open RAN landscape. Open RAN leverages open standards, fostering compatibility across various hardware and software ecosystems in the wireless domain. This architecture allows for freedom from vendor dependency, making room for innovations beyond traditional providers. By integrating hardware and software from diverse vendors, Open RAN enhances market competition and, as a result, can significantly reduce operational costs for mobile network providers. The infrastructure involves macrocell components implementing technologies like MIMO, engineered for large-scale device connection while minimizing latency. The Central Unit (CU) aggregates upper layer protocols across multiple Distributed Units (DUs), allowing vast capacity networks using FPGAs and synchronized components. These features, alongside advanced DSL-based amplifiers, establish the 5G ORAN Base Station as a cornerstone in advanced telecom infrastructure.
Harmony Trace is a ground-breaking tool aimed at providing comprehensive traceability and quality management throughout the semiconductor design process. It integrates design artifacts to create a seamless traceability matrix, crucial for certification in functional safety applications. The framework is equipped to support complex system-on-chip (SoC) endeavors by ensuring that every element of the design is comprehensively linked, monitored, and validated across its full lifecycle. This tool enhances system quality by enabling transparent linkage through the semiconductor development process, aligning with standards like ISO 26262. Harmony Trace’s compatibility with diverse industry tools such as IBM DOORS, Jama Connect, and Atlassian Jira ensures robust cross-domain integration, facilitating efficient collaboration between various systems and design tools. By automating traceability and certification processes, Harmony Trace accelerates compliance and mitigates risks associated with safety-critical designs. It also enables modular reporting and semantic data processing, providing valuable insights and advancements in design quality. This tool makes managing large-scale semiconductor projects more streamlined and efficient, ensuring all design components are accurately tracked and evaluated throughout their development.
Packetcraft offers a sophisticated Channel Sounding technology, an advanced solution for high-accuracy distance measurement and precise location tracking using Bluetooth connectivity. This innovative technology enables tapping into competitive use cases where exact localization and measurement are paramount, making it ideal for sectors like automotive and IoT device networks. Channel Sounding provides an avenue for implementing emerging Bluetooth technologies that demand superior location precision. It capitalizes on measuring the time of flight of Bluetooth signals, thus offering refined metrics for distance determination. The technology is designed to be readily integrated with existing systems, providing developers with the flexibility and capability to elevate their product offerings. Such advancements in Bluetooth technology not only expand the functional capabilities of end products but also streamline their adaptation to modern requirements. Packetcraft's Channel Sounding is also backed by extensive engineering support, enabling more seamless integration into varied product portfolios and meeting the increasing demand for smart and location-aware devices.
The AMBA 5 CHI Verification IP is designed to test the highly sophisticated AMBA 5 Coherent Hub Interface protocol. This protocol is crucial for optimizing data traffic in Network on Chip (NoC) architectures, and the verification IP ensures that data coherency is meticulously maintained across the system. Built with an emphasis on high performance, the AMBA 5 CHI VIP provides engineers with robust testing methodologies for designing next-generation applications. The verification IP supports multiple data ordering models and ensures that data transactions are processed correctly under diverse operating conditions. It is equipped with extensive protocol test coverage, which aids developers in identifying and rectifying potential error points early in the design cycle, thereby reducing time to market. Enhanced reporting features allow seamless monitoring of transaction processes, delivering precise feedback to developers. This tool is valuable for those involved in complex SoC design, where maintaining consistency and synchronization between various processing elements is critical. By ensuring protocol compliance and effective interface operations, the AMBA 5 CHI VIP is a key asset in the semiconductor IP portfolio.