All IPs > Multimedia > AV1
AV1 semiconductor IPs have become a pivotal component in the realm of multimedia processing. As a next-generation video codec developed by the Alliance for Open Media (AOMedia), AV1 is designed to deliver high-quality video experiences at remarkably efficient bitrates. This makes it particularly appealing for applications that demand top-tier video quality without compromising on data transmission efficiency, such as streaming services, video conferencing platforms, and various forms of digital media broadcasting.
In the rapidly evolving tech landscape, the demand for efficient data processing and transmission is paramount. AV1 semiconductor IPs offer an innovative solution by significantly reducing the bandwidth requirements for video streaming. This enables smoother delivery of high-resolution content over constrained networks, making AV1 an attractive choice for content providers aiming to deliver superior user experiences. Additionally, the open-source nature of AV1 allows for widespread adoption and adaptation across various applications and platforms.
Products within this category typically include encoder and decoder IP cores optimized for AV1 video processing. These cores are engineered to handle complex encoding tasks that efficiently compress video data without sacrificing quality, playing a crucial role in enabling high-definition streaming even at lower bitrates. As digital media consumption continues to surge, AV1 semiconductor IPs are expected to play an integral role in supporting the technological backbone necessary for emerging multimedia applications, mobile devices, and smart TVs.
Moreover, as part of a broader ecosystem, AV1 complements existing multimedia systems by providing a scalable and cost-effective solution for next-level video coding. This IP's inclusion in multimedia product offerings bridges the gap between burgeoning consumer demands and the technological requirements of the digital age. Its implementation not only ensures compatibility with modern standards but also provides a future-proof option for developers and manufacturers investing in cutting-edge multimedia solutions.
ISPido is a sophisticated Image Signal Processing Pipeline designed for comprehensive image enhancement tasks. It is ultra-configurable using the AXI4-LITE protocol, supporting integration with processors like RISCV. The ISP Pipeline accommodates procedures such as defective pixel correction, color interpolation using the Malvar-Cutler algorithm, and various statistical adjustments to facilitate adaptive control. Furthermore, ISPido incorporates comprehensive color conversion functionalities, with support for HDR processing and chroma resampling to 4:2:2/4:2:0 formats. Supporting bit depths of 8, 10, or 12 bits, and resolutions up to 7680x7680, ISPido ensures high-resolution output crucial for next-generation image processing needs. This flexibility positions it perfectly for projects ranging from low power devices to ultra-high-definition vision systems. Each component of ISPido aligns with AMBA AXI4 standards, ensuring broad compatibility and modular customization possibilities. Such features make it an ideal choice for heterogeneous electronics ecosystems involving CPUs, GPUs, and specialized processors, further solidifying its practicality for widespread deployment.
The KL720 AI SoC offers an industry-leading performance-to-power ratio of 0.9 TOPS per Watt, rendering it suitable for high-performance applications. It's two to four times more power-efficient than its competitors, making it ideal for devices requiring significant processing capability. The chip facilitates real-time processing of 4K images and supports full HD video and 3D sensing, addressing applications in IP cams, smart TVs, AI glasses, and more, enabling gesture control for gaming and voice recognition.
The JPEG XS Encoder/Decoder from TMC aligns with the evolving demands of high-resolution imagery transmission. As appliances and applications embrace higher throughput requirements, this product stands out for offering visually lossless compression that supports rapid data handling. Particularly useful in scenarios like remote sensing and broadcast transmission, JPEG XS facilitates efficient and quick data transmission without compromising image integrity. With the rise of 5G infrastructure, low-latency compression becomes increasingly critical. JPEG XS addresses these needs by minimizing delay in transmission, making it suitable for interactive applications such as virtual reality and automated driving systems. Moreover, the encoder and decoder pairs are engineered to function with high-speed transmission lines to meet challenging operational requirements. This product supports a variety of color spaces and bit depths, ensuring adaptable integration into existing technological ecosystems. Its reduced need for external memory decreases design complexities, cutting down development time and costs.
The HDR Core is engineered to deliver enhanced dynamic range image processing by amalgamating multiple exposures to preserve image details in both bright and dim environments. It has the ability to support 120dB HDR through the integration of sensors like IMX585 and OV10640, among others. This core applies motion compensation alongside detection algorithms to mitigate ghosting effects in HDR imaging. It operates by effectively combining staggered based, dual conversion gain, and split pixel HDR sensor techniques to achieve realistic image outputs with preserved local contrast. The core adapts through frame-based HDR processing even when used with non-HDR sensors, demonstrating flexibility across various imaging conditions. Tone mapping is utilized within the HDR Core to adjust the high dynamic range image to fit the display capabilities of devices, ensuring color accuracy and local contrast are maintained without introducing noise, even in low light conditions. This makes the core highly valuable in applications where image quality and accuracy are paramount.
The SMS Fully Integrated Gigabit Ethernet & Fibre Channel Transceiver Core is engineered for high-efficiency communication applications requiring robust performance. This core supports IEEE 802.3z compliance for Gigabit Ethernet over fiber and copper media, ensuring seamless integration with existing network infrastructures. Its design emphasizes full duplex operation, facilitated by a 10-bit controller interface for both transmit and receive data paths. A discerning feature of this transceiver core is its precise clock recovery DLL and PLL architecture, crucial for high-speed data alignment and minimizing jitter. This robust clocking mechanism is complemented by high-speed drivers and low jitter PECL outputs, optimizing the core for performance in demanding networking environments. Moreover, the core’s architecture supports advanced features such as programmable receive cable equalization and embedded Bit Error Rate Testing (BER). Its CMOS implementation reduces power consumption and enhances cost-efficiency, ensuring a compact fit in various system architectures.
The Advanced Video Transmission Toolkit (FV-VTT) from FastVDO is a cutting-edge solution designed to simulate video encoding, forward error correction (FEC), transmission channels, and video quality assessment. This toolkit supports popular video standards like H.264, H.265, H.266, and AV1, along with advanced FECs such as Polar, LDPC, and Turbo codes used in Wifi and 5G standards. Incorporating diverse channel models like AWGN, Rayleigh fading, and burst error channels, FV-VTT is a comprehensive package for video transmission analysis. By accurately simulating varying conditions and assessing received video quality, this toolkit aids in the development of robust video transmission systems capable of maintaining fidelity across different environments. FastVDO's toolkit is instrumental for developers and researchers focused on optimizing video communication technologies, offering insights to improve video delivery and quality in real-world applications. This innovative product embodies FastVDO's commitment to advancing multimedia communication standards, providing powerful tools for video engineers.
The AV1 Video Encoder from BLUEDOT enhances performance by supporting high game resolution and frame rate demands. Key for cloud gaming and e-sports streaming, it tackles bandwidth challenges with low-latency encoding, maintaining high video quality. Developed using semiconductor design insights, this encoder is delivered as a cloud-based service, offering a cost-effective encoding solution for large-scale platforms.
HEVC/H.265 Main/Main10/ Main Still Picture Profile @L5.2 AVC/H.264 BP/CBP/MP/HP/HP10 @L5.2 Capable of encoding up to 8K ((8192x4096) A 32-bit AMBA3 APB bus for host CPU system control 128-bit AMBA3 AXI for data transfer (Optionally, additional secondary AXI) Latency tolerance Low power consumption Programmability Configurable IP Multi-instances Frame buffer compression (CFrame) Rotation & Mirroring Bit-depth & chroma sub-sample conversion Background detection 3DNR Lambda table QP Map Custom mode decision, etc.
HEVC/H.265 - Main/Main10 Profile @L5.1 AVC/H.264 - BP/CBP/MP/HP/HP10 Profile @ L5.2 Capable of decoding up to 4K60fps (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Secondary AXI interfaces Downscaler (on-the-fly mode)
The H.264 Encoder by VISENGI is a cutting-edge solution designed to deliver top-notch video compression. It boasts the highest pixel throughput in the industry, enabling UltraHD 4K 60 capabilities on low-range FPGAs and even 8K 30 on mid-range FPGAs like Arria 10 and Zynq. This encoder uses a unique single-engine design to maintain minimal latency, outperforming multi-engine alternatives. There are two variants available: H264E-I, a compact version for applications requiring minimal external memory and lighter compression, and H264E-P, which provides superior compression for more substantial needs. Both versions ensure a processing speed of over 5.2 pixels encoded per cycle, demonstrating high efficiency and throughput across various resolution demands. Another highlight is its versatile resolution support, allowing for continuous adaptation from low to high resolutions—ranging from QVGA to 8K—within the same IP core. This flexibility coupled with comprehensive real-time control options makes it ideal for dynamic and demanding scenarios. Designed for straightforward integration, the encoder uses AXI interfaces and supports a wide range of I/O configurations enhancing its adaptability in multiple environments.
VISENGI’s H.264 Decoder IP core is designed to complement their H.264 Encoder, ensuring optimal performance and compatibility. It supports multiple profiles including the High 4:4:4 Predictive Profile, which matches the encoding specifications. The decoder achieves a high throughput and maintains low latency, keeping up with the high performance of the encoder. The architecture is scalable, allowing for multiple stream decoding in parallel, which offers flexibility in balancing size, latency, and pixel throughput. The core is not a general-purpose decoder but is crafted to work seamlessly with VISENGI's specific encoder profiles, enhancing performance and reducing latency substantially. With embedded DMA engines for direct memory connections and support for high-latency memories, the interface design is aligned with industry standards, notably the AXI interfaces. The inclusion of motion compensation capabilities further improves efficiency, especially when used in conjunction with VISENGI's advanced encoder variants.
MPEG-H Audio System is a cutting-edge audio technology designed for the immersive experiences of modern television and virtual reality platforms. Recognized as a groundbreaking audio system, Fraunhofer IIS developed it to provide an interactive and enveloping audio environment, transforming the way viewers and gamers experience sound in multimedia contexts. Tailored for the demands of both VR and broadcast TV, the system supports a comprehensive 3D sound experience that makes use of state-of-the-art audio encoding. At its core, MPEG-H Audio System allows users to position sound elements freely in a three-dimensional space, enabling an unprecedented level of realism. Whether it's the dramatic soundscapes in film or the all-encompassing audio required for virtual reality games, MPEG-H offers flexibility and precision that cater to a wide audience ranging from everyday users to professional creators. The audio system’s compatibility with the next generation TV standards and its adaptability to various playback environments make it particularly advantageous. Its design seamlessly integrates into existing deployment frameworks, providing dynamic and rich audio experiences without the complexity of previous systems. As such, MPEG-H Audio is poised to redefine the standards of digital audio, making its impact felt across entertainment and content production industries worldwide.
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
VISENGI's 2D DCT Core provides efficient two-dimensional discrete cosine transform capabilities, crucial for a variety of data compression processes including image and video compression. This core boasts a fully parallelized design with pipelining, enabling high-throughput processing suitable for real-time applications. Operating over 8x8 blocks of pixels, the 2D DCT Core efficiently transforms spatial data into frequency components, which are easier to compress. The modular design supports different input/output bit widths and the capability to run multiple operations concurrently, allowing adaptation based on specific application needs. This versatility is underscored by its efficient use of resources, making it suitable for deployment in FPGAs or ASICs with varying capacity. Seamlessly integrating into systems that require robust image and video processing capabilities, the core's customizable parameters ensure broad applicability and consistent performance.
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding Down-scaler (On-the-fly mode) MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard AV1: Main profile @ L6 Main tier 50Mbps HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L5.1 HEVC: Main/Main10 profile, Main/Main 10 Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L5.2 (Interlaced coding tools are not supported) Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard AV1: Main profile @ L5.1 Main tier 50Mbps HEVC/H.265: Main/Main 10 profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L5.2 (Interlaced coding tools are not supported.) VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported) Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard AV1: Main profile @ L6 High tier HEVC/H.265: Main/Main10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Decoding/Encoding Tools Support Extended Sequential ISO/IEC 10918-1 JPEG compliance Support one or three color components Three components in a scan (interleaved only) 8-bit and 12-bit samples for each component Support 4:2:0, 4:2:2, 4:4:0, 4:4:4 and 4:0:0 color formats Max. six 8x8 blocks in one MCU Support NV12/NV16/NV24 (CbCr Interleaved), NV21/NV61/NV42 (CrCb Interleaved) Support from 16 x 16 to 32K x 32K (32,768 x 32,768) image size Packed mode is supported 12-bit PPM format is supported Value-added Features Partial mode for encoding and decoding On-the-fly rotator/mirror ROI(Region of Interest) for decoding On-the-fly downsampler for decoding Color format converting for decoding Performance Decode up to 290M pix/s for 4:2:0 color format Encode up to 290M pix/s for 4:2:0 color format Operating clock frequency: 200MHz Ease of integration AMBA 32-bit APB (w/ PREADY) interface for communication with a host processor AMBA 64-bit AXI interface for the external memory
Brief specification HEVC/H.265 Main/Main10 Profile @L5.1 AV1 Main Profile @ L5.1 VP9 Profile 0/ Profile 2 @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 System I/F A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/additional Secondary AXI) Burst Write Back (BWB) Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance
Supported standards for Decoder ISO/IEC23008-2 HEVC/H.265, ITU-T Rec. H.265 Main/Main10 Profile L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 AVS2 Main/Main10 Profile @L8.0.60 Main performance 4K(3840x2160) 60fps @ 450MHz Max. resolution: 8192x4096 Features Frame buffer compression (CFrame) Embedded Post-processing (w/Down-scaler) Low delay Low power consumption Latency tolerance Interface AMBA 32-bit APB interface for Host CPU AMBA 128-bit AXI interface for the external memory
HEVC/H.265 Main/Main10 Profile @L5.1 AVC/H.264 BP/CBP/MP/HP/HP10 Profile @ L5.2 VP9 Profile 0/Profile 2 (HBD) AVS2 Main10 Profile @L8.0.60 Capable of decoding up to 4Kp60 (8192x4096) A 32-bit APB bus and 128-bit AMBA3 AXI buses (w/ additional secondary AXI) Burst Write Back Map converter Low delay Low power consumption Configurable IP Latency tolerance Programmability Multi-instances Frame buffer compression (CFrame) Downscaler (on-the-fly mode)
Video Codec Standard AV1: Main Profile @ L5.1 Performance 4K60fps@500MHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer * Optional AXI can be used to alleviate bandwidth usage
Video Codec Standard AV1: Main/High profile @ L6 Main tier 50Mbps Professional profile except 12-bit @ L6 Main tier 50Mbps Mono/YUV420/YUV422/YUV444 8-/10-bit HEVC/H.265: Main/Main 10/Main 4:2:2 10 profile @ L6 High tier Main 4:4:4/Main 4:4:4 10 profile @ L6 High tier (Only support 4:2:0 coding tools, high precision weighted prediction, and chroma QP offset list) AVC/H.264: Baseline/Constrained Baseline/Main/High/High10 profile @ L6 High 10 Intra/High 4:2:2/High 4:2:2 Intra profile with frame_mbs_only_flag = 1 @ L6 High 4:4:4 Predictive/High 4:4:4 Intra/CAVLC 4:4:4 Intra profile @ L6 with: frame_mbs_only_flag = 1 bit_depth_luma ≤ 10 bit_depth_chroma ≤ 10 frame_mbs_only_flag = 1 and qpprime_y_zero_transform_bypass_flag = 0 VP9 (Decoder only): Profile 0 and Profile 2 (12-bit not supported), YUV420 8/10-bit Performance 4K120fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Rotate/Mirror Down-scaler Crop Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, and Sorenson decoder HW IP for 2Kp60, 4:2:0 Standards AVC/H.264 BP/CBP/MP/HP L.4.1 Max: 1920x1088; Min: 16x16 MVC SHP L.4.1 Max: 1920x1088; Min: 16x16 MPEG-4 SP/ASP L.5 Max: 1920x1088; Min: 16x16 H.263 Profile 3 Max: 1920x1088; Min: 16x16 VC-1 SP/MP/AP L.3 Max: 1920x1088 or 2048x1024 Min: 16x16 MPEG-1/2 MP L.high Max: 1920x1088; Min: 16x16 Sorenson Spark Max: 1920x1088; Min: 16x16 VP8 WebM/WebP Max: 1920x1088; Min: 16x16 Theora Max: 1920x1088; Min: 16x16 AVS Jizhun/Guangdian L6.2 Max: 1920x1088; Min: 16x16 Features Frame buffer compression (CFrame) Low delay decoding Configurable IP Programmability Low power consumption Frame-based processing Multi-instances Latency tolerance Burst Write Back Down-scaler (on-the-fly mode) Map converter MPEG-2/4 De-ringing Built-in de-blocking filter A 32-bit AMBA3 APB bus and 64-bit AMBA3 AXI buses (w/additional Secondary AXI buses)
Video Codec Standard HEVC: Main/Main10 profile @ L6 High tier AVC: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 (Interlaced coding tools are not supported) Performance 4K120fps@500MHz or 8K60fps@1GHz Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture encoding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer *Optional AXI can be used to alleviate bandwidth usage
H.264, MVC, VP8, MPEG-1/2/4, VC-1, AVS, AVS+, H.263, Sorenson Decoding and encoding support at 1080p 60fps Supported standards for Decoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP,ASP@L6 SMPTE 421M-2006 VC-1 SP/MP/AP@L3 ISO/IEC 13818-2 MPEG-2 MP@HL ITU-T H.263(Annex I,J,K,T) AVS Jizhun @L6.2 AVS+ Guangdian @L6.2 On2 VP8 Sorenson Spark Theora Supported standards for Encoder ISO/IEC 14496-10 AVC/H.264 BP/MP/HP@L4.2 ISO/IEC 14496-10/5 MVC Stereo High Profile@L4.1 ISO/IEC 14496-2 MPEG-4 SP@L6 ITU-T H.263(Annex J,K,T) Supported Max. Resolution Supports up to 2048x2048 resolution Performance Single-stream H.264 HD(1920x1080p) 30fps decoding at <133MHz core clock H.264 HD(1920x1080p) 60fps decoding at <266MHz core clock H.264 HD(1920x1080p) 30fps encoding at <133MHz core clock H.264 HD(1920x1080p) 60fps encoding at <266MHz core clock Multi-stream Dual H.264 HD(1920x1080p) 30fps decoding at <266MHz core clock Dual H.264 HD(1920x1080p) 30fps encoding at <266MHz core clock 6SD/D1(NTSC&PAL) 30fps decoding at <133MHz core clock Full HD(1080p) encoding and decoding at <266MHz core clock Encoding Tools Selective [+/-64,+/-48] Quarter-pel and half-pel accuracy motion estimation using a full- search algorithm Flexible bit-rate control CBR VBR Fixed QP CABAC/CAVLC for AVC/H.264 Built-in pre- rotation/mirroring function 90xn degree rotation Vertical/horizontal mirroring Decoding Tools CABAC/CAVLC for AVC/H.264 MPEG-4 AC/DC prediction AVC/H.264 intra-prediction In-loop deblocking filter for H.264, H.263, and AVS Overlapped smoothing filter for VC-1 Built-in post-processing function 90xn degree rotation Vertical/horizontal mirroring De-ringing De-blocking filter for MPEG-2/4 Interface AMBA 32-bit APB interface for Host CPU AMBA 64-bit AXI interface for the external memory
High-resolution Image Processing IP Performance 4K60p@400MHz (600MHz for display interface) Features Support various color format : YUV420, YUV422, YUV444, and RGB Up-/Down-scaler x1/8~x8 : selectable scaler algorithm with Bi-cubic and Lanczos Two scalers, connected to DRAM and display/direct I/F respectively, operating at different ratios at the same time (configurable to one scaler option) Color space conversion : YUV2RGB and RGB2YUV, coefficient downloadable Optional features Crop and digital zoom : scaling on cropped region Flip : horizontal and vertical 3rd Party interfaces: such as AFBC v1.2 and PVRIC v4 (support output only) Interface Display Interface : 3 channels for components with vertical/horizontal sync signal (ITU-R BT.601 compatible) Direct Interface (optional feature) : On-the-fly interface based on ready-valid protocol Support CF10 (Chips&Media’s Frame buffer compression) for Chips&Media video codec Support AFBC v1.2 and PVRIC v4 (optional feature) for output of MAPI
Video Codec Standard HEVC/H.265: Main profile @ L5.1 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High profile @ L5.2 Performance 4K60fps@500MHz with a single-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (Optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC/H.265: Main/Main 10 profile @ L6 High tier AVC/H.264: Baseline/Constrained Baseline/Main/High/High 10 profile @ L6 Performance 4K120fps@500MHz or 8K30fps@500MHz with a dual-core 4K240fps@1GHz or 8K60fps@1GHz with a dual-core Max resolution: 8192 x 8192 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Frame buffer compression (FBC) Multi-instances 3rd Party I/F Bit-depth and YUV format conversion of the source picture Encoder Features I/P/B picture coding Picture/Block level of rate control ROI coding Background coding Interface AMBA3 32-bit APB I/F for host I/F AMBA3 128-bit AXI for data transfer (optional AXI can be used to alleviate bandwidth usage.)
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-/10-bit depth Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding MapConverter 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
Video Codec Standard HEVC: Main/Main Still Picture profile @ L5.1 High tier AVC: Baseline/Constrained Baseline/Main/High profiles @ L5.2 Performance 4K60fps@500MHz Max resolution: 8192 x 4096 Min resolution: 256 x 128 Bit depth: 8-bit Features Multi-instances Frame-buffer compression (CFrame) In-loop filter Rotation & Mirroring Bit depth & chroma sample format conversion Lossless coding Background coding 3DNR, etc. Interface 32-bit AMBA3 APB bus 128-bit AMBA3 AXI buses Primary AXI interface and an optional secondary AXI interface
The TM7606/7 Series offers a high-performance video transmission solution, ideal for applications requiring dual-channel video streaming over standard internet or mobile networks. Distinguished by its low-latency functionality, this system ensures video transmission is smooth and effective, even in challenging conditions. Notably, it incorporates visibility enhancement and SRT features, optimizing remote operation and monitoring tasks. The design supports various input and output configurations, catering to specific needs with both HDMI and SDI options. Its compact size and lightweight nature make it easy to transport, effectively minimizing the constraints of space and logistics. Furthermore, the encoder's ability to handle dual-channel 3G-SDI inputs exemplifies its high adaptability and capacity for simultaneous processing. TMC's original codec enhances data security by preventing unauthorized access to transmitted data, which is crucial in professional workflows. The automatic rate control and preset functions contribute to its user-friendly design, making adjustments in transmission settings convenient and efficient.
Foresys Financial Management System 2.0 is designed to streamline and optimize the advertising and campaign management processes for financial institutions. It facilitates pre-campaign planning, monitoring, and optimization of advertising effectiveness through detailed analysis and reporting features. This solution is tailored to ensure maximum advertising efficiency, transforming campaign strategies into actionable insights. The system integrates seamlessly into existing business infrastructures, providing real-time data on campaign performance and allowing marketers to make timely adjustments for better outcomes. Its robust analytics engine supports comprehensive evaluation of marketing efforts, contributing to improved ROI and strategic planning. Furthermore, this system is equipped with user-friendly dashboards that offer an intuitive overview of campaigns, enabling decision-makers to derive insightful conclusions quickly. It supports a broad spectrum of marketing channels, ensuring organizations can reach their target audiences effectively and promptly increase their brand visibility.
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