All IPs > Multimedia
In the rapidly evolving world of semiconductors, multimedia semiconductor IPs play a crucial role in enabling and enhancing digital media experiences across various electronic devices. This category encompasses a broad range of intellectual properties tailored for multimedia processing, from audio and video codecs to graphical interfaces, essential for consumer electronics, mobile devices, broadcasting equipment, and more. As technology advances, so too do the demands for higher performance, better quality, and increased efficiency in multimedia signal processing.
This category is home to subcategories that feature cutting-edge technologies and industry standards in multimedia processing. 2D and 3D rendering IPs lead the visual innovation charge, offering essential tools for developing immersive user interfaces and gaming experiences. Advanced audio interfaces, including ADPCM and WMA IPs, provide high-quality sound reproduction and compression, essential for both professional audio systems and consumer devices.
One of the highlights of the multimedia IP category is video compression technology. Standards like H.264, H.265, and the new H.266 are crucial for streaming services, broadcasting, and digital video recorders, offering solutions that reduce data rates while maintaining video quality. Image processing IPs including JPEG, JPEG 2000, and MPEG standards, ensure efficient image storage and retrieval, vital for digital cameras and web applications.
Additionally, interface IPs such as HDMI, Camera Interface, and MHL provide seamless connectivity, enabling efficient data transfer between devices. With innovations such as AV1 for open-source video coding, and emerging technologies like TICO and MPEG 5 LCEVC, our catalog covers both established and avant-garde solutions for multimedia applications. These semiconductor IPs empower developers and manufacturers to deliver next-generation multimedia experiences, ensuring devices meet the modern consumer's expectations for quality and performance.
Overview: CMOS Image Sensors (CIS) often suffer from base noise, such as Additive White Gaussian Noise (AWGN), which deteriorates image quality in low-light environments. Traditional noise reduction methods include mask filters for still images and temporal noise data accumulation for video streams. However, these methods can lead to ghosting artifacts in sequential images due to inconsistent signal processing. To address this, this IP offers advanced noise reduction techniques and features a specific Anti-ghost Block to minimize ghosting effects. Specifications: Maximum Resolution o Image : 13MP o Video : 13MP@30fps -Input formats : YUV422–8 bits -Output formats o DVP : YUV422-8 bits o AXI : YUV420, YUV422 -8 bits-Interface o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) Features: Base Noise Correction: AWGN reduction for improved image quality Mask Filter: Convolution-based noise reduction for still images Temporal Noise Data Accumulation: Gaussian Distribution-based noise reduction for video streams using 2 frames of images 3D Noise Reduction (3DNR): Sequential image noise reduction with Anti-ghost Block Motion Estimation and Adaptive: Suppresses ghosting artifacts during noise reduction Real-Time Processing: Supports Digital Video Port (DVP) and AXI interfaces for seamless integration Anti-Ghost Real time De-noising output
Overview: Lens distortion is a common issue in cameras, especially with wide-angle or fisheye lenses, causing straight lines to appear curved. Radial distortion, where the image is expanded or reduced radially from the center, is the most prominent type. Failure to correct distortion can lead to issues in digital image analysis. The solution involves mathematically modeling and correcting distortion by estimating parameters that determine the degree of distortion and applying inverse transformations. Automotive systems often require additional image processing features, such as de-warping, for front/rear view cameras. The Lens Distortion Correction H/W IP comprises 3 blocks for coordinate generation, data caching, and interpolation, providing de-warping capabilities for accurate image correction. Specifications: Maximum Resolution: o Image: 8MP (3840x2160) o Video: 8MP @ 60fps Input Formats: YUV422 - 8 bits Output Formats: o AXI: YUV420, YUV422, RGB888 - 8 bits Interface: o ARM® AMBA APB BUS interface for system control o ARM® AMBA AXI interface for data Features: Programmable Window Size and Position Barrel Distortion Correction Support Wide Angle Correction up to 192° De-warping Modes: o Zoom o Tilt o Pan o Rotate o Side-view Programmable Parameters: o Zoom Factor: controls Distance from the Image Plane to the Camera (Sensor)
Overview: RCCC and RCCB in ISP refer to Red and Blue Color Correction Coefficients, respectively. These coefficients are utilized in Image Signal Processing to enhance red and blue color components for accurate color reproduction and balance. They are essential for color correction and calibration to ensure optimal image quality and color accuracy in photography, video recording, and visual displays. The IP is designed to process RCCC pattern data from sensors, where green and blue pixels are substituted by Clear pixel, resulting in Red or Clear (Monochrome) format after demosaicing. It supports real-time processing with Digital Video Port (DVP) format similar to CIS output. RCCB sensors use Clear pixels instead of Green pixels, enhancing sensitivity and image quality in low-light conditions compared to traditional RGB Bayer sensors. LOTUS converts input from RCCB sensors to a pattern resembling RGB Bayer sensors, providing DVP format interface for real-time processing. Features: Maximum Resolution: 8MP (3840h x 2160v) Maximum Input Frame Rate: 30fps Low Power Consumption RCCC/RCCB Pattern demosaicing
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARM® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications: Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps Input Formats: Bayer-8, 10, 12, 14 bits Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features: Defective Pixel Correction: On-The-Fly Defective Pixel Correction 14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5% 2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm Color Correction Matrix: 3x3 Matrix Bayer Gamma Correction: 19 points RGB Gamma Correction: 19 points Color Enhancement: Hue/Sat/∆-L Control for R/G/B/C/M/Y Channels High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting Auto White Balance: Based on R/G/B Feed-Forward Method Auto Focus: 2-Type 6-Region AF Value Return
Overview: Human eyes have a wider dynamic range than CMOS image sensors (CIS), leading to differences in how objects are perceived in images or videos. To address this, CIS and IP algorithms have been developed to express a higher range of brightness. High Dynamic Range (HDR) based on Single Exposure has limitations in recreating the Saturation Region, prompting the development of Wide Dynamic Range (WDR) using Multi Exposure images. The IP supports PWL companding mode or Linear mode to perform WDR. It analyzes the full-image histogram for global tone mapping and maximizes visible contrast in local areas for enhanced dynamic range. Specifications: Maximum Resolution: o Image: 13MP o Video: 13MP @ 60fps (Input/Output) Input Formats (Bayer): o HDR Linear Mode: Max raw 28 bits o Companding Mode: Max PWL compressed raw 24 bits Output Formats (Bayer): 14 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Video data stream interface Features: Global Tone Mapping based on histogram analysis o Adaptive global tone mapping per Input Images Local Tone Mapping for adaptive contrast enhancement Real-Time WDR Output Low Power Consumption and Small Gate Count 28-bit Sensor Data Interface
Overview: RGB-IR features in ISP enable the capture and processing of Red, Green, Blue, and Infrared (IR) light data in an Image Signal Processing (ISP) system. This functionality enhances image quality by extracting additional information not visible to the human eye in standard RGB images. By integrating IR and RGB data into the demosaic processing pipeline, the ISP can enhance scene analysis, object detection, and image clarity in applications such as surveillance, automotive, and security systems. Features: IR Core - 4Kx1EA: 4K Maximum Resolution: 3840h x 2160v @ 30fps IR Color Correction 3.99x support IR data Full-size output / 1/4x subsample support (Pure IR Pixel data) Only RGB-IR 4x4 pattern support IR data Crop support
KPIT Technologies provides robust digital frameworks that enable advanced connectivity amongst vehicle systems, driven by software innovation. These solutions are integral in turning vehicles into hubs of data exchange and engaging passenger experiences. This includes state-of-the-art in-vehicle infotainment systems and augmented reality interfaces, aiming to improve user satisfaction through personalized, secure, and efficient vehicle interactions. KPIT enhances cloud-driven solutions that effectively integrate these technological marvels, ensuring elasticity in scaling and optimizing connectivity solutions for the modern mobility ecosystem.
The PDM-to-PCM Converter is a crucial element in digital audio processing, transforming pulse-density modulation signals into pulse-code modulation format. This conversion process ensures compatibility and improved sound clarity in digital audio systems. The converter is designed with flexibility in mind, easily integrating into existing systems to enhance audio capture and playback. Used extensively in consumer electronics such as smart speakers and headsets, it plays a vital role in delivering superior audio experiences. Its efficient design aligns with low power operation, benefiting mobile and portable audio devices.
Vehicle Engineering & Design Solutions by KPIT revolve around transforming vehicle development through cutting-edge design and simulation technologies. By employing advanced Computer Aided Design (CAD) and virtual prototyping, KPIT enhances product development and market entry speed. The focus is on aligning vehicle aesthetics with functional performance, ensuring that vehicles not only appeal to modern consumers but also comply with modern sustainability mandates. KPIT’s holistic approach offers comprehensive solutions that simplify the design and validation processes, fostering innovation in both conventional and electric vehicle configurations.
The WAVE6 codec series by Chips&Media is a versatile solution offering multi-standard video encoding and decoding capabilities, tailored for high-resolution content delivery. Integrating AV1 encoding, it ensures superior streaming and bandwidth optimization. This solution is especially viable for devices requiring high efficiency and low power consumption, such as data centers and surveillance cameras. With its dual-core architecture, the WAVE6 achieves better processing speeds, supporting up to 8K resolution at 60 frames per second. Engineered with an optimized architecture, WAVE6 includes features like frame buffer compression and color space conversion, which enhance the overall performance while minimizing power use. Its design is straightforward, with a single-clock domain facilitating on-the-fly processes for various codec engines. This codec is not only efficient in terms of power usage but also capable of supporting a range of YUV formats and bit depths, maintaining high image quality with features like rotate/mirror and down-scaling functionalities. The WAVE6's specification supports a broad array of applications, from data centers needing robust processing power to automotive systems where efficiency and reliability are paramount. Its compatibility with multiple industry standards, including HEVC, AVC, and VP9, ensures that it meets diverse customer requirements while optimizing usage of external memory bandwidth through advanced compression technologies.
The Chimera GPNPU stands as a powerful neural processing unit tailor-made for on-device AI computing. This processor architecture revolutionizes the landscape of SoC design, providing a unified execution pipeline that integrates both matrix and vector operations with control code typically handled by separate cores. Such integration boosts developer productivity and enhances performance significantly. The Chimera GPNPU's ability to run diverse AI models—including classical backbones, vision transformers, and large language models—demonstrates its adaptability to future AI developments. Its scalable design enables handling of extensive computational workloads reaching up to 864 TOPs, making it suitable for a wide array of applications including automotive-grade AI solutions. This licensable processor core is built with a unique hybrid architecture that combines Von Neuman and 2D SIMD matrix instructions, facilitating efficient execution of a myriad array of data processing tasks. The Chimera GPNPU has been optimized for integration, allowing seamless incorporation into modern SoC designs for high-speed and power-efficient computing. Key features include a robust instruction set tailored for ML tasks, effective memory optimization strategies, and a systematic approach to on-chip data handling, all working to minimize power usage while maximizing throughput and computational accuracy. Furthermore, the Chimera GPNPU not only meets contemporary demands of AI processing but is forward-compatible with potential advancements in machine learning models. Through comprehensive safety enhancements, it addresses stringent automotive safety requirements, ensuring reliable performance in critical applications like ADAS and enhanced in-cabin monitoring systems. This combination of performance, efficiency, and scalability positions the Chimera GPNPU as a pivotal tool in the advancement of AI-driven technologies within industries demanding high reliability and long-term support.
The DSC Encoder core is meticulously engineered for encoding video signals using the Display Stream Compression technique. Ideal for both FPGA and ASIC applications, this encoder reduces data transmission needs while preserving visual fidelity, making it an excellent choice for high-definition broadcasting, professional video editing, and more. It supports integration across various process nodes and is compatible with existing industry standards.
This solution from Chips&Media focuses on efficient JPEG and legacy video codec functionalities. Tailored predominantly for mobile and digital imaging devices, it serves sectors like automotive systems, digital cameras, and multimedia conferencing units. The JPEG Codec/CODA/BODA offers comprehensive support for a range of color formats and resolutions, capable of handling outputs up to 290 megapixels per second, making it apt for high-volume image and video processing requirements. Focused on flexibility and performance, this IP comprises advanced image compression algorithms and customizable encoding and decoding modes. These features empower devices to process images swiftly with minimal delay, ensuring clarity and precision in each frame. With features tailored for dynamic environments, including on-the-fly format conversion and rotational adjustments, this codec maintains high-quality outputs across varying operational demands. The robustness of JPEG Codec/CODA/BODA is further enhanced by its compatibility with extensive standards, allowing broad implementation across leading audio-visual hardware. Its support for multi-view video coding, low delay processing, and minimal resource demands corroborates its utility in diverse technological landscapes, from consumer electronics to healthcare imaging solutions.
The KL730 AI SoC is equipped with a state-of-the-art third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computational power. This innovative architecture enhances computational efficiency, particularly with the latest CNN networks and transformer applications, while reducing DDR bandwidth demands. The KL730 excels in video processing, offering support for 4K 60FPS output and boasts capabilities like noise reduction, wide dynamic range, and low-light imaging. It is ideal for applications such as intelligent security, autonomous driving, and video conferencing.
Opus Encoder/Decoder is a high-performance audio codec designed for efficient and flexible sound processing. Known for its cross-platform compatibility, the Opus codec offers exceptional compression rates without sacrificing audio quality. It supports a wide range of audio frequencies and bitrates, rendering it versatile for applications ranging from internet telephony to streaming and audio archiving. This encoder/decoder ensures minimal latency, critical for seamless audio streaming, and adapts dynamically to varying network conditions to maintain optimal sound clarity. The Opus technology is pivotal for modern high-quality audio demands due to its adaptability and superior performance metrics.
The JPEG Decoder IP allows for high-quality image decoding from the JPEG format to raster scan format. Scalable and adaptable, it provides support for various chroma sampling formats and color depths. This core ensures seamless integration into multiple host systems thanks to its standalone operation capability. It incorporates a robust architectural design intended for high-throughput performance, with flexibility for on-chip and off-chip memory interfacing, making it well-suited for demanding video and imaging tasks.
This encoder core from Alma Technologies supports ultra-high throughput operations for 8-bit baseline to 10/12-bit extended JPEG encoding. Designed for modern image and Ultra HD video compression needs, it supports multiple color depths and chroma sampling formats. This IP can be configured to function entirely with on-chip resources or combine on- and off-chip memory use, ensuring flexibility across varied system architectures. The encoder seamlessly manages input and output data, using a configurable architecture that can balance silicon area and processing power.
The XCM_64X64_A provides a sophisticated architecture featuring 128 ADC 2-bit 1GSps with VGA front ends, designed for cross-correlation applications in NASA projects. Utilizing 45nm IBM SOI CMOS technology, it achieves ultra-low power consumption of approximately 0.5W for the entire array. The structure is geared towards synthetic radar receivers, radiometers, and spectrometers, operating at bandwidths from 10MHz to 500MHz. It integrates seamlessly into systems requiring precise data acquisition and processing, ideal for advanced research and observational instruments. With a focus on low power and high data throughput, the XCM_64X64_A addresses the challenges faced in high-energy physics and observational technology arenas. Its efficient power usage and robust design ensure long-term performance and reliability in demanding applications.
Arasan's MIPI DSI-2 Transmitter IP serves as the backbone for high-definition display connections, ideally suited for driving modern display panels. This IP supports a diverse range of display resolutions, making it adaptable for applications in smartphones, tablets, and automotive infotainment systems. The DSI-2 Transmitter IP provides a robust link between the display processor and the display panel, ensuring smooth video streaming with minimal latency. Its compliance with the MIPI standard allows for high-speed data transfer while maintaining data integrity through sophisticated error correction techniques. Versatility in configuration options allows the IP to support various pixel formats and refresh rates, accommodating the needs of different display technologies. Whether for gaming consoles or advanced automotive displays, this IP ensures optimal performance and vivid graphics output.
The DSC Decoder is a high-efficiency core designed to decompress video streams conforming to the Display Stream Compression (DSC) standard. Its implementation on diverse silicon platforms allows it to be integrated into a wide variety of applications, from consumer devices to medical imaging. This decoder ensures that video content remains high-quality while significantly reducing the bandwidth required for transmission.
The XCM_64X64 represents a complete cross-correlator solution with 64x64 channels, designed to cater to NASA's high-end synthetic radar receivers. Executed using IBM's 45nm SOI CMOS technology, this correlator emphasizes energy efficiency with a total power consumption of approximately 1.5W. It is engineered to support advanced radiometric and spectroscopic applications, with bandwidth capabilities ranging from 10MHz to 500MHz. The array's infrastructure supports precise signal analyses, making it ideal for use in scientific and exploratory sectors. Designed for optimum power-to-performance ratios, the XCM_64X64 excels in environments that demand high data integrity and reliable processing under stringent operational conditions. It is a vital component for synthetic aperture radar systems and other complex observational tools.
ASRC-Lite is a streamlined audio sample rate converter designed for applications requiring efficient and precise audio data conversion. This versatile solution is engineered to handle multiple audio sample rates, effectively converting audio signals with minimal latency and high sound quality. The ASRC-Lite is ideal for systems where performance and resource efficiency are paramount, embodying Coreworks' commitment to delivering high-quality audio processing capabilities. With a focus on flexibility and integration, the ASRC-Lite can be seamlessly incorporated into a variety of audio applications, ranging from consumer electronics to professional audio equipment. The module is equipped with dynamic features that ensure precise sample rate conversion across different audio formats, supporting optimal performance in real-time environments. As audio systems become increasingly complex, the ASRC-Lite provides a reliable and scalable solution that addresses the evolving needs of audio signal processing. Building on Coreworks' extensive expertise in digital audio processing, the ASRC-Lite exemplifies the marriage of cutting-edge technology and user-oriented design. By offering robust support for low-latency audio conversion, it enables developers to create sophisticated audio solutions that maintain the integrity and clarity of the original sound. This audio sample rate converter is a testament to Coreworks’ innovation in developing functionally advanced yet resource-conscious IP solutions.
The GSV3100 IP is a shader architecture-based 3D graphics solution supporting OpenGL ES 2.0/1.1 and OpenVG 1.1. It incorporates an advanced hardware processing pipeline, ideal for rendering sophisticated graphics applications that require complex shading and rendering strategies in real-time, suitable for high-performance embedded systems.
The MIPI V-NLM-01 is an image noise reduction solution utilizing Non-Local Mean (NLM) algorithms to enhance image clarity. It features a parameterized search-window size and number of bits per pixel, ensuring high-efficiency implementation in varying conditions. Supporting HDMI resolutions up to 2048x1080 at 30 to 60 fps, this core is designed for high-quality imaging needs where precision is key.
Chips&Media's WAVE5 is a proven multi-standard video codec IP renowned for its versatility in handling a broad spectrum of video formats. Designed for high-performance applications, it ensures efficient processing by utilizing dual-core technology, suitable for environments like data centers and surveillance setups. The WAVE5's capability to encode and decode at high resolutions and frame rates makes it a reliable choice for video-intensive operations. Incorporating sophisticated features such as frame buffer compression and multi-instance support, WAVE5 provides enhanced video quality while ensuring minimal latency. With support for industry standards like HEVC and AVC, it meets diverse demands within the multimedia domain, efficiently processing video streams at up to 8K60fps. The codec is optimized for power usage, allowing it to deliver excellent performance without excessive resource consumption. WAVE5's interface architecture supports robust data transfer and system control through AMBA3 APB and AXI protocols, ensuring seamless communication and operational efficiency. This is complemented by comprehensive support for bit-depth and YUV format conversions, enhancing compatibility with various media types and application needs. Its wide applicability in fields such as automotive, drones, and home entertainment underscores its adaptability and powerful processing capabilities.
Wasiela's DVB-S2-LDPC-BCH is engineered to deliver robust forward error correction (FEC) essential for digital video broadcasting, particularly over satellite applications. It efficiently combines LDPC and BCH codes to offer near error-free operation, closely approaching the Shannon limit. This capability ensures high-quality, reliable broadcast signals, even in challenging conditions, adhering to ETSI EN 302 307-1 standards.
JPEG-LS Encoder IP offers efficient and lossless image compression adhering to the ISO/IEC IS 14495-1 standard. Optimized for low-complexity functions, it manages image compression tasks with minimal host intervention. This IP supports a variety of sample depths and operates efficiently across diverse hardware environments. Its standalone configuration enables robust high-rate encoding, helping facilitate integration into existing video and image pipelines.
This encoder core efficiently supports JPEG 2000 encoding, offering capabilities for both lossy and numerically lossless compression. It supports various chroma formats and bit depths, maintaining performance across low to high resolutions. Ideal for both graphical and video applications, this encoder adapts through configurable internal engines to match processing needs, supporting detailed imaging tasks with a streamlined and powerful compression engine.
The BlueLynx Chiplet Interconnect is an adaptive interconnect solution, offering both physical (PHY) and link layer interfaces that support industry standards such as Universal Chiplet Interconnect Express (UCIe) and Open Compute Project Bunch of Wires (BoW). This IP is engineered for seamless integration with network-on-chip systems, leveraging various established standards like AMBA CHI, AXI, and ACE to provide efficient die-to-die subsystem solutions. The advanced customizable architecture of BlueLynx ensures that users can tailor the IP to specific bandwidth and physical requirements, optimizing power-performance-area (PPA) metrics across applications. With compatibility spanning nodes from 16nm, 12nm, 7nm, to as advanced as 3nm and multi-foundry support, this IP is highly adaptable to various packaging needs, whether low-cost or advanced. Incorporating high data rates from 2 Gb/s to above 24 Gb/s, the BlueLynx boasts very low power consumption and latency, achieved through < 0.375 pJ/bit energy efficiency and < 2 ns latency. It includes innovative features like staggered bump pitch options, integrated DLL with duty-cycle correction, and built-in self-test mechanisms, making it a robust choice for high-performance computing, AI, and mobile applications.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores offer top-tier video compression capabilities, optimized for FPGA implementations. These cores are ITAR-compliant and customizable, supporting 1080p60 H.264 Baseline profiles with a single core. Notable for their compact size and high speed, these cores suit various configurations including H.264 Encoder, H.264 CODEC, and H.264 I-Frame Only Encoder variants. Their flexibility allows customization for specific pixel depths and resolutions, catering to unique project demands. An evaluation license is available for this high-performance core, designed to integrate seamlessly into FPGA environments, delivering minimal latency and high throughput that meets industry standards.
The Camera ISP Core is designed to optimize image signal processing by integrating sophisticated algorithms that produce sharp, high-resolution images while requiring minimal logic. Compatible with RGB Bayer and monochrome image sensors, this core handles inputs from 8 to 14 bits and supports resolutions from 256x256 up to 8192x8192 pixels. Its multi-pixel processing capabilities per clock cycle allow it to achieve performance metrics like 4Kp60 and 4Kp120 on FPGA devices. It uses AXI4-Lite and AXI4-Stream interfaces to streamline defect correction, lens shading correction, and high-quality demosaicing processes. Advanced noise reduction features, both 2D and 3D, are incorporated to handle different lighting conditions effectively. The core also includes sophisticated color and gamma corrections, with HDR processing for combining multiple exposure images to improve dynamic range. Capabilities such as auto focus and saturation, contrast, and brightness control are further enhanced by automatic white balance and exposure adjustments based on RGB histograms and window analyses. Beyond its core features, the Camera ISP Core is available with several configurations including the HDR, Pro, and AI variations, supporting different performance requirements and FPGA platforms. The versatility of the core makes it suitable for a range of applications where high-quality real-time image processing is essential.
The H.265/HEVC H.264/AVC 422 12bit Multi-Codec for 8K is meticulously designed to cater to the massive data requirements of 8K video encoding and decoding. Offering high compression ratios, it significantly reduces bandwidth usage while maintaining the high-quality visuals necessary for ultra-high-definition formats. Specialists in fields like broadcasting and high-resolution video production can leverage this codec's powerful capabilities to deliver pristine image quality. It incorporates the latest compression technologies, allowing fluid playback and interaction even with the most data-intensive video formats. The technology eases the transition to higher resolutions, ensuring enhanced viewer experiences and streamlined broadcasting operations.
The IP Camera Front End by Bitec is specifically optimized for Altera CMOS sensor technology, providing a comprehensive parameterized design that enhances video signal processing, especially for high-resolution camera applications. This IP is critical in industries that rely on accurate image data capture, including security surveillance, industrial inspection, and scientific imaging.\n\nThis tailored solution supports the integration of complex video analytics, ensuring rapid data throughput and minimal latency in video processing. Its ability to handle large data volumes with precision and accuracy is a testament to its robust engineering design. Users benefit from this system's configuration flexibility, which allows customization according to specific application demands, whether in high-speed environments or scenarios demanding detailed image analysis.\n\nEngineered with adaptability in mind, the IP core supports a wide array of video outputs, maintaining compatibility with both legacy and emerging video standards. This ensures that manufacturers can easily implement the core into their systems, maintaining a significant edge in the competitive field of multimedia technology.
Imec's Hyperspectral Imaging System leverages its advanced semiconductor technology to push the boundaries of on-chip spectral imaging. Designed for high-performance applications, this imaging system allows for detailed Earth observation and a variety of other uses. The system encompasses unique innovations in sensor technology, enabling a broad spectrum of light capture that extends beyond traditional imaging limits. By merging this with an enhanced imaging processor, the Hyperspectral Imaging System offers even more refined and precise data capture. This system is tailored for industries where precision and reliability are paramount, such as agriculture, mining, and environmental monitoring. Imec has engineered this technology to not only capture visible light but also the infrared spectrum, maximizing the information the device can collect. The compact, efficient setup makes it feasible for integration into broader systems or standalone applications. By ensuring impeccable spectral resolution and operational efficiency, the Hyperspectral Imaging System stands out as a versatile solution for demanding imaging requirements. Imec's continual research and development in this domain ensure that this imaging technology evolves alongside the emergent needs of diversified industries.
Designed for high-quality image processing, the JPEG XS Encoder/Decoder targets applications requiring low-latency and visually lossless video transmission. This technology is particularly useful in real-time video streaming environments where consistency and minimal delay are critical. Its efficiency in compression while maintaining image integrity makes it a preferred choice for industries moving towards 8K and beyond. Capable of seamless integration into existing systems, this encoder/decoder facilitates high-speed data transfer, keeping latency to an absolute minimum while upholding image quality standards. Its adaptability is enhanced by supporting a wide range of platforms, ensuring that it meets expansive industry needs.
The VoSPI Rx for FLIR Lepton IR Sensor by BitSim NOW is tailored for capturing and managing infrared sensor data effectively. Designed to work with Xilinx-7 platforms, this IP is aimed at applications requiring precise thermal imaging and data processing. It optimizes the data acquisition process by ensuring successful and efficient data reception from infrared sensors, crucial in fields like surveillance, medical imaging, and industrial automation. This receiver is an essential component for those looking to integrate advanced thermal sensing capabilities into their technology solutions, offering robust performance and reliability.
ZIA Stereo Vision is an advanced stereoscopic vision module designed to provide precise distance estimation. By combining left and right camera inputs, it leverages semi-global matching algorithms to derive depth maps essential for applications like autonomous vehicles and robotic navigation. It operates under varying image resolutions and provides high-speed processing, ensuring integration into systems where rapid environmental mapping is crucial. Its hardware design optimizes power, space, and performance metrics, making it ideal for high-demand use cases that rely on accurate spatial awareness.
The KL630 AI SoC embodies next-generation AI chip technology with a pioneering NPU architecture. It uniquely supports Int4 precision and transformer networks, offering superb computational efficiency combined with low power consumption. Utilizing an ARM Cortex A5 CPU, it supports a range of AI frameworks and is built to handle scenarios from smart security to automotives, providing robust capability in both high and low light conditions.
Altek's AI Camera Module exemplifies innovation in the realm of smart imaging solutions, designed to serve as a critical component in AI recognition and video processing systems. This module integrates advanced image processing capabilities, enabling it to deliver superior high-resolution images that are indispensable for AI-driven applications. With an expert blend of lens design and software integration, the module achieves optimal performance in AI and IoT contexts. This modular solution is highly adaptable, supporting edge computing to meet real-time data processing needs. It can cater to high-resolution demands such as 2K and 4K video quality, enhancing detail and clarity for surveillance or autonomous platforms. Its rich functionality spans a range of use cases, from facial recognition and tracking to complex video analytics, ensuring clients have a flexible solution that fits into various AI ecosystems. Altek’s AI Camera Module is designed for seamless integration, offering capabilities that span across consumer electronics, industrial applications, and smart cities. It stands out by providing robust performance and high adaptability to different environments, harnessing machine learning algorithms to improve precision and efficiency. The module's collaboration potential with global brands underlines its reliability and advanced technological framework, making it a go-to choice for organizations aiming to excel in high-end AI+IoT implementations.
The H.264 Low Power & Low Latency HW Video Decoder from Atria Logic is engineered to fit low-power mobile and industrial contexts. It supports H.264 Baseline Profile decoding, targeting a wide range of applications including in-car infotainment, industrial robotics control, and mobile device media playback. Supporting decoding resolutions up to 1080p30, this decoder is designed for low-latency performance, a necessity for real-time video applications. Implemented using a clock-gated, multi-domain design, it ensures power-efficient operation, ideal for battery-powered or cost-sensitive environments. Additional features such as support for error resilient operations and advanced decoding techniques make it exceptionally flexible and robust. The IP’s architecture is heavily optimized to facilitate high performance on modest power budgets, thereby extending the capabilities of mobile and embedded systems seeking advanced video processing functionalities.
ISPido on VIP Board is a tailored run-time solution designed specifically for Lattice Semiconductors' VIP board, offering enhanced image processing capabilities. Designed for real-time image sharpness and balance, the system provides both automatic configuration options and manual fine-tuning capabilities through a menu interface. This interface allows the selection of different gamma tables, application of convolutional filters, and more. The VIP Board includes CrossLink and HDMI bridges and uses Sony IMX 214 image sensors with an ECP5-85 FPGA processor, ensuring robust processing power and high-quality image output. With a resolution output of 1920 x 1080p over HDMI and YCrCb 4:2:2 format, this board is instrumental in achieving runtime calibration. Overall, ISPido on VIP Board offers a customizable platform for image processing tasks, balancing ease of use with powerful processing capabilities, thus supporting a variety of video and vision applications.
The MVUM1000 ultrasound sensor array is highly specialized for medical imaging applications, offering a 256-element linear array formation. Employing capacitive micromachined ultrasound transducers (CMUT), it ensures superior sensitivity and integrability with modern interface electronics. This ultrasound sensor caters specifically to medical imaging, facilitating real-time diagnosis with applications in point-of-care and handheld devices. The use of capacitive transduction enables high sensitivity to acoustic pressure while maintaining minimal power consumption, an advantage in power-sensitive applications. Equipped with integrated front-end electronics, the MVUM1000 supports multiple imaging modes. The sensor's compact, yet highly efficient design ensures it meets the stringent needs of modern medical equipment while offering customization opportunities for specific technological demands.
The SL 100X Universal Demodulator is a versatile software-defined baseband demodulator IC that supports various waveform standards. Designed to cover a wide range of applications, this demodulator is a fully programmable solution that enables compatibility with multiple radio standards. The IC's architecture allows for adaptability in dynamic environments, making it ideal for broadcast, mobile devices, and other communication platforms. Saankhya Labs has incorporated ultra-low power consumption and a minimal footprint into the SL 100X, ensuring that energy efficiency is maintained without compromising performance. This universal approach allows developers to streamline their product lines without sacrificing the versatility required for modern communication environments. The SL 100X broadens access to flexible communication solutions, granting engineers the ability to introduce new technologies with ease. From traditional broadcasting systems to the latest in mobile communication, the SL 100X acts as a cornerstone for the creation of advanced wireless communication systems.
This core is a highly integrated solution tailored for Gigabit Ethernet and Fibre Channel transceiver applications. It incorporates all necessary components such as high-speed drivers, clock recovery, DLL and PLL architectures, serializer/deserializer (SERDES), low jitter PECL interfaces, and data alignment features. Designed for inherently full duplex operation, it supports a 1.25 Gbps data rate, compliant with IEEE 802.3z standards. The transceiver offers a programmable receive cable equalization without the need for external loop filter capacitors and minimizes transmit jitter through its advanced equalization techniques. With embedded bit error rate testing capabilities and a low-cost CMOS implementation, it efficiently supports 75 and 50 Ohm terminations, thereby enhancing its versatility in various high-speed networking applications.
Trion FPGAs by Efinix are optimized for the fast-paced demands of the edge computing and IoT sectors. Built on a 40 nm process, these FPGAs provide a blend of power-performance-area efficiency suitable for a wide array of innovative applications including mobile, consumer electronics, industrial systems, and more. With logic densities ranging from 4K to 120K logic elements, Trion FPGAs are versatile enough to cater to both standard and burgeoning tech markets. The Trion lineup features a robust set of integrated interfaces including GPIO, PLLs, oscillators, DDR, MIPI, and LVDS, making them adaptable to varied application needs. These attributes, combined with their commitment to low power consumption, render them ideal for wearables, smart devices, and portable imaging systems where space and power efficiency are paramount. In terms of development flexibility, Trion FPGAs are available in a variety of package options, including tiny WLCSP packages designed for compact, integrated applications. With embedded DDR controllers and support for RISC-V processors, these FPGAs provide scalable solutions for building complete systems encompassing video processing, consumer applications, and advanced IoT deployments.
The Vega eFPGA from Rapid Silicon represents an innovative leap in providing customizable FPGA capabilities to System-on-Chip (SoC) designs. This eFPGA is designed to deliver flexibility and efficiency, allowing a seamless integration that enhances performance without raising costs. By embedding programmability directly into SoCs, Vega eFPGA facilitates diverse and adaptable computing needs. Structured with three configurable tile types – CLB, BRAM, and DSP – the Vega eFPGA is engineered for optimal performance. The CLB comprises eight 6-input lookup tables (LUTs), each offering dual independent outputs. It includes features like fast adders with carry chains and programmable registers, ensuring computational versatility. The BRAM component supports 36Kb dual-port memory, adaptable as 18Kb split memory configurations. The DSP tile incorporates an 18×20 multiplier with a 64-bit accumulator, supporting complex mathematical processing. Rapid Silicon's Vega eFPGA is optimized for scalability, providing flexibility in tile configurations to meet varied application requirements. It ensures ample compatibility with existing systems through seamless SoC integration, proprietary Raptor EDA tools, and robust IP libraries. These capabilities enable Vega to offer bespoke solutions tailored to specific end-user needs.
ASRC-Pro is an advanced audio sample rate converter tailored for high-end audio applications that demand superior sound fidelity and versatility. This IP is engineered to manage complex audio streams, providing seamless and accurate conversion between different audio sample rates while ensuring minimal distortion and optimal sound quality. ASRC-Pro is suitable for a wide range of professional audio and broadcast environments, setting the benchmark for performance and reliability in audio processing. Coreworks has developed the ASRC-Pro to meet the exacting standards of audio professionals. It offers a comprehensive suite of features that facilitate the manipulation of audio data, enhancing both usability and integration within larger audio architectures. The ASRC-Pro supports a variety of audio formats and sample rates, allowing developers to create diverse audio solutions that are flexible and scalable. Its superior noise reduction capabilities and robust architecture make it a preferred choice for applications where sound quality is non-negotiable. Moreover, the ASRC-Pro is exemplary of Coreworks' dedication to providing state-of-the-art solutions in digital signal processing. With its advanced processing capabilities and user-centric design, this converter enables the delivery of pristine audio clarity, making it invaluable for high-fidelity audio systems and applications. By incorporating Coreworks' cutting-edge technologies, ASRC-Pro enhances the end-user’s auditory experience with precision and clarity.
Atria Logic offers a sophisticated H.264 UHD Hi422 Intra Video Decoder, designed for applications such as medical imaging and professional video production. This IP enables pristine video quality with support for 10-bit video and YUV 4:2:2 color sampling, ensuring smooth gradations and vivid colors. Its architecture facilitates low-latency video decoding at sub-frame levels, making it ideal for critical broadcast and industrial applications. The decoder integrates seamlessly into existing systems with its implementation in Xilinx Zynq-7000 programmable logic. It efficiently utilizes the programmable resources, allowing ample space for additional circuit integration. Being compliant with the H.264 High-422 profile at Level 5.1, it supports high-resolution video content up to 3840x2160p30. It is especially suitable for scenarios demanding high video fidelity and reliability. This IP stands out for its ability to deliver low latency with glass-to-glass delays as little as 0.6ms, crucial for real-time monitoring and manipulation tasks. It combines powerful features with ease of integration, making it a valuable asset for enterprises looking to enhance their video processing capabilities.
The JPEG2000 Video Compression Solution by StreamDSP is crafted to provide flexible, high-grade compression and decompression capabilities for video and still images. This solution stands out due to its capability to perform both lossy and lossless compression within a single codestream, making it ideal for applications that require a balance between quality and compression efficiency. Optimized for FPGA implementations, this solution circumvents the need for external processing units, streamlining integration complexities. JPEG2000's robustness caters to diverse fields such as medical imaging, digital cinema, and remote sensing, where clarity and precision are paramount. The architecture's flexibility allows it to be molded to specific project demands, ensuring that each application from digital photography to scientific imaging benefits from superior image integrity and compression ratios.
The WDR Core provides an advanced approach to wide dynamic range imaging by controlling image tone curves automatically based on scene analysis. This core is adept at ensuring that both shadows and highlights are appropriately compensated, thus maintaining image contrast and true color fidelity without the reliance on frame memory. Automatic adjustments extend the dynamic range of captured images, providing detailed correction in overexposed and underexposed areas. This capability is vital for environments with variable lighting conditions where traditional gamma corrections might introduce inaccuracies or unnatural visual effects. The core focuses on enhancing the user experience by delivering detailed and balanced images across diverse scenarios. Its versatility is particularly useful in applications like surveillance, where clarity across a range of light levels is critical, and in consumer electronics that require high-quality imaging in varying illumination.