All IPs > Interface Controller & PHY > MIPI
The MIPI category under Interface Controller & PHY encompasses a broad range of semiconductor IPs tailored for high-speed data transfer between components in mobile and IoT devices. MIPI, which stands for Mobile Industry Processor Interface, is an industry-driven standard aimed at simplifying the integration of different advanced technologies into small form factor devices while ensuring optimal communication efficiency and power consumption.
Within this category, you will find semiconductor IPs that address the critical need for reducing latency and increasing the bandwidth of data communication across various internal components. These MIPI interfaces are vital in smartphones, tablets, and other portable electronics, where space is at a premium, yet there's a demand for high-performance data exchange and energy efficiency. The IPs provide solutions for connecting processors to modems, sensors, displays, and cameras, enabling manufacturers to build devices with faster data processing capabilities and higher battery life.
MIPI semiconductor IPs in this category include MIPI D-PHY, C-PHY, and M-PHY, among others. These IPs are designed to support versatile and scalable designs, allowing for personalization depending on the specific requirements of the end product. MIPI D-PHY, for instance, is often used in applications requiring video transmission with high-quality imaging sensors, providing a robust method to deliver both power and data through the same interface.
By leveraging MIPI semiconductor IPs, designers can ensure that their products adhere to the latest industry standards, providing a competitive edge in the technology market. These IPs support a seamless interface experience, enhance data transmission efficiencies, and reduce both development time and costs. Integrating MIPI interface controller and PHY solutions will drive innovation and bring sophisticated electronic products to market faster and more efficiently than ever before.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
The SerDes Interfaces from Silicon Creations feature cutting-edge capabilities for high-speed serial data transmission in semiconductor devices. Supporting a vast range of industry protocols, these interfaces offer both flexibility and performance, making them ideal for varied high-bandwidth applications. These interfaces accommodate rates from as low as 100Mbps to an impressive 32.75Gbps, covering a wide spectrum of technologies from JESD204 to PCIe and V-by-One. They include programmable serialization and deserialization features, along with advanced techniques for reducing latency, ensuring the rapid delivery and reception of data streams. Built on proven IP platforms, the SerDes interfaces integrate advanced PLLs to manage jitter and power consumption effectively. With adaptability to a multitude of fabrication nodes, these solutions meet the diverse needs of networked devices and high-speed interconnects, showcasing Silicon Creations’ expertise in providing industry-leading communication solutions.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The LVDS/D-PHY Combo Receiver by Mixel is intended for high-throughput environments where compatibility with both LVDS and D-PHY standards is essential. It combines the benefits of a source-synchronous physical layer for MIPI D-PHY and the TIA/EIA-644 standard LVDS, offering significant versatility. Its high-performance architecture ensures rapid data provisioning with minimized energy requirements, making it ideal for use in devices where efficient power handling and robust communication interfaces are necessary.
The C/D-PHY Combo is an advanced hybrid PHY designed for use in systems requiring both high flexibility and efficiency. As a dual-configuration PHY, it can switch between C-PHY and D-PHY configurations, functioning as a receiver or transmitter depending on application needs. This adaptability makes it particularly valuable for cutting-edge mobile and IoT devices, where it offers optimized performance under varying power conditions. The IP’s low-power consumption and support for multiple process nodes ensure it can be employed across diverse manufacturing landscapes.
Mobiveil's NVM Express Controller is engineered for both enterprise and client applications, designed to unleash the potential of PCIe-based SSDs. It features a flexible, configurable architecture optimized for thread management, reliability, and power efficiency while ensuring maximum performance. It can be integrated seamlessly with Mobiveil's PCI Express Controller and a variety of third-party NAND Flash controllers, further enhancing data throughput and overall system efficiency.
SkyeChip’s MIPI D-PHY is a fully integrated interface solution adhering to the MIPI D-PHY v2.5 standard. This IP block supports data transfer rates up to 1.5 Gbps per lane, extendable to 2.5 Gbps per lane for enhanced throughput. Its low-power state modes make it highly efficient for portable and low-energy system designs. By offering seamless lane control and interface logic integration, it caters to various demanding connectivity specifications, ensuring compatibility and efficiency in data transmission applications.
The LVDS Serializer from Mixel is a high-efficiency component designed for converting parallel data streams into serial data format. With capabilities that maximize data rates up to 5Gbps, it serves high-performance applications needing efficient data transmission over minimal wiring. Implemented using digital CMOS technology, this serializer works over four channels, allowing smooth integration into systems demanding high throughput with reduced electromagnetic interference. Its adaptations make it well-suited for data-intensive environments such as high-speed data acquisition systems or video transmission interfaces.
The CT25205 integrates several building blocks of the IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. Designed with Verilog HDL, this digital core is optimized for implementation on both standard cells and FPGA architectures, ensuring seamless compatibility with IEEE Ethernet MAC interfaces through MII. The core's standout feature is the integrated Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer, which allows existing MACs to leverage PLCA benefits without additional hardware modifications. A key aspect of this design is its connectivity to an OPEN Alliance 10BASE-T1S PMD Interface, streamlining integration into Zonal Gateways and MCUs. Paired with Canova Tech's complementary IPs, such as the CT25208 MAC controller, CT25205 forms the backbone of cutting-edge communication systems in industries requiring efficient data exchange. The CT25205 supports a wide array of industrial applications due to its robustness and capability to enhance the existing communication frameworks. It is particularly well-suited for automotive and industrial environments where reliable and durable Ethernet solutions are crucial.
The MIPI CSI2MUX-A1F is a CSI2 Video Multiplexer designed to aggregate inputs from up to four CSI2 cameras into a single output stream. Compliant with CSI2 rev 1.3 and DPHY rev 1.2, this video multiplexer can manage data transmission at 4 x 1.5Gbps. It's perfect for applications requiring efficient conversion from multiple image sources to a consolidated feed.
The Arria 10 System on Module (SoM) is designed with an emphasis on embedded and automotive vision applications. This compact module leverages Altera's Arria 10 SoC devices in a sleek 29x29 mm package, offering a plethora of interfaces while maintaining a small, efficient form factor. It features an Altera Arria 10 SoC FPGA with a range from 160 to 480 KLEs, coupled with a Cortex A9 Dual-Core CPU. This enables robust integration and performance for demanding applications. The module's power management system ensures a seamless power-up and -down sequence, requiring only a 12V supply from the baseboard. Its dual DDR4 memory interfaces provide up to 2.4 Gbit/s per pin, offering a total bandwidth of up to 230 Gbit/s for both CPU and FPGA memory systems. This module supports a wide array of high-speed interfaces, including PCIe Gen3 x8, 10/40 Gbit/s Ethernet, DisplayPort, and 12G SDI, making it suitable for complex imaging and communication tasks. Additional features include up to 32 LVDS lanes for configurable RX or TX, two USB interfaces with OTG support, and ARM I²C, SPI, and GPIO interface signals. Furthermore, the Arria 10 SoM includes pre-configured IP for memory controllers and an Angstrom Linux distribution, facilitating rapid development and deployment of applications.
Mixel’s LVDS/D-PHY Combo Transmitter is a versatile component tailored for high-speed data transmission. It integrates a MIPI D-PHY with a robust LVDS transmitter, creating a platform capable of handling the diverse requirements of modern telecommunications. This combo allows seamless interfacing between components using different signaling standards, enhancing system compatibility. Through its energy-efficient architecture, the transmitter is suited for applications that prioritize reduced power consumption without compromising on speed, such as in mobile or portable devices.
Arasan's MIPI DSI-2 Transmitter IP serves as the backbone for high-definition display connections, ideally suited for driving modern display panels. This IP supports a diverse range of display resolutions, making it adaptable for applications in smartphones, tablets, and automotive infotainment systems. The DSI-2 Transmitter IP provides a robust link between the display processor and the display panel, ensuring smooth video streaming with minimal latency. Its compliance with the MIPI standard allows for high-speed data transfer while maintaining data integrity through sophisticated error correction techniques. Versatility in configuration options allows the IP to support various pixel formats and refresh rates, accommodating the needs of different display technologies. Whether for gaming consoles or advanced automotive displays, this IP ensures optimal performance and vivid graphics output.
The MIPI SVRPlus-8L-F is an advanced 8-lane, second-generation Serial Video Receiver designed specifically for FPGA applications. It supports CSI2 rev 2.0 and DPHY rev 1.2, allowing it to handle high-speed data transmission efficiently. The receiver can manage 16 virtual channels and provides 4 pixels output per clock cycle, complete with calibration support. Furthermore, it includes communication error statistics to ensure reliability.
The MIPI SVTPlus-8L-F is an innovative 8-lane, second-generation Serial Video Transmitter crafted for FPGA contexts. It aligns with CSI2 rev 2.0 and DPHY rev 1.2 standards, ensuring robust and efficient data transmission. Operating at a remarkable speed of 12Gbps, this transmitter is optimized for high-performance environments where precision and speed are paramount.
The MIPI CSI-2 Tx Compact Transmitter designed by BitSim NOW is a versatile solution for transmitting data efficiently across different platforms. It is compatible with Xilinx Spartan-6/7, Kintex, Zynq, Ultrascale, and Ultrascale+ platforms, making it suitable for a wide range of applications in imaging and graphics. This transmitter ensures reliable data transfer and optimal performance across various devices, enhancing the capability of integrated systems. It facilitates high-speed communication channels which are critical in applications requiring rapid data processing and low latency.
The MIPI SVRPlus2500 is a sophisticated 4-lane video receiver that adheres to CSI2 rev 2.0 and DPHY rev 1.2 standards. Designed to support low clock ratings for simpler timing closure, it offers PRBS support and outputs 4/8/16 pixels per clock. This receiver incorporates 16 virtual channels and 1:16 input deserializers per lane, making it a versatile choice for intricate video applications. Handling data rates up to 4 x 2.5Gbps, it is built for high-efficiency environments.
Mixel’s LVDS Deserializer is engineered to convert high-speed serial data streams back to parallel data format. Implemented with digital CMOS technology, it supports up to 5Gbps data rate over multiple channels, enabling efficient data handling in data-centric systems. This component ensures reliable data integrity and quick adaptation to different data transmission needs, making it particularly suited for applications such as image processing, high-definition video decoding, and other systems where data precision and speed are critical.
The MIPI SVTPlus2500 is an advanced 4-lane video transmitter that uses CSI2 rev 2.0 and DPHY rev 1.2 protocols. Optimized for easy timing closure through its low clock rating, it includes PRBS support and can handle 8/16 pixel input per clock. With the capability to manage 16 virtual channels at a speed of 4 x 2.5Gbps, this transmitter is ideal for dynamic video environments that demand flexibility and precise programmable timing parameters.
BitSim NOW's MIPI CSI-2 Rx Compact Receiver is designed to deliver high-performance data reception for imaging and graphical applications. This receiver is compatible with FPGA platforms such as Xilinx Spartan-6/7, Kintex, Zynq, and Ultrascale series, ensuring a wide compatibility range for developers and engineers. By supporting high-speed data reception, the Rx Compact Receiver facilitates seamless communication and data integrity, which are essential in real-time imaging processes and applications that require precise data management. The receiver is engineered to support robust data handling capabilities, enhancing the overall system efficiency.
The D-PHY, part of the MIPI Alliance's suite of physical layer specifications, is designed for lower-power applications. Mixel's D-PHY is optimized for mobile, IoT, and wearable devices, delivering high data rates while ensuring power efficiency. The design supports multiple power modes and a wide range of data rates, providing vendors with the flexibility to balance battery life with performance demands. Mixel supports adaptability through various process nodes, ensuring that the D-PHY core can be integrated seamlessly across different manufacturing processes.
The BlueLynx Chiplet Interconnect is an adaptive interconnect solution, offering both physical (PHY) and link layer interfaces that support industry standards such as Universal Chiplet Interconnect Express (UCIe) and Open Compute Project Bunch of Wires (BoW). This IP is engineered for seamless integration with network-on-chip systems, leveraging various established standards like AMBA CHI, AXI, and ACE to provide efficient die-to-die subsystem solutions. The advanced customizable architecture of BlueLynx ensures that users can tailor the IP to specific bandwidth and physical requirements, optimizing power-performance-area (PPA) metrics across applications. With compatibility spanning nodes from 16nm, 12nm, 7nm, to as advanced as 3nm and multi-foundry support, this IP is highly adaptable to various packaging needs, whether low-cost or advanced. Incorporating high data rates from 2 Gb/s to above 24 Gb/s, the BlueLynx boasts very low power consumption and latency, achieved through < 0.375 pJ/bit energy efficiency and < 2 ns latency. It includes innovative features like staggered bump pitch options, integrated DLL with duty-cycle correction, and built-in self-test mechanisms, making it a robust choice for high-performance computing, AI, and mobile applications.
The M-PHY serves as a high-performance physical layer targeted at energy-sensitive applications in mobile and wearable technologies. Engineered for speed without excessive power draw, the M-PHY finds its place in environments where long-lasting performance is crucial. The architecture is modular, adapting to various data rates and power management states, enabling it to align with the stringent power requirements of modern electronics, such as smartphones and portable IoT devices. The integration-ready IP supports a multitude of technology nodes, ensuring compatibility across a wide spectrum of manufacturing settings.
The MIPI IP offered by Silicon Library enables high-speed communication between components inside a device, supporting modern displays and camera modules. Its DPHY-Tx and DPHY-Rx configurations provide versatile solutions for transmitting and receiving data efficiently across various electronic devices. Designed to optimize performance, the MIPI IP supports extensive data rates and a wide range of resolutions, making it integral for high-resolution displays and camera sensors in smartphones, tablets, and other portable devices. It facilitates seamless integration, ensuring robust communication pathways. Energy efficiency is a key feature, as it is engineered to deliver high performance while minimizing power consumption. This makes the MIPI a crucial component in mobile and consumer electronics, where battery life and performance are paramount. Its flexible architecture allows for adaptation to different system requirements, providing a reliable interface solution.
The MIPI CSI-2 Receiver IP by Arasan is an integral component for high-speed data transmission in camera applications. This IP facilitates the camera sensor to processor interface, adhering to the MIPI specification standard. It supports performance enhancements with high bandwidth, allowing seamless capture of images and video. The CSI-2 Receiver IP is engineered to handle significant data loads, enabling real-time processing of high-resolution images. Its design includes features for error correction and auto-calibration, contributing to reliability and data integrity. Compliance with the MIPI specification ensures broad compatibility with a range of camera sensors and microcontrollers. Configurability is a key advantage, with support for various data formats and transmission modes tailored for specific user needs. This adaptability simplifies the integration process across different applications, from smartphones and tablets to automotive camera systems, ensuring consistent performance across the board.
Altek's AI Camera Module exemplifies innovation in the realm of smart imaging solutions, designed to serve as a critical component in AI recognition and video processing systems. This module integrates advanced image processing capabilities, enabling it to deliver superior high-resolution images that are indispensable for AI-driven applications. With an expert blend of lens design and software integration, the module achieves optimal performance in AI and IoT contexts. This modular solution is highly adaptable, supporting edge computing to meet real-time data processing needs. It can cater to high-resolution demands such as 2K and 4K video quality, enhancing detail and clarity for surveillance or autonomous platforms. Its rich functionality spans a range of use cases, from facial recognition and tracking to complex video analytics, ensuring clients have a flexible solution that fits into various AI ecosystems. Altek’s AI Camera Module is designed for seamless integration, offering capabilities that span across consumer electronics, industrial applications, and smart cities. It stands out by providing robust performance and high adaptability to different environments, harnessing machine learning algorithms to improve precision and efficiency. The module's collaboration potential with global brands underlines its reliability and advanced technological framework, making it a go-to choice for organizations aiming to excel in high-end AI+IoT implementations.
Designed to meet the demands of high data rate transmission, Mixel’s C-PHY is an essential component in the MIPI standard’s lineup. It provides the necessary framework for devices requiring low energy consumption without compromising speed. Targeting mobile, wearable, and IoT applications, the C-PHY facilitates power management and delivers data through a flexible serial communication interface. This IP supports an extensive array of process nodes, making it versatile for deployments across varied technological landscapes from advanced mobile devices to developing IoT ecosystems.
The X1 SATA SSD Controller is designed for high performance and power efficiency in industrial environments. It features a 32-bit dual-core microprocessor optimized for flash handling, integrating unique instruction sets and hardware accelerators. The controller includes enhanced durability with the hyMap Flash Translation Layer and FlashXE for extended endurance, making it ideal for industrial SSDs, CFast cards, and M.2 modules. It offers comprehensive flash management and security features, ensuring robust and reliable data storage.
The Tentiva Video FMC board stands out as a sophisticated solution for advanced video processing needs, offering modularity for easy customization and expansion. This board includes two high-speed PHY slots that support data rates up to 20 Gbps, designed to facilitate communication between the board and a variety of PHY cards. The modular architecture allows developers to adapt to specific project requirements easily, inserting or removing PHY cards as needed. This design flexibility supports a variety of applications, ranging from standard video transmission to more intricate and diverse setups. Available PHY card options include DPT14X, DP14RX, eDP14TX, DP21TX, and DP21RX, facilitating operations across different DisplayPort versions. Designed for compatibility with FPGA development boards equipped with an FMC header, the Tentiva Video FMC integrates seamlessly with numerous boards from various manufacturers. Its versatility makes it a reliable choice for projects demanding high-speed video processing and transmission capabilities, keeping pace with evolving industry demands.
The SerDes product from KNiulink Semiconductor is designed with state-of-the-art architecture and technology, optimized for low energy consumption and exceptional performance applications. It features a high degree of configurability, allowing seamless integration with user logic or SOCs. This versatile IP supports a variety of protocols including PCIE, RapidIO, SATA, SAS, JESD204, USB3.1, LVDS, and MIPI, making it a crucial component for high-speed data transfer solutions.
The ADNESC ARINC 664 End System Controller is a robust and high-performance solution designed for the aeronautics sector, featuring full compliance with RTCA DO-254 and a development process adhering to RTCA DO-178B standards. Renowned for its high-speed multi-host interface, it achieves data transfer rates up to 400 Mbit/s, making it ideal for next-generation avionic data networks. This controller is lauded for its target device independence, achieved through generic VHDL code development, allowing for flexibility and adaptability across different system architectures. Embedded with SRAM, it provides rapid access times and enhances processing efficiency, crucial for avionics applications where timely data handling is critical. By integrating advanced features such as multi-host support, the ADNESC ARINC 664 ensures that avionic systems can maintain high levels of reliability and interoperability within complex aerospace environments. IOxOS Technologies has designed this controller to meet the rigorous demands of modern aerospace applications, providing robust solutions that are adaptable, efficient, and ready for future technological advancements.
The RF-SOI and RF-CMOS platforms offered by Tower Semiconductor are engineered to deliver exceptional performance for wireless communication applications. This platform is designed to address the needs of high-frequency and low-power RF applications essential for modern telecommunications, including 5G, IoT devices, and other consumer electronics requiring seamless connectivity. By leveraging RF-SOI technology, the platform achieves lower power consumption and improved integration of RF components, thereby enhancing system performance and reducing overall product costs. RF-CMOS adds to this by providing flexibility in designing integrated circuits that need both analog and digital components on a single chip, useful for space-constrained applications without sacrificing performance. These platforms support a wide bandwidth spectrum and high dynamic range, making them ideal for high-speed data transfer applications. With advanced design enablement support such as comprehensive PDKs and simulation tools, the RF-SOI and RF-CMOS platforms facilitate quick adaptation and integration into existing product lines, accelerating the development process of cutting-edge wireless solutions.
The Titanium Ti375 is an innovative FPGA from Efinix, designed for applications requiring high-density logic and low power consumption. This component integrates the advanced Efinix Quantum compute fabric with extensive I/O capabilities, making it highly suitable for a range of demanding tasks. Featuring a hardened RISC-V block and versatile SerDes transceivers, the Ti375 is built to handle complex tasks such as compute acceleration and machine learning applications. One of the standout features of the Ti375 is its SerDes transceiver, capable of supporting multiple protocols including PCIe 4.0, Ethernet SGMII, and 10GBase-KR, offering data rates from 1.25 Gbps to 16 Gbps. This makes it ideal for high-speed network and communication applications. The FPGA's RISC-V block enhances processing capabilities with a quad-core configuration, efficiently balancing hardware and software tasks. For developers, the Ti375 offers configurable high-speed I/O, supporting a variety of single-ended and differential standards, including MIPI and LVDS. This configurability ensures that developers can tailor I/O to meet specific system needs, facilitating seamless integration into existing infrastructures. Additionally, the Titanium series' power and performance metrics ensure that it is adept for applications in automotive, industrial automation, machine vision, and more.
The MIPI C-PHY Interface offers a physical channel for the Camera Serial Interface 2 (CSI-2), providing a bandwidth of 5.7 Gbps per lane. By optimizing throughput over channels limited by bandwidth, this technology facilitates increased data transmission without demanding a higher signaling clock rate, making it highly efficient for next-gen applications.
The MIPI Video Processing Pipeline leverages the MIPI standards to enable efficient video data processing tailored for embedded FPGA platforms. This comprehensive solution supports key video protocols like Avalon and AXI-4 Streaming, adapting easily to various sensor video formats and frame rates. The pipeline handles resolutions reaching 4K at 60 frames per second, catering to high-definition video requirements in consumer electronics and professional imaging markets. With its scalable architecture, it allows multiple pixels per clock processing without compromising on performance, aiding in resource optimization. StreamDSP's pipeline supports customizable stages such as defective pixel correction, color correction, and chroma resampling, each pivotal in achieving high-quality video output. This flexibility ensures the IP can be utilized in diverse applications ranging from automotive infotainment systems to industrial imaging setups.
The Universal High-Speed SERDES is an innovative solution aimed at providing flexible data transmission across different applications with rates ranging from 1G to 12.5Gbps. This interface core is engineered to address the high-speed data exchange requirements found in systems such as RapidIO, Fiber Channel, and XAUI. A key feature of this SERDES is its programmable pre-emphasis and adaptive equalization capabilities, which enhance signal integrity over diverse transmission paths. It offers multiple data width configurations, including 16-bit and 40-bit, providing designers with enhanced versatility to tailor to specific system requirements. The SERDES is available in multiple variants that are designed to eliminate external components, simplifying system integration and improving reliability. Its robust design supports various packaging options and channel configurations, making it ideal for networking applications where high throughput and reliability are paramount.
Brite's YouMIPI interfaces facilitate high-speed data transfer for camera sensors and display modules. This versatile solution supports both CSI and DSI protocols, making it suitable for a wide range of multimedia applications. The YouMIPI series includes advanced configurations for data transfer through MIPI standards, emphasizing reduced electromagnetic interference and data scrambling capabilities for signal integrity. It leverages standard PPI interfaces to seamlessly connect MIPI PHY and control units, providing robust support for varied image formats and resolutions. Focused on adaptability, the YouMIPI design accommodates numerous lane configurations, thus enhancing support for high throughput data channels. This flexibility ensures compatibility with different display and camera configurations, making it an ideal choice for advanced multimedia and imaging solutions.
The DisplayPort 1.4 core stands out as an ideal solution for DisplayPort requirements. It is designed to be compact and easy-to-use, facilitating both source (DPTX) and sink (DPRX) functionalities. Notably, it supports link rates of 1.62, 2.7, 5.4, and 8.1 Gbps, making it compatible with a variety of link conditions. Additionally, it accommodates 1, 2, and 4 DP lanes, with native support for video via AXI stream interfaces. The IP's versatility extends to both Single Stream Transport (SST) and Multi Stream Transport (MST) modes, meaning it can manage dual and quad pixel clocks efficiently. This comprehensive solution supports secondary data packet interfaces essential for audio and metadata transport, maintaining its high performance across different video and color spaces. Its compatibility with various FPGA devices, including AMD's UltraScale+ and Artix-7, and Intel's Cyclone 10 GX, underscores its adaptability. Integration is simplified with a thin host driver and an intuitive API, thereby ensuring seamless implementation in diverse systems. Users who require further customization and control over the IP can access the source code on Parretto's GitHub. Detailed documentation supports developers through the features, configurations, and reference designs, ensuring that users can fully exploit the potential of this robust IP core.
The MIPI D-PHY Analog Transceiver by Arasan is an essential IP for implementing high-speed data links in mobile and consumer electronics. Its design allows for efficient interfacing with camera and display panels by complying with the MIPI standards for CSI-2 and DSI. Featuring a configurable transceiver design, this IP can operate as both a transmitter and receiver, providing flexibility in design applications. Supporting data rates up to 2.5Gbps per lane, it ensures stable and rapid data transfer while minimizing power consumption and chip area. The IP is also engineered for adaptability, porting to various foundry processes, and can be implemented across a multitude of devices, from smartphones to in-car infotainment systems. Its support for both high-speed and low-power modes allows it to cater to diverse application needs.
This solution integrates support for both the Camera Serial Interface (CSI-2) and the Display Serial Interface (DSI). The D-PHY Universal PHY configuration permits it to act as a transmitter, receiver, or transceiver. The design includes an analog front end to manage electrical signal levels and a digital interface for I/O control, facilitating seamless video and imaging applications.
MIPI Interface IP by Analog Circuit Works stands as a robust solution for mobile and camera applications, offering comprehensive support for various interfaces like the Camera Serial Interface (CSI) and Display Serial Interface (DSI). It is a versatile choice that underpins a broad range of communication standards on top of the MIPI PHY layer.\n\nAdaptable to different system requirements, this IP ensures high performance and seamless integration across mobile devices, featuring efficient signal processing that enhances data handling and transmission. Its design maintains compatibility with a multitude of mobile standards, thus facilitating ease of use and quicker implementation.\n\nBy integrating MIPI Interface IP, developers can optimize communication protocols, achieving higher throughput and reliability, essential for state-of-the-art mobile and imaging technologies.
The Multi-Protocol SERDES offered by Pico Semiconductor serves high-speed and versatile data communication requirements. These SERDES cores are capable of operating at speeds ranging from 1-32Gbps, tailored for protocols like XAUI, RXAUI, and SGMII. They are adaptable to various process nodes, such as 40nm and 65nm from TSMC and GLOBALFOUNDRIES, ensuring integration flexibility across different technology platforms.\n\nThis SERDES lineup emphasizes high data rates with efficient power consumption, combining low jitter performance with wideband capabilities. Each channel configuration—ranging from single to multi-channel setups—addresses specific customer needs, enhancing integration options for complex systems like networking and telecommunications equipment.\n\nBy utilizing these SERDES solutions, designers can achieve high data throughput while maintaining signal integrity, benefiting applications that demand rigorous data transmission performance. They are essential for modern communication systems that require robust and efficient data exchange at multiple levels.
Eliyan’s NuLink Die-to-Die (D2D) PHY technology is designed to revolutionize the interconnection of chiplets using industry-standard packaging techniques. This technology offers low power consumption while maintaining high-performance metrics, seamlessly integrating into both standard and advanced packaging options. Eliyan's D2D IP allows for significant flexibility in application design and reduces the dependency on complex silicon interposer technologies. By using standard organic/laminate packages, the NuLink technology enhances system-level design optimizations, cost savings, and thermal performance. Support for numerous industry standards, including UCIe and BoW, ensures a versatile application in a wide array of semiconductor designs. The tailored PHY IP cores facilitate the incorporation of high-bandwidth interconnected systems within ASICs without the necessity of proprietary packaging methods. With up to 64 data lanes and bump map layouts adaptable to specific protocols, the NuLink D2D PHY exemplifies adaptable technology suitable for various semiconductor applications. This unique approach allows for greater design flexibility, mixing and matching chiplets with different dimensions, which is particularly beneficial in applications involving high bandwidth and low latency requirements. The ability of the NuLink D2D technology to deliver interposer-like bandwidth and power without high-cost advanced packaging makes it a remarkable solution in cutting-edge chip design.
SystemBIST is a sophisticated, vendor-independent plug-and-play IC tailored for the flexible configuration of FPGAs on PCBs. The aim of this solution is to simplify the FPGA configuration and testing processes by eliminating the need for PROMs and complex firmware. SystemBIST utilizes the IEEE 1149.1 and IEEE 1532 standards, ensuring broad applicability across different vendor products while maintaining high quality and configuration flexibility.\n\nThe hallmark of SystemBIST is its ability to execute deterministic Built-In Self Test (BIST) for PCBs and system-level components. This significantly simplifies the testing process as embedded test patterns and scripts can be reused, providing reliable testing scenarios without additional software efforts. SystemBIST’s capabilities extend beyond FPGA programming, enabling re-programming and testing of CPLDs and other components in the field, ensuring products remain adaptable and secure.\n\nWith comprehensive support from Intellitech’s Eclipse Test Development Environment, SystemBIST provides a centralized framework for the generation, validation, and application of test suites, integrating seamlessly with existing system configurations. This capability is complemented by SystemBIST’s robust anti-tamper and counterfeit protection, featuring embedded security measures to safeguard the integrity of designs.
The C100 is a highly integrated, low-power IoT SoC chip designed to implement control and interconnection functionalities. It incorporates an advanced 32-bit RISC-V CPU, clocked at up to 1.5GHz, with embedded RAM and ROM for enhanced computational efficiency and capability. This chip integrates multiple transmission interfaces including Wi-Fi, and features components such as ADC, LDO, and temperature sensors, making it suitable for a broad range of IoT applications. Designed to facilitate simpler, faster, and wider application development, the C100 aims to offer high efficiency processing capabilities.