All IPs > Interface Controller & PHY > AMBA AHB / APB/ AXI
AMBA, which stands for Advanced Microcontroller Bus Architecture, is a far-reaching and well-established open-standard, on-chip interconnect specification used widely in the design and structuring of system-on-chip (SoC) technologies. Among the most popular protocols under this architecture are AHB (Advanced High-performance Bus), APB (Advanced Peripheral Bus), and AXI (Advanced eXtensible Interface). These protocols facilitate effective communication between various components of a digital system, ensuring optimal performance and scalability.
**AHB, APB, and AXI Semiconductor IPs**
*AMBA AHB* is specifically designed for high-performance and high-bandwidth requirements. It's a parallel bus interface that is commonly employed for connecting processors and other high-speed components in a SoC. AHB IPs ensure that data is transferred efficiently across the components, making them ideal for applications where speed and reliability are crucial.
*AMBA APB* is tailored for low power and less complex communication needs. It is often used for interfacing with peripheral devices that do not require high throughput, such as UARTs or low-speed memory controllers. APB semiconductor IPs are valued for their simplicity and low power consumption, often being the choice for battery-operated or portable devices.
*AMBA AXI* is characterized by its advanced features, supporting high data bandwidth and flexible configurations. AXI IPs are used where the highest performance is needed, leveraging features like burst transactions, multiple outstanding addresses, and out-of-order transaction completion, making it suitable for complex and demanding tasks.
Integrating these semiconductor IPs into your system ensures that you leverage their specialized features for increased efficiency and performance. In products that require robust, flexible, and scalable communication channels, AMBA interface controllers and PHYs provide the backbone necessary to build systems that can meet current and future demands.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
eSi-Connect is a sophisticated networking solution designed to enhance the communication efficiency between eSi-RISC cores and their peripherals. Utilizing the AMBA protocol, it provides seamless interconnections across processors, memory controllers, and various peripheral devices. This results in a streamlined design process and reduced complexity during system integration. Leveraging industry-standard architectures, eSi-Connect ensures that a wide range of third-party IP cores can be integrated smoothly, providing flexibility and choice in design customization. Its design optimally supports the scalability and compatibility requirements of complex embedded systems. eSi-Connect's robust framework is crafted to support a myriad of applications, from simple control systems to multiprocessor platforms requiring advanced data throughput and low latency. This adaptability makes it a pivotal component in the design of modern embedded systems, facilitating enhanced system performance and efficiency.
The SerDes Interfaces from Silicon Creations feature cutting-edge capabilities for high-speed serial data transmission in semiconductor devices. Supporting a vast range of industry protocols, these interfaces offer both flexibility and performance, making them ideal for varied high-bandwidth applications. These interfaces accommodate rates from as low as 100Mbps to an impressive 32.75Gbps, covering a wide spectrum of technologies from JESD204 to PCIe and V-by-One. They include programmable serialization and deserialization features, along with advanced techniques for reducing latency, ensuring the rapid delivery and reception of data streams. Built on proven IP platforms, the SerDes interfaces integrate advanced PLLs to manage jitter and power consumption effectively. With adaptability to a multitude of fabrication nodes, these solutions meet the diverse needs of networked devices and high-speed interconnects, showcasing Silicon Creations’ expertise in providing industry-leading communication solutions.
This LPDDR4/4X/5 Secondary/Slave PHY provides sophisticated memory-side interfacing capabilities that support AI processors and next-gen ASIC designs. It effectively integrates with devices requiring high-speed, low-power LPDDR communication, aligning with international JEDEC standards. While designed for usage on TSMC's 7nm technology, this IP can adapt to other processes, expanding its scope across advanced and emerging memory technologies such as DRAM and various non-volatile options.
Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus transaction. It also produces error messages for empty addresses in the hierarchy.
The AHB-Lite APB4 Bridge from Roa Logic is a parameterized soft IP bridge designed to facilitate communication between AMBA AHB-Lite and APB protocols. This bridge serves as a crucial component in systems requiring seamless integration of different bus architectures. It translates signals between the AHB-Lite and APB protocols, ensuring compatibility across a range of devices and subsystems. As a versatile interconnection solution, this bridge is essential for systems that incorporate various peripherals and require efficient bus communication. It is optimized for low latency and high throughput, offering robust support for dynamic and static systems. This bridge is invaluable in enhancing data flows and maintaining system integrity in multi-bus designs. The AHB-Lite APB4 Bridge simplifies the integration of peripherals, making it easier for system architects to design adaptable and efficient systems that meet their specific performance requirements. Its parameterized nature allows customization to suit varying project needs, ensuring flexibility and enhanced functionality.
The Origin E1 is a highly efficient neural processing unit (NPU) designed for always-on applications across home appliances, smartphones, and edge nodes. It is engineered to deliver approximately 1 Tera Operations per Second (TOPS) and is tailored for cost- and area-sensitive deployment. Featuring the LittleNPU architecture, the Origin E1 excels in low-power environments, making it an ideal solution for devices where minimal power consumption and area are critical. This NPU capitalizes on Expedera's innovative packet-based execution strategy, which allows it to perform parallel layer execution for optimal resource use, cutting down on latency, power, and silicon area. The E1 supports a variety of network types commonly used in consumer electronics, including Convolutional Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and more. A significant advantage of Origin E1 is its scalability and market-leading power efficiency, achieving 18 TOPS/W and supporting standard, custom, and proprietary networks. With a robust software stack and support for popular AI frameworks like TensorFlow and ONNX, it ensures seamless integration into a diverse range of AI applications.
The Origin E8 neural processing unit (NPU) stands out for its extreme performance capabilities, designed to serve demanding applications such as high-end automotive systems and data centers. Capable of delivering up to 128 TOPS per core, this NPU supports the most advanced AI workloads seamlessly, whether in autonomous vehicles or data-intensive environments. By employing Expedera's packet-based architecture, Origin E8 ensures efficient parallel processing across layers and achieves impressive scalability without the drawbacks of increased power and area penalties associated with tiled architectures. It allows running extensive AI models that cater to both standard and custom requirements without compromising on model accuracy. The NPU features a comprehensive software stack and full support for a variety of frameworks, ensuring ease of deployment across platforms. Scalability up to PetaOps and support for resolutions as high as 8K make the Origin E8 an excellent solution for industries that demand unrivaled performance and adaptability.
The Origin E2 is a versatile, power- and area-optimized neural processing unit (NPU) designed to enhance AI performance in smartphones, edge nodes, and consumer devices. This NPU supports a broad range of AI networks such as RNNs, LSTMs, CNNs, DNNs, and others, ensuring minimal latency while optimizing for power and area efficiency. Origin E2 is notable for its adaptable architecture, which facilitates seamless parallel execution across multiple neural network layers, thus maximizing resource utilization and providing deterministic performance. With performance capabilities scalable from 1 to 20 TOPS, the Origin E2 maintains excellent efficiency up to 18 TOPS per Watt, reflecting its superior design strategy over traditional layer-based solutions. This NPU's software stack supports prevalent frameworks like TensorFlow and ONNX, equipped with features such as mixed precision quantization and multi-job APIs. It’s particularly suitable for applications that require efficient processing of video, audio, and text-based neural networks, offering leading-edge performance in power-constrained environments.
The UART Serial Communication Controller is engineered to provide reliable asynchronous data transmission between processors and peripheral devices. The design includes support for variable data rates, ensuring flexibility in communication demands across different operational scenarios. This versatility makes it suitable for embedded systems where diverse data types and throughput requirements are needed. It supports the integration of various peripheral devices, thus enhancing the capability and scalability of the communications architecture within complex systems.
The UDP Offload Engine by Intilop showcases the company’s commitment to enhancing data throughput via hardware acceleration. Designed to manage UDP protocols efficiently, this engine assists in reducing system overheads, thereby enhancing network performance substantially. Tailored for environments that heavily rely on UDP traffic, such as video streaming and real-time data analytics, this engine ticks all the right boxes by delivering low-latency data handling and release from conventional CPU processing tasks. It provides a significant leap forward in terms of efficiency, as UDP traffic typically necessitates rapid packet processing. This IP's design is synonymous with robustness, ensuring high availability and sustained throughput in demanding networking scenarios. It marks itself as an essential component for any architect planning to deploy efficient and high-performance UDP-based networking systems.
The PolarFire FPGA Family by Microsemi is engineered to deliver cost-effectiveness alongside exceptional power efficiency, positioning itself as the optimal choice for mid-range FPGA applications. Crafted to offer transceivers ranging from 250 Mbps to a robust 12.7 Gbps, these FPGAs cater to diverse bandwidth requirements. With logic elements spanning 100K to 500K and incorporating up to 33 Mbits of RAM, the PolarFire series seamlessly addresses demanding processing needs while ensuring secure and reliable performance. At the heart of its design philosophy is a focus on best-in-class security features combined with high reliability, making it particularly relevant for industries like automotive, industrial, and communication infrastructures where failure is not an option. It supports applications that require low power consumption without sacrificing performance, which is increasingly important in today's energy-conscious environments. These FPGAs find their versatility in a range of applications, from driving advancements in ADAS in the automotive industry to supporting broadband and 5G mobile infrastructures in telecommunications. The family also extends its use cases to data center technologies, highlighting its adaptability and efficiency in both digital and analog processing fields. With such a broad spectrum of applicability, the PolarFire FPGA Family stands as a shining example in Microsemi's product arsenal, delivering solutions tuned for innovation and performance.
The Multi-Channel Flex DMA IP Core offers an adaptable solution for handling up to 16 streaming channels, each managed independently to prevent mutual obstruction. Users can customize the data rate for each channel to optimize interfacing simplicity while incorporating prioritized FIFO buffers to ensure crucial data streams maintain supremacy. Designed with streaming and co-processor applications in mind, this IP core reads data from any source, processes it, and disseminates it to designated targets. Additionally, the core includes mechanisms for monitoring CRC errors along PCI Express links, enabling the prompt identification and exclusion of assemblies with subpar signal integrity during production testing. This core is paramount in safety-critical applications, where signal integrity and real-time data management are vital, offering high reliability and responsiveness in demanding environments. Its blend of efficiency and precision makes it a favorite for being able to swiftly adapt to varied processing needs without compromising on performance quality.
The ABX Platform by Racyics utilizes Adaptive Body Biasing (ABB) technology to drive performance in ultra-low voltage scenarios. This platform is tailored for extensive applications requiring ultra-low power as well as high performance. The ABB generator, along with the standard cells and SRAM IP, form the core of the ABX Platform, providing efficient compensation for process variations, supply voltage fluctuations, and temperature changes.\n\nFor automotive applications, the ABX Platform delivers notable improvements in leakage power, achieving up to 76% reduction for automotive-grade applications with temperatures reaching 150°C. The platform's RBB feature substantially enhances leakage control, making it ideal for automotive uses. Beyond automotive, the ABX Platform's FBB functionality significantly boosts performance, offering up to 10.3 times the output at 0.5V operation compared to non-bias implementations.\n\nExtensively tested and silicon-proven, the ABX Platform ensures reliability and power efficiency with easy integration into standard design flows. The solution also provides tight cornering and ABB-aware implementations for improved Power-Performance-Area (PPA) metrics. As a turnkey solution, it is designed for seamless integration into existing systems and comes with a free evaluation kit for potential customers to explore its capabilities before committing.
The Origin E6 NPU is engineered for high-performance on-device AI tasks in smartphones, AR/VR headsets, and other consumer electronics requiring cutting-edge AI models and technologies. This neural processing unit balances power and performance effectively, delivering between 16 to 32 TOPS per core while catering to a range of AI workloads including image transformers and point cloud analysis. Utilizing Expedera’s unique packet-based architecture, the Origin E6 offers superior resource utilization and ensures performance with deterministic latency, avoiding the penalties typically associated with tiled architectures. Origin E6 supports advanced AI models such as Stable Diffusion and Transformers, providing optimal performance for both current and predicted future AI workloads. The NPU integrates seamlessly into chip designs with a comprehensive software stack supporting popular AI frameworks. Its field-proven architecture, deployed in millions of devices, offers manufacturers the flexibility to design AI-enabled devices that maximize user experience while maintaining cost efficiency.
Intilop's 10G TCP Offload Engine epitomizes advanced network throughput technology through its ultra-low latency mechanisms. This engine is engineered to handle high-frequency data transactions with little to no delay, rendering it ideal for data center environments, cloud computing, and communication sectors where immediate data access and processing are critical. The ingress and egress latency is minimized, bringing forth seamless data flows that rival traditional software-driven networking solutions. This segment of Intilop's engine arsenal supports robust integration within existing infrastructures, maintaining versatility across various network configurations. Tailored for real-time data applications, its proactive offloading mechanism translates into side-stepping CPU-dependent bottlenecks, optimizing both performance and network resilience.
The eSPI Master/Slave Controller effectively conforms to the Enhanced SPI specification, providing programmable functionality for master/slave configurations. With compliance to eSPI Bus Protocols, it supports various hardware interconnects, including AMBA AXI and AHB, making it suitable for both low and high-performance embedded systems. The controller is designed to address diverse operational needs, from consumer electronics to automotive applications, where reliability and accuracy in data transfers are critical. Its versatile architecture supports flexible deployment in complex system environments, enhancing communication efficiency across integrated networks.
The AXI Bridge for PCIe is a versatile Smartlogic solution featuring up to four AXI4 interfaces. This IP core seamlessly translates AXI read and write commands into PCIe Transaction Layer Packets, maintaining continuous parallel operations across all interfaces with zero interference. Unused interfaces can be deactivated to conserve logical resources, highlighting its efficiency-oriented design. The inclusion of a high-performance kernel mode driver enhances its operability on Windows and Linux systems, paving the way for easy software integration. This characteristic allows users to transfer payloads without delving into the complexities of PCIe packet formation. Ideal for various applications, especially in networking, this component provides dependable solutions where high throughput and low-latency data interactions are essential. It stands out for its ability to support dynamic Ethernet applications, ensuring that network environments function optimally at all times.
The Multi-Channel AXI DMA Engine excels in bridging AXI Stream and AXI Memory mapped operations, managed by a potent DMA engine. Capable of processing data from 16 AXI Stream Slave inputs, it ensures efficient data writing and reading into DDR memories. AXI Stream Masters can extract information, enabling further DSP processing across multiple streams. The inclusion of programmable address generators allows non-linear data storage, simplifying the retrieval process for algorithmic units by categorizing data in easily manageable sections or Regions of Interest (ROI). This functionality greatly aids subsequent data sorting and processing activities. By facilitating compatibility with GStreamer and offering Linux driver support, this IP core is versatile for use in SoC-based environments that demand seamless data handling and processing. Its adaptability extends to non-SoC FPGAs requiring efficient DDR data buffering, making it indispensable for a wide array of data-intensive digital environments.
The SPI Master/Slave Controller by Digital Blocks is crafted for seamless integration into systems requiring robust serial data exchange. This Verilog IP core supports both master and slave operations over AMBA AXI, AHB, or APB interfaces. The architecture is optimized for efficient communication with external SPI master or slave devices, ensuring reliable data transfers in various industrial and consumer applications. Its adaptable design is particularly suited for environments where multi-faceted peripheral interfaces are necessary, facilitating complex system integrations with multiple SPI-enabled components.
The AXI Bridge with DMA for PCIe from Smartlogic is engineered for high-performance data transfer applications, providing an array of industry-standard AXI interfaces. Designed to handle complex data streaming from FPGA to Host or vice versa, this IP core supports concurrent operations across all interfaces without interference. Its smart design allows for easy access to remote memory locations for shared and peer-to-peer memory applications. This product is notable for its ability to manage continuous data flow effectively, making it ideal for developers crafting sophisticated PCIe endpoints without deep protocol expertise. The inclusion of a kernel mode driver for Windows and Linux ensures smooth software integration, simplifying the deployment in diverse operating systems. Such integration allows developers to focus on transmitting raw data rather than crafting compliant PCIe packets, reducing complexity and development time. The core is especially valuable in network applications, where seamless Ethernet compatibility is crucial. Its robustness makes it well-suited for applications needing reliable data exchange and control over extensive data transactions, particularly in environments demanding high processing throughput and modular expansion capabilities.
The AXI4 DMA Controller is a multi-channel Verilog RTL IP core that manages data transfers with exceptional throughput across several large and small data sets. Supporting configurations from 1 to 16 channels, it features independent DMA Read and Write Controllers, utilizing AXI3 and AXI4 protocols to ensure efficient data handling across memory and peripherals. Its design accommodates intricate data transfer requirements, offering features such as scatter-gather linked lists and user-defined AXI burst lengths up to 256 beats. The DMA controller is adept in facilitating multiple concurrent data streams, enhancing performance for high-bandwidth applications.
The CANmodule-IIIx is an enhanced version of the traditional CAN controller, featuring an extensive set of 32 receive and 32 transmit buffers. This setup is particularly beneficial for applications demanding high-capacity data management and robust error handling. The module’s structure supports mailboxes with a prioritized arbitration mechanism, offering flexibility for advanced application-specific configurations.<br/><br/>Compliant with the CAN 2.0A/B standards and designed in an HDL that is adaptable to both FPGA and ASIC technologies, the CANmodule-IIIx includes on-chip SRAM to facilitate efficient data handling. It integrates seamlessly into ARM-based SoCs through its AMBA 3 Advanced Peripheral Bus, providing a high-performance, fully synchronous system interface.<br/><br/>Key features include single-shot transmissions, automatic RTR interrupt handling, and sophisticated message filtering capabilities that encompass ID, IDE, RTR, and initial data bytes. Outstanding for areas like aerospace and industrial automation, the CANmodule-IIIx ensures data integrity and responsiveness via its programmable interrupt controller and comprehensive test modes.
The I/O solutions provided by Analog Bits focus on delivering low-power, high-efficiency differential clocking and signaling capabilities. These IPs are designed for minimized transistor count while maintaining superior signaling quality, making them optimal for die-to-die communication. Customization is a key benefit, allowing for client-specific architectural arrangements that suit their exact needs while utilizing the smallest possible area and power budget.
The AHB-Lite Multilayer Switch by Roa Logic is a high-performance interconnect solution that facilitates robust communication across multiple masters and slaves in an AMBA-based architecture. This switch is engineered to handle high data throughput while maintaining low latency, making it ideal for sophisticated system-on-chip (SoC) designs. The architecture of the AHB-Lite Multilayer Switch allows for parallel data processing, ensuring that each master-slave pair can communicate without interference from other pairs. This capability significantly boosts system efficiency and performance, accommodating a wide spectrum of applications that demand rapid data transfer and efficient communication protocols. Equipped with flexible configuration options, this switch supports an unlimited number of bus masters and slaves. This scalability is crucial for designs targeting growth in complexity and function, enabling seamless expansion and system upgrades. This switch is, therefore, an excellent choice for future-proofing new designs against the steadily increasing data processing demands of advanced electronics.
The CANmodule-III is a sophisticated controller core that introduces a mailbox approach to CAN data handling. Conforming to the ISO 11898-1 standard, it boasts 16 receive buffers, each with a dedicated message filter, and 8 transmit buffers, featuring a prioritization system. This structure caters to advanced higher-layer protocols, making it ideal for applications requiring nuanced data management such as those in industrial automation or automotive communications.<br/><br/>Designed in a technology-independent HDL, it is compatible with both FPGA and ASIC platforms, leveraging on-chip SRAM for optimized performance. The integration with ARM-based SoC environments is facilitated by an AMBA 3 Advanced Peripheral Bus interface. This fully synchronous zero wait-state bus interface supports seamless connections to other system buses, thus enabling high throughput and low latency communications.<br/><br/>The CANmodule-III's robust architecture includes features like single-shot transmission, automatic RTR response management, and a comprehensive error capture system. The full suite of debugging capabilities includes loops and listen-only mode, ensuring that developers can maintain control over communication channels throughout the product lifecycle.
The MIPI CSI2MUX-A1F is a CSI2 Video Multiplexer designed to aggregate inputs from up to four CSI2 cameras into a single output stream. Compliant with CSI2 rev 1.3 and DPHY rev 1.2, this video multiplexer can manage data transmission at 4 x 1.5Gbps. It's perfect for applications requiring efficient conversion from multiple image sources to a consolidated feed.
Secure Protocol Engines are high-performance IP solutions tailored to manage intensive network and security operations. These IP blocks are designed to handle offloading of network processing tasks, enhancing system efficiency and performance. With integration ease and high compatibility across systems, they offer robust security by accelerating cryptographic protocols immensely necessary in today’s fast-paced digital environments.
The APB4 Multiplexer from Roa Logic is a sophisticated switching component that enables communication between a single APB4 master and multiple APB4 slaves through a unified bus interface. This multiplexer is a critical element in systems where multiple peripherals must be accessed efficiently by a single control unit. Designed for optimal performance, the APB4 Multiplexer ensures signal integrity and efficient routing, effectively managing the data flow between varied modules. The multiplexer's ability to handle multiple slaves simultaneously makes it indispensable for complex embedded systems where flexibility and scalability are vital. By simplifying the bus architecture and driving innovation in system designs, the APB4 Multiplexer provides a cost-effective solution that minimizes resource usage while maximizing system performance. This makes it an attractive choice for system architects looking to optimize their designs without sacrificing functionality and speed.
The Arria 10 System on Module (SoM) is designed with an emphasis on embedded and automotive vision applications. This compact module leverages Altera's Arria 10 SoC devices in a sleek 29x29 mm package, offering a plethora of interfaces while maintaining a small, efficient form factor. It features an Altera Arria 10 SoC FPGA with a range from 160 to 480 KLEs, coupled with a Cortex A9 Dual-Core CPU. This enables robust integration and performance for demanding applications. The module's power management system ensures a seamless power-up and -down sequence, requiring only a 12V supply from the baseboard. Its dual DDR4 memory interfaces provide up to 2.4 Gbit/s per pin, offering a total bandwidth of up to 230 Gbit/s for both CPU and FPGA memory systems. This module supports a wide array of high-speed interfaces, including PCIe Gen3 x8, 10/40 Gbit/s Ethernet, DisplayPort, and 12G SDI, making it suitable for complex imaging and communication tasks. Additional features include up to 32 LVDS lanes for configurable RX or TX, two USB interfaces with OTG support, and ARM I²C, SPI, and GPIO interface signals. Furthermore, the Arria 10 SoM includes pre-configured IP for memory controllers and an Angstrom Linux distribution, facilitating rapid development and deployment of applications.
The Exostiv Blade is designed for advanced FPGA debugging and validation, offering deep, high-speed data capture capabilities across multiple FPGAs. It supports up to 800 MHz sampling speeds and immense data bandwidth of up to 4.5 Tbps. Its architecture allows data capture from multiple FPGA nodes, with up to 5.12 TB of trace storage in a single unit. This system suits scenarios requiring extensive node visibility and is scalable, adaptable to numerous FPGA prototyping systems, providing remote access capabilities for comprehensive data analysis across diverse environments. The Blade can effectively manage pre-silicon and complex multi-FPGA systems testing, offering insights from millions of capture nodes using advanced triggering and data qualification methods.
The High-Channel-Count DMA IP Core is specialized for memory-intensive applications demanding high throughput, accommodating up to 64 data streams. It efficiently allocates streams within distinct host memory regions via DMA while facilitating user logic interfacing through up to 8 AXI4 (Full/Lite) masters. In addition to supporting data reading with up to 16 AXI Stream masters, this core simplifies the development of complex PCIe endpoints by enabling users to focus solely on data payloads, eliminating the need for intricate PCIe packet management. This capability makes it ideal for data-intensive operations such as streaming, Ethernet applications, and high-level computations. The IP core is equipped for Ethernet compatibility and comes with a detailed schematic to assist in implementation, ensuring that network congestion or interruptions have minimal impact on its performance. It is designed to support high-performance data handling and fast processing for real-time applications.
The MIPI SVRPlus-8L-F is an advanced 8-lane, second-generation Serial Video Receiver designed specifically for FPGA applications. It supports CSI2 rev 2.0 and DPHY rev 1.2, allowing it to handle high-speed data transmission efficiently. The receiver can manage 16 virtual channels and provides 4 pixels output per clock cycle, complete with calibration support. Furthermore, it includes communication error statistics to ensure reliability.
The MIPI SVTPlus-8L-F is an innovative 8-lane, second-generation Serial Video Transmitter crafted for FPGA contexts. It aligns with CSI2 rev 2.0 and DPHY rev 1.2 standards, ensuring robust and efficient data transmission. Operating at a remarkable speed of 12Gbps, this transmitter is optimized for high-performance environments where precision and speed are paramount.
Spec-TRACER is a powerful tool for managing the lifecycle of FPGA and ASIC requirements. It provides a unified platform for capturing, managing, and tracing requirements, making complex designs more manageable and traceable throughout their lifecycle. This tool is specifically tailored to comply with stringent industry standards for user and design requirements, aligning with hardware and software deliverables. By facilitating clear requirement management, Spec-TRACER ensures thorough traceability and accountability, reducing risks of design deviations and enhancing communication across development teams. This results in a streamlined workflow where requirements can be easily documented, tracked, and matched with design outputs effectively. Spec-TRACER excels in capturing detailed analyzes and facilitating robust reporting, aligning closely with processes required in domains such as aerospace and defense. Its capacity to support comprehensive requirements management protocols makes it indispensable for projects demanding high levels of compliance and verification rigor, ultimately enhancing the quality and reliability of final products.
The CANmodule-IIx is a FIFO-based CAN controller designed for streamlined integration within FPGA and ASIC systems. This IP core complies fully with the CAN 2.0A/B standard and supports ISO 11898-1 compliance, making it a reliable choice for various communication needs in automotive and industrial applications.<br/><br/>Incorporating advanced message filtering, the CANmodule-IIx is equipped with three fully programmable filters, alongside a 32-message receive FIFO and a 16-message transmit FIFO. This allows the module to efficiently process and prioritize a wide range of messages, bolstered by a high-priority transmit buffer that can bypass the traditional FIFO path for critical communications.<br/><br/>Integration into ARM-based SoCs is facilitated via its AMBA APB interface, allowing seamless connectivity within complex system architectures. The CANmodule-IIx's design supports testing and debugging capabilities, including loopback modes and a dedicated SRAM-based message buffer, ensuring reliability and ease of use across its deployment.
Exostiv is engineered for massive data capture within FPGA systems, allowing monitoring and visualization of internal signals in real-time. It supports probes with up to 65 Gbps bandwidth and high-speed transceiver connections. A robust tool for FPGA design environments, Exostiv is adaptable to any prototyping board and significantly reduces the risk of FPGA bugs reaching production. With its vibrant software environment, Exostiv allows flexible manipulation of capture data, integrates Exostiv Core Inserter for IP management, and helps engineers flawlessly assess design authenticity in real-world fences.
The Metis AIPU PCIe AI Accelerator Card represents a powerful computing solution for high-demand AI applications. This card, equipped with a single Metis AI Processing Unit, delivers extraordinary processing capabilities, reaching up to 214 Tera Operations Per Second (TOPS). Designed to handle intensive computing tasks, it is particularly suited for applications requiring substantial computational power and rapid data processing, such as real-time video analytics and AI-driven operations in various industrial and retail environments. This accelerator card integrates seamlessly into PCIe slots, providing developers with an easy-to-deploy solution enhanced by Axelera AI's Voyager Software Development Kit. The kit simplifies the deployment of neural networks, making it a practical tool for both seasoned developers and newcomers to AI technology. The card's power efficiency is a standout feature, aimed at reducing operational costs while ensuring optimal performance. With its innovative architecture, the Metis AIPU PCIe AI Accelerator Card not only meets but exceeds the needs of modern AI applications, ensuring users can harness significant processing power without the overheads associated with traditional systems.
The I2C Master/Slave Controller is a robust IP core that integrates a microprocessor to an I2C bus using various AMBA bus interfaces. Designed to support various speeds, including Standard-mode and High-speed mode, it embraces features from the latest I2C specifications by NXP. The controller is optimized for seamless integration into a diverse range of applications, ensuring high reliability and performance. This makes it ideal for use in systems requiring complex interfacing and control, extending from consumer electronics to sophisticated industrial environments.
The MIPI SVRPlus2500 is a sophisticated 4-lane video receiver that adheres to CSI2 rev 2.0 and DPHY rev 1.2 standards. Designed to support low clock ratings for simpler timing closure, it offers PRBS support and outputs 4/8/16 pixels per clock. This receiver incorporates 16 virtual channels and 1:16 input deserializers per lane, making it a versatile choice for intricate video applications. Handling data rates up to 4 x 2.5Gbps, it is built for high-efficiency environments.
The SafeIP TriplePHY represents the pinnacle of Siliconally’s technology in safe communication solutions, elevating the standard for IEEE 802.3 compliant systems. As an extension of the DualPHY capabilities, this offering provides an additional channel, strengthening secure communication pathways within highly automated and sophisticated system environments. It caters to industries that rely heavily on rapid, real-time data transmission and demands seamless error detection to maintain operational efficacy.\n\nThe TriplePHY harnesses the power of GlobalFoundries 22FDX, an advanced platform known for its high-performance, energy-efficient attributes. This underlying technology equips the TriplePHY with ultra-low latency and exceptional signal reliability, necessary for maintaining integrity in critical communication systems. Siliconally's dedication to rigorous testing ensures this IP remains silicon-proven and highly adaptable across various technology nodes.\n\nWith its introduction, the product redefines the benchmarks in safety-critical communication, accommodating multiple parallel data streams without compromising on speed or accuracy. It is engineered to react swiftly to erroneous data in milliseconds, thus safeguarding against potential system niggles before they escalate. Adhering to ISO 26262, the TriplePHY stands as a premier choice for sectors like autonomous driving, aerospace, and heavy industrial operations.\n\nThis solution not only enhances operational safety but also advances system integration processes through its compatibility with market standards. Its three-channel advantage enhances redundancy and data path integrity, aligning with Siliconally's vision of providing cutting-edge safety solutions where milliseconds matter.
Designed for high-performance networking, this 10G TCP Offload Engine integrates with a MAC and supports ultra-low latency interactions with PCIe and Host IF. Its principal feature is streamlining TCP processing, which sources hefty gains in throughput while diminishing CPU workload. This optimization is paramount in applications requiring real-time processing and heightened bandwidth efficiency. The engine showcases superior determinism and minimal jitter, offering robust TCP offloading that facilitates the deployment of high-speed networks efficiently and reliably. By utilizing offload techniques, users can achieve throughput that scales impressively across a variety of infrastructures, stretching from enterprise data centers to edge computing setups. With its seamless integration and proven reliability, this offload engine is a boon for enterprises looking to bolster their network infrastructure against evolving data challenges.
The MIPI SVTPlus2500 is an advanced 4-lane video transmitter that uses CSI2 rev 2.0 and DPHY rev 1.2 protocols. Optimized for easy timing closure through its low clock rating, it includes PRBS support and can handle 8/16 pixel input per clock. With the capability to manage 16 virtual channels at a speed of 4 x 2.5Gbps, this transmitter is ideal for dynamic video environments that demand flexibility and precise programmable timing parameters.
The PCI-Express PHY Core offers a low-power, scalable transceiver solution compliant with PCI-Express Base Specification 1.0a and PIPE interface standards. It is uniquely designed to provide modular implementations that optimize silicon area, offering a full range of multi-lane functionality for various applications. The PHY contains both PMA and PCS layers of the PCI-Express networking layers, interfacing efficiently with the MAC layer. It features an advanced clock recovery architecture ensuring robust performance in noisy environments and supports a variety of processes, making it adaptable to differing manufacturing needs.
The Ultra-Low Latency (ULL) 10GE PHY+MAC core from Algo-Logic is engineered for 10 Gigabit Ethernet applications demanding quick turnaround and precise packet processing. This core is compliant with the IEEE802.3 standards and uniquely supports both local and remote fault detection, making it ideal for critical trading operations. Its architecture offers a significant reduction in system jitter, thus enhancing the overall performance and reliability of trading infrastructure.
VisualSim Architect is a sophisticated software platform dedicated to the modeling and simulation of system performance, power, and functionality. It empowers system engineers to explore designs virtually, measuring potential bottlenecks and power consumption before actual production begins. The platform aids in validating different hardware and software architectures, ensuring that the system is designed for optimal efficiency and performance. It also enables users to create virtual prototypes that mimic real-life system behaviors, thus facilitating a deeper understanding of potential implementation challenges. This preemptive approach allows companies to fine-tune their designs, ensuring that all components work harmoniously, thereby reducing risk and accelerating time-to-market. Furthermore, the platform's flexible system-level modeling capabilities cater to a diverse range of application fields, from automotive to consumer electronics.