All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
The SerDes Interfaces developed by Silicon Creations are optimized for high-speed serial data links, processing speeds up to 32.75Gbps across various protocols. These interfaces provide exceptional flexibility and feature rich configurability to align with specific customer needs in advanced data transmission environments. With PMAs optimized for ultra-low latency and reduced area footprint, the SerDes interfaces demonstrate high efficiency and performance. Leveraging Silicon Creations’ ring PLL technology, these interfaces ensure the delivery of reliable and precise data communication capabilities, pivotal for next-generation electronic solutions.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
This LPDDR4/4X/5 Secondary/Slave PHY provides sophisticated memory-side interfacing capabilities that support AI processors and next-gen ASIC designs. It effectively integrates with devices requiring high-speed, low-power LPDDR communication, aligning with international JEDEC standards. While designed for usage on TSMC's 7nm technology, this IP can adapt to other processes, expanding its scope across advanced and emerging memory technologies such as DRAM and various non-volatile options.
KPIT excels at providing AUTOSAR solutions that streamline software integration and improve vehicle architecture. The company's focus on middleware development ensures efficient application deployment and integration within both classic and adaptive AUTOSAR frameworks. KPIT's solutions enable quick software updates, robust validation processes, and cost-effective production timelines, essential for the evolving landscape of Software-Defined Vehicles (SDVs).
The Connected Vehicle Solutions by KPIT focus on integrating in-vehicle systems with the broader connected world, transforming the cockpit experience. Utilizing high-resolution displays, augmented reality, and AI-driven personalization, these solutions improve productivity, safety, and user engagement. The company's advancements in over-the-air updates facilitate seamless vehicle interactions and connectivity, ushering in new revenue streams for OEMs while overcoming the challenges of system integration and market competitiveness.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features:  Maximum Operating speed of 12.5MHz  Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support  Multi-Time Programmable Non-Volatile Memory Interface  Programmable and DIMM-specific registers for customization  Error log registers for tracking  Packet Error Check (PEC) and Parity Error Check functions  Bus Reset function  Support I3C Basic mode  In-Band Interrupt (IBI) support  Write, read, and default read operations in I2C mode  Error handling for PEC, Parity errors, and CCC errors  I3C Basic Common Command Codes (CCC) support Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
LVDS Interfaces by Silicon Creations are designed to facilitate high-speed and reliable data transmission. These interfaces are suitable for applications requiring efficient chip-to-chip communication, handling data rates up to 3.3Gbps. Featuring bi-directional capabilities and superb programmability, they can support a variety of standards and are engineered to deliver optimal signal integrity. Silicon Creations' use of robust PLLs and adaptive CDR technologies ensures the interfaces provide stable and precise alignment across all lanes. The impressive flexibility and performance of these interfaces make them ideal for a wide spectrum of modern digital applications.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
KPIT provides state-of-the-art solutions for vehicle diagnostics and aftersales service, essential for the maintenance of software-intensive vehicles. The iDART framework offers comprehensive diagnostic functions and enhances service operations through AI-guided systems. This framework facilitates the transition to a unified, future-proof diagnostic ecosystem, reducing downtime and ensuring optimal vehicle performance. KPIT's solutions streamline complex diagnostic processes, making vehicles easier to manage and repair over their lifespans, enhancing customer satisfaction and loyalty.
KPIT's digital solutions harness cloud and edge analytics to modernize vehicle data management, optimizing efficiency and security in connected mobility. With a focus on overcoming data overload and ensuring compliance with regulatory standards, these solutions enable secure and scalable cloud environments for vehicle connectivity. The edge computing aspect enhances system responsiveness by processing data within vehicles, promoting innovation and dynamic feature development.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configura􀆟on. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Op􀆟onal DMA support as plugin module. • Support for alternate nego􀆟a􀆟on protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configura􀆟on. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
The pPLL03F-GF22FDX is a specialized all-digital PLL crafted for performance computing applications. Optimized for use in GlobalFoundries' 22FDX, it delivers low-jitter clocking, suitable for complex SoCs with multiple clock domains. This PLL can handle frequencies up to 4GHz, ensuring high performance for ADC/DAC systems with moderate SNR requirements. Designed with Perceptia's second-generation PLL technology, it offers a compact footprint and minimal power draw, catering to performance computing and critical timing needs. It features fractional multiplication, offering flexible frequency selection, and supports integration into SoCs through standard views and back-end models. The pPLL03F-GF22FDX includes two separately programmable PLL outputs and is equipped with a lock-detect function to enhance system reliability. This technology ensures consistent performance across various process nodes and offers customization and migration support to meet varied technological demands.
The Metis AIPU PCIe AI Accelerator Card provides an unparalleled performance boost for AI tasks by leveraging multiple Metis AIPUs within a single setup. This card is capable of delivering up to 856 TOPS, supporting complex AI workloads such as computer vision applications that require rapid and efficient data processing. Its design allows for handling both small-scale and extensive applications with ease, ensuring versatility across different scenarios. By utilizing a range of deep learning models, including YOLOv5 and ResNet-50, this AI accelerator card processes up to 12,800 FPS for ResNet-50 and an impressive 38,884 FPS for MobileNet V2-1.0. The card’s architecture enables high throughput, making it particularly suited for video analytics tasks where speed is crucial. The card also excels in scenarios that demand high energy efficiency, providing best-in-class performance at a significantly reduced operational cost. Coupled with the Voyager SDK, the Metis PCIe card integrates seamlessly into existing AI systems, enhancing development speed and deployment efficiency.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Pixel to Byte conversion support from Application layer to LLP layer  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern in Data Lane Module  Lane Distribution Function for distributing packet bytes across N-Lanes  Sync word insertion through PPI command in C-PHY physical layer  Insertion of Filler bytes in LLP layer for packet footer alignment  Setting specific bits in packet header  Defining frame blanking period  Seed selection in scrambler and de-scrambler by Sync word  Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports EP & RC. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
WAVE6 is a sophisticated multi-standard video codec designed to handle an array of video standards such as AV1, HEVC, AVC, and VP9. Capable of efficiently managing high-resolution video encoding and decoding processes, WAVE6 offers unmatched performance for applications demanding 4K and 8K resolutions. The technology incorporates a dual-core architecture that doubles operational efficiency and is crucial for high-throughput sectors like data centers and surveillance systems. Key features include support for color depth adaptations ranging from 8-bit to 10-bit and advanced power efficiency mechanisms. The WAVE6 codec is notable for incorporating features such as Chips&Media’s unique lossless frame buffer compression technology, CFrame™, to significantly minimize external memory bandwidth usage. With a streamlined architecture that simplifies video processing tasks, this codec supports multiple interface standards, enhancing your system's scalability and integration. High versatility makes WAVE6 a preferred choice for modern multimedia processing units, providing effective solutions for bandwidth challenges while maintaining superior image quality. WAVE6's efficient resource management and multi-instance capabilities make it a standout product in environments requiring low power consumption and high output precision. It facilitates color space conversion, bit-depth switching, and offers secondary interface options, tailoring it for a diverse range of implementation scenarios, from mobile technology to media broadcasting facilities.
The AHB-Lite APB4 Bridge facilitates connectivity between different bus protocols, specifically the AMBA 3 AHB-Lite and AMBA APB v2.0. As a soft IP, it is parameterized, making it adaptable to various design specifications. This bridge is crucial in systems requiring efficient data transport between high-speed and low-power subsystems, providing a seamless communication interface.
Origin E1 neural engines are expertly adjusted for networks that are typically employed in always-on applications. These include devices such as home appliances, smartphones, and edge nodes requiring around 1 TOPS performance. This focused optimization makes the E1 LittleNPU processors particularly suitable for cost- and area-sensitive applications, making efficient use of energy and reducing processing latency to negligible levels. The design also incorporates a power-efficient architecture that maintains low power consumption while handling always-sensing data operations. This enables continuous sampling and analysis of visual information without compromising on efficiency or user privacy. Additionally, the architecture is rooted in Expedera's packet-based design which allows for parallel execution across layers, optimizing performance and resource utilization. Market-leading efficiency with up to 18 TOPS/W further underlines Origin E1's capacity to deliver outstanding AI performance with minimal resources. The processor supports standard and proprietary neural network operations, ensuring versatility in its applications. Importantly, it accommodates a comprehensive software stack that includes an array of tools such as compilers and quantizers to facilitate deployment in diverse use cases without requiring extensive re-designs. Its application has already seen it deployed in over 10 million devices worldwide, in various consumer technology formats.
Archband Labs offers a PDM-to-PCM Converter that excels in translating Pulse Density Modulated (PDM) audio signals into Pulse Code Modulated (PCM) format. This conversion is crucial in audio signal processing where digital formats require conversions for accurate playback or further audio processing. Ideal for modern multimedia systems and portable audio devices, the PDM-to-PCM Converter provides high fidelity in signal conversion, ensuring sound quality is preserved during the process. This IP is highly efficient, making it perfect for applications where power conservation is important, such as battery-powered gadgets and smart wearables. Its compact design provides easy integration into existing systems, facilitating upgrades without significant redesigns. With reliable performance, this converter supports the growing demand for adaptable and high-efficiency audio processing solutions, aiding engineers in achieving cutting-edge audio clarity.
Spec-TRACER is an integrated requirements lifecycle management application, purpose-built for FPGA and ASIC design environments. It supports the comprehensive management of design specifications and facilitates traceability across the development process, from initial specification capture through verification. This tool is invaluable in projects requiring stringent accountability and regulatory compliance, as seen in aerospace and automotive sectors. It enhances project consistency by ensuring that all design requirements are traceable, verifiable, and adhered to throughout the development phase. With features that allow for detailed analysis, reporting, and change management, Spec-TRACER simplifies the complexity of managing design requirements. Teams can achieve enhanced coordination and transparency, verifying that all specifications are met and documented appropriately, thus utilizing thorough and documented processes for effective project management.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
Silicon Library's HDMI Receiver (Rx) IP is designed to provide a seamless interface for receiving high-definition digital video and audio from HDMI sources. It supports both HDMI 1.4 and 2.0 standards to ensure interoperability with a broad range of HDMI-compliant devices, encompassing applications in consumer electronics and multimedia systems. Engineered for precision and efficiency, the HDMI Rx IP features powerful decoding technology that ensures high fidelity and accurate playback of digital media content. The receiver is tailored for environments that require robust handling of HD and UHD content, offering enhanced image and sound capabilities to deliver an immersive viewing experience. The HDMI Rx offers adaptive equalization and clock signal management to maintain signal integrity at various transmission distances. With its low-power architecture and versatile configuration options, this IP provides an adaptable solution that meets the demands of modern multimedia systems, delivering unrivaled performance in digital data reception.
Designed for high-performance environments such as data centers and automotive systems, the Origin E8 NPU cores push the limits of AI inference, achieving up to 128 TOPS on a single core. Its architecture supports concurrent running of multiple neural networks without context switching lag, making it a top choice for performance-intensive tasks like computer vision and large-scale model deployments. The E8's flexibility in deployment ensures that AI applications can be optimized post-silicon, bringing performance efficiencies previously unattainable in its category. The E8's architecture and sustained performance, alongside its ability to operate within strict power envelopes (18 TOPS/W), make it suitable for passive cooling environments, which is crucial for cutting-edge AI applications. It stands out by offering PetaOps performance scaling through its customizable design that avoids penalties typically faced by tiled architectures. The E8 maintains exemplary determinism and resource utilization, essential for running advanced neural models like LLMs and intricate ADAS tasks. Furthermore, this core integrates easily with existing development frameworks and supports a full TVM-based software stack, allowing for seamless deployment of trained models. The expansive support for both current and emerging AI workloads makes the Origin E8 a robust solution for the most demanding computational challenges in AI.
A high-performance Chiplet tailored for PCIe Gen 5 applications, offering advanced features in data transfer speed and efficiency. It integrates Yorchip's patented PHY technology, providing low latency and power consumption solutions suitable for modern computing needs.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus transaction. It also produces error messages for empty addresses in the hierarchy.
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
The Metis AIPU M.2 Accelerator Module is a powerful AI processing solution designed for edge devices. It offers a compact design tailored for applications requiring efficient AI computations with minimized power consumption. With a focus on video analytics and other high-demand tasks, this module transforms edge devices into AI-capable systems. Equipped with the Metis AIPU, the M.2 module can achieve up to 3,200 FPS for ResNet-50, providing remarkable performance metrics for its size. This makes it ideal for deployment in environments where space and power availability are limited but computational demands are high. It features an NGFF (Next Generation Form Factor) socket, ensuring it can be easily integrated into a variety of systems. The module leverages Axelera's Digital-In-Memory-Computing technology to enhance neural network inference speed while maintaining power efficiency. It's particularly well-suited for applications such as multi-channel video analytics, offering robust support for various machine learning frameworks, including PyTorch, ONNX, and TensorFlow.
The MXL-LVDS-MIPI-RX is a high-frequency, low-power, low-cost, source-synchronous, Physical Layer that supports the MIPI® Alliance Standard for D-PHY and compatible with the TIA/EIA-644 LVDS standard. (Learn more about Mixel’s MIPI ecosystem at Mixel MIPI Central which gives you access to Mixel’s best of class MIPI ecosystem supply chain partners.) The IP is configured as a MIPI slave and consists of 5 lanes: 1 Clock lane and 4 data lanes, which make it suitable for display serial interface applications (DSI). The High-Speed signals have a low voltage swing, while Low-Power signals have large swing. High-Speed functions are used for High-Speed Data traffic while low power functions are mostly used for control.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The CT25205 integrates several building blocks of the IEEE 802.3cg 10BASE-T1S Ethernet Physical Layer. Designed with Verilog HDL, this digital core is optimized for implementation on both standard cells and FPGA architectures, ensuring seamless compatibility with IEEE Ethernet MAC interfaces through MII. The core's standout feature is the integrated Physical Layer Collision Avoidance (PLCA) Reconciliation Sublayer, which allows existing MACs to leverage PLCA benefits without additional hardware modifications. A key aspect of this design is its connectivity to an OPEN Alliance 10BASE-T1S PMD Interface, streamlining integration into Zonal Gateways and MCUs. Paired with Canova Tech's complementary IPs, such as the CT25208 MAC controller, CT25205 forms the backbone of cutting-edge communication systems in industries requiring efficient data exchange. The CT25205 supports a wide array of industrial applications due to its robustness and capability to enhance the existing communication frameworks. It is particularly well-suited for automotive and industrial environments where reliable and durable Ethernet solutions are crucial.
The UDP Offload Engine (UOE) by Intilop is a specialized component designed to enhance the throughput of networks handling extensive amounts of UDP traffic. Offering ultra-low latency, this engine significantly mitigates the processing demands on CPUs by offloading the processing tasks associated with UDP protocol layers. The UOE integrates a suite of functions that permit faster data transmission and reception, crucial for real-time applications such as video streaming and Voice over IP (VoIP), where uninterrupted and swift data flow is critical. By eliminating the bottleneck traditionally caused by CPU-bound UDP packet processing, the UOE ensures that systems can achieve higher data rates and improved response times without overburdening the CPU. Its capacity to handle numerous concurrent UDP sessions without sacrificing speed makes it ideal for deployment in environments requiring constant high-performance networking, such as media servers and VoIP systems. Emphasizing both hardware efficiency and software compatibility, this engine exemplifies Intilop's commitment to delivering top-tier networking solutions.
The Die-to-Die (D2D) Interconnect solution by SkyeChip is a comprehensive technology facilitating high-speed data transfer between dies. Compliant with the UCIe 2.0 specification, it provides high bandwidth and minimal power overhead making it ideal for chiplet-based architectures. This lightweight interconnect supports diverse protocols such as PCIe and CXL, allowing adaptability to numerous communication requirements. It is designed to support major packaging technologies, ensuring flexibility and robustness in post-package yields and supporting loopback tests for integrity assurance.
The H.264 FPGA Encoder and CODEC Micro Footprint Cores are designed to offer superior video compression capabilities, ensuring minimal latency with a remarkable sub-1ms delay for 1080p30. This licensable core is notable for its compliance with ITAR standards, making it adaptable for various strategic applications. It facilitates 1080p60 baseline support with a single compact core that's touted as the fastest and smallest in its class. These cores are customizable, allowing for tailored pixel depths and unique resolutions that can be modified based on the specific requirements of a project. Moreover, the flexibility of these cores extends to various encoding flavors, including H.264 Encoder, CODEC, and I-Frame Only Encoder, which further enhances their usage in a wide range of applications. A low-cost evaluation license is also available, making the cores accessible for diverse testing and development scenarios.
The Origin E2 family of NPU cores is tailored for power-sensitive devices like smartphones and edge nodes that seek to balance power, performance, and area efficiency. These cores are engineered to handle video resolutions up to 4K, as well as audio and text-based neural networks. Utilizing Expedera’s packet-based architecture, the Origin E2 ensures efficient parallel processing, reducing the need for device-specific optimizations, thus maintaining high model accuracy and adaptability. The E2 is flexible and can be customized to fit specific use cases, aiding in mitigating dark silicon and enhancing power efficiency. Its performance capacity ranges from 1 to 20 TOPS and supports an extensive array of neural network types including CNNs, RNNs, DNNs, and LSTMs. With impressive power efficiency rated at up to 18 TOPS/W, this NPU core keeps power consumption low while delivering high performance that suits a variety of applications. As part of a full TVM-based software stack, it provides developers with tools to efficiently implement their neural networks across different hardware configurations, supporting frameworks such as TensorFlow and ONNX. Successfully applied in smartphones and other consumer electronics, the E2 has proved its capabilities in real-world scenarios, significantly enhancing the functionality and feature set of devices.
The AHB-Lite Multilayer Switch is engineered to provide a high-performance, low-latency interconnect fabric capable of supporting numerous bus masters and slaves. This switch is essential in complex system architectures where multiple data paths need to be managed efficiently simultaneously, ensuring seamless data throughput and reduced bottlenecks in system operations.
The AI Camera Module from Altek is an innovative integration of image sensor technology and intelligent processing, designed to cater to the burgeoning needs of AI in imaging. It combines rich optical design capabilities with software-hardware amalgamation competencies, delivering multiple AI camera models that assist clients in achieving differentiated AI + IoT needs. This flexible camera module excels in edge computing by supporting high-resolution requirements such as 2K and 4K, thereby becoming an indispensable tool in environments demanding detailed image analysis. The AI Camera Module allows for superior adaptability in performing functions such as facial detection and edge computation, thus broadening its applicability across industries. Altek's collaboration with major global brands fortifies the AI Camera Module's position in the market, ensuring it meets diverse client specifications. Whether used in security, industrial, or home automation applications, this module effectively integrates into various systems to deliver enhanced visual processing capabilities.
Digital Blocks' UART Serial Communication Controller provides a reliable and efficient solution for synchronous and asynchronous serial data communication. Supporting a range of baud rates, this controller is designed to interface with microprocessors via AMBA buses and can be configured to suit various communication protocols and settings. The IP core's flexibility and robust performance make it suitable for use in embedded systems, industrial control, and any application requiring dependable serial communication.
Digital Blocks' AXI4 DMA Controller is engineered for high-efficiency data transfer in embedded systems. It is a multi-channel controller that allows for 1 to 16 independent data transfers, with adaptability for various data sizes and configurations. This controller supports complex data transfer schemes like scatter-gather with linked-lists, interrupt reporting, and can handle large bursts of data efficiently due to its extensive support for both AXI3 and AXI4 protocols. It's designed for uses requiring high throughput and reliability, making it particularly suitable for performance-critical aerospace and communications applications.
The CXL 3.1 Switch is a sophisticated piece of technology designed to enable comprehensive connectivity and interoperability across various high-performance computing devices. By supporting the latest CXL 3.1 standards, this switch provides multi-level switching capabilities, enabling efficient resource management and data processing in large-scale server environments. It ensures seamless integration between differing devices, from GPUs to memory expanders, managing complex data traffic with optimized latency and bandwidth. This switch is crucial for cloud and data center applications, providing a backbone for systems requiring significant scalability. With features supporting multi-device connectivity and port-based routing, the CXL 3.1 Switch facilitates memory sharing and data coherence across diverse hardware, enhancing overall system efficiency. Its role in forming CXL-enabled AI clusters makes it a cornerstone for the next generation of AI-driven services, allowing vast data resource pools to be dynamically allocated where needed. The innovative architecture of the CXL 3.1 Switch integrates advanced communication protocols to handle large data volumes effectively. It provides unmatched latency performance that elevates computing speeds and minimizes bottlenecks. The adaptation of this technology within AI clusters highlights its potential in accelerating AI inference and training tasks, making it an indispensable tool for modern computational needs.
The MXL-SR-LVDS is a high performance 4-channel LVDS Serializer implemented using digital CMOS technology. Both the serial and parallel data are organized into four channels. The parallel data width is programmable, and the input clock is 25MHz to 165MHz. The Serializer is highly integrated and requires no external components. It employs optional pre-emphasis to enable transmission over a longer distance while achieving low BER. The circuit is designed in a modular fashion and desensitized to process variations. This facilitates process migration, and results in a robust design.