All IPs > Interface Controller & PHY
Interface Controller & PHY semiconductor IPs are integral components in modern digital systems that facilitate communication between various parts of an electronic system, including processors, memory, and peripherals. These IPs are designed to manage data traffic efficiently, ensuring reliable and high-speed data transfer between different interfaces and devices. This catalog features a wide range of IPs that serve various standard and custom interface protocols, making them indispensable for semiconductor companies developing complex SoCs (System on Chips) and digital systems.
In this category, you will find a selection of IPs tailored for popular interface protocols such as AMBA (AHB, APB, AXI), HDMI, PCI, USB, and MIPI, among others. Each IP solution is optimized for performance, supporting high-speed data transfer and reduced latency to meet the demanding needs of today's applications. These IPs not only provide seamless integration capabilities into your design but also ensure compliance with industry standards, which is crucial for interoperability in multi-vendor environments.
The embedded controllers within these IPs handle the logical functions necessary for device communication, while the PHY (physical layer) IPs manage the actual transmission and reception of data across physical media. Together, they enable efficient bridging between different communication protocols, making them critical components in a vast array of devices ranging from consumer electronics like smartphones and gaming consoles to industrial systems and automotive applications.
Our catalog also offers specialized solutions such as Multi-Protocol PHYs that support multiple standards within a single IP, providing flexibility and reducing the footprint for designs that require versatile connectivity options. By selecting the right Interface Controller & PHY IP from our catalog, developers can significantly enhance the functionality and overall performance of their products, leveraging the latest advancements in data interface technology. Explore our offerings and find the precise IP solutions needed to bring your innovative designs to life.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
KPIT Technologies is a forerunner in developing AUTOSAR-compliant platforms that support the evolution of software-defined vehicles. Their solutions facilitate efficient software integration, middleware development, and high-level application performance optimization. By using advanced tools and methodologies, KPIT helps speed up the production timelines of modern vehicles, ensuring compliance with both AUTOSAR Classic and Adaptive frameworks. Their technologies enable automakers to minimize platform validation times and reduce integration complexities, thereby enhancing the scalability and functionality of vehicle systems.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
eSi-Connect is a sophisticated networking solution designed to enhance the communication efficiency between eSi-RISC cores and their peripherals. Utilizing the AMBA protocol, it provides seamless interconnections across processors, memory controllers, and various peripheral devices. This results in a streamlined design process and reduced complexity during system integration. Leveraging industry-standard architectures, eSi-Connect ensures that a wide range of third-party IP cores can be integrated smoothly, providing flexibility and choice in design customization. Its design optimally supports the scalability and compatibility requirements of complex embedded systems. eSi-Connect's robust framework is crafted to support a myriad of applications, from simple control systems to multiprocessor platforms requiring advanced data throughput and low latency. This adaptability makes it a pivotal component in the design of modern embedded systems, facilitating enhanced system performance and efficiency.
Silicon Creations' LVDS Interfaces provide a low-power, high-speed data communication solution ideal for connecting integrated circuits in close proximity. Known for their low noise and power efficiency, these interfaces are widely used in applications ranging from display technology to telecommunications. These robust LVDS solutions support high data rates and are highly adaptable to various process nodes from 90nm to more advanced 7nm FinFET, making them suitable for both legacy and cutting-edge technologies. They ensure data integrity and signal stability across different conditions and configurations, leveraging enhanced CDR architectures. With extensive configurations supporting uni-directional and bi-directional operation, the LVDS interfaces provide flexibility for custom communications setups and are compliant with multiple standards like Camera Link and FPD-Link. Their capability to manage high-speed data links with precision positions them as essential components in demanding electronic applications.
The SerDes Interfaces from Silicon Creations feature cutting-edge capabilities for high-speed serial data transmission in semiconductor devices. Supporting a vast range of industry protocols, these interfaces offer both flexibility and performance, making them ideal for varied high-bandwidth applications. These interfaces accommodate rates from as low as 100Mbps to an impressive 32.75Gbps, covering a wide spectrum of technologies from JESD204 to PCIe and V-by-One. They include programmable serialization and deserialization features, along with advanced techniques for reducing latency, ensuring the rapid delivery and reception of data streams. Built on proven IP platforms, the SerDes interfaces integrate advanced PLLs to manage jitter and power consumption effectively. With adaptability to a multitude of fabrication nodes, these solutions meet the diverse needs of networked devices and high-speed interconnects, showcasing Silicon Creations’ expertise in providing industry-leading communication solutions.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features:  Maximum Operating speed of 12.5MHz  Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support  Multi-Time Programmable Non-Volatile Memory Interface  Programmable and DIMM-specific registers for customization  Error log registers for tracking  Packet Error Check (PEC) and Parity Error Check functions  Bus Reset function  Support I3C Basic mode  In-Band Interrupt (IBI) support  Write, read, and default read operations in I2C mode  Error handling for PEC, Parity errors, and CCC errors  I3C Basic Common Command Codes (CCC) support Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
KPIT's Connected Vehicle Solutions leverage modern cloud and edge computing to enhance the connectivity features of today’s vehicles. This technology supports secure data management, advanced analytics, and comprehensive solutions for real-time vehicle connectivity. The platform is engineered to provide enriched data-driven insights, enabling OEMs to better handle vehicle data, improve cybersecurity measures, and ensure compliance with emerging regulatory standards. By transforming data into strategic advantages, KPIT aids automotive manufacturers in delivering enhanced user experiences and operational efficiencies.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
KPIT Technologies provides robust digital frameworks that enable advanced connectivity amongst vehicle systems, driven by software innovation. These solutions are integral in turning vehicles into hubs of data exchange and engaging passenger experiences. This includes state-of-the-art in-vehicle infotainment systems and augmented reality interfaces, aiming to improve user satisfaction through personalized, secure, and efficient vehicle interactions. KPIT enhances cloud-driven solutions that effectively integrate these technological marvels, ensuring elasticity in scaling and optimizing connectivity solutions for the modern mobility ecosystem.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configura􀆟on. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Op􀆟onal DMA support as plugin module. • Support for alternate nego􀆟a􀆟on protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configura􀆟on. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
This LPDDR4/4X/5 Secondary/Slave PHY provides sophisticated memory-side interfacing capabilities that support AI processors and next-gen ASIC designs. It effectively integrates with devices requiring high-speed, low-power LPDDR communication, aligning with international JEDEC standards. While designed for usage on TSMC's 7nm technology, this IP can adapt to other processes, expanding its scope across advanced and emerging memory technologies such as DRAM and various non-volatile options.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Pixel to Byte conversion support from Application layer to LLP layer  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern in Data Lane Module  Lane Distribution Function for distributing packet bytes across N-Lanes  Sync word insertion through PPI command in C-PHY physical layer  Insertion of Filler bytes in LLP layer for packet footer alignment  Setting specific bits in packet header  Defining frame blanking period  Seed selection in scrambler and de-scrambler by Sync word  Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports EP & RC. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
KPIT's iDART platform addresses the challenges posed by software-defined vehicles, focusing on optimizing diagnostics, maintenance, and aftersales services. By deploying advanced AI-driven diagnostics and self-learning systems, the platform enhances the reliability of vehicle servicing and improves the overall customer experience. This transformation embraces legacy system integration while advancing toward fully automated, predictive, and customer-centered service models that support the evolving demands of the automotive market.
Decoder logic controls numerous targets based on input from the initiator. It determines/decodes which target component will handle the current bus transaction. It also produces error messages for empty addresses in the hierarchy.
The AHB-Lite APB4 Bridge from Roa Logic is a parameterized soft IP bridge designed to facilitate communication between AMBA AHB-Lite and APB protocols. This bridge serves as a crucial component in systems requiring seamless integration of different bus architectures. It translates signals between the AHB-Lite and APB protocols, ensuring compatibility across a range of devices and subsystems. As a versatile interconnection solution, this bridge is essential for systems that incorporate various peripherals and require efficient bus communication. It is optimized for low latency and high throughput, offering robust support for dynamic and static systems. This bridge is invaluable in enhancing data flows and maintaining system integrity in multi-bus designs. The AHB-Lite APB4 Bridge simplifies the integration of peripherals, making it easier for system architects to design adaptable and efficient systems that meet their specific performance requirements. Its parameterized nature allows customization to suit varying project needs, ensuring flexibility and enhanced functionality.
The Origin E1 is a highly efficient neural processing unit (NPU) designed for always-on applications across home appliances, smartphones, and edge nodes. It is engineered to deliver approximately 1 Tera Operations per Second (TOPS) and is tailored for cost- and area-sensitive deployment. Featuring the LittleNPU architecture, the Origin E1 excels in low-power environments, making it an ideal solution for devices where minimal power consumption and area are critical. This NPU capitalizes on Expedera's innovative packet-based execution strategy, which allows it to perform parallel layer execution for optimal resource use, cutting down on latency, power, and silicon area. The E1 supports a variety of network types commonly used in consumer electronics, including Convolutional Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and more. A significant advantage of Origin E1 is its scalability and market-leading power efficiency, achieving 18 TOPS/W and supporting standard, custom, and proprietary networks. With a robust software stack and support for popular AI frameworks like TensorFlow and ONNX, it ensures seamless integration into a diverse range of AI applications.
The Origin E8 neural processing unit (NPU) stands out for its extreme performance capabilities, designed to serve demanding applications such as high-end automotive systems and data centers. Capable of delivering up to 128 TOPS per core, this NPU supports the most advanced AI workloads seamlessly, whether in autonomous vehicles or data-intensive environments. By employing Expedera's packet-based architecture, Origin E8 ensures efficient parallel processing across layers and achieves impressive scalability without the drawbacks of increased power and area penalties associated with tiled architectures. It allows running extensive AI models that cater to both standard and custom requirements without compromising on model accuracy. The NPU features a comprehensive software stack and full support for a variety of frameworks, ensuring ease of deployment across platforms. Scalability up to PetaOps and support for resolutions as high as 8K make the Origin E8 an excellent solution for industries that demand unrivaled performance and adaptability.
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
MIPI I3C Controller IP Core is fully compliant with the latest I3C specification and delivers high bandwidth and scalability for integration of multiple sensors into mobile, automotive and IoT system-on-chips (SoCs). The MIPI I3C Controller supports in-band interrupts within the 2-wire interface provides significantly lower pin count, simplifying board design and reducing power and cost of the system. The MIPI I3C Controller IP is fully backward compatible with I2C, allowing designers to future proof their design, and the I3C controller IP operating modes enable systems with several ICs to efficiently connect to all sensors on a single I3C bus. The standard-based ARM® AMBA® Advanced High Performance Bus (AHB) connects the IP to the rest of the SoC offering easy IP integration. MIPI I3C Controller IP is designed to easily integrate into any SoC offering lowest gate count and quickly fit into any Chip development flow.
The Die-to-Die (D2D) Interconnect solution by SkyeChip is a comprehensive technology facilitating high-speed data transfer between dies. Compliant with the UCIe 2.0 specification, it provides high bandwidth and minimal power overhead making it ideal for chiplet-based architectures. This lightweight interconnect supports diverse protocols such as PCIe and CXL, allowing adaptability to numerous communication requirements. It is designed to support major packaging technologies, ensuring flexibility and robustness in post-package yields and supporting loopback tests for integrity assurance.
The Origin E2 is a versatile, power- and area-optimized neural processing unit (NPU) designed to enhance AI performance in smartphones, edge nodes, and consumer devices. This NPU supports a broad range of AI networks such as RNNs, LSTMs, CNNs, DNNs, and others, ensuring minimal latency while optimizing for power and area efficiency. Origin E2 is notable for its adaptable architecture, which facilitates seamless parallel execution across multiple neural network layers, thus maximizing resource utilization and providing deterministic performance. With performance capabilities scalable from 1 to 20 TOPS, the Origin E2 maintains excellent efficiency up to 18 TOPS per Watt, reflecting its superior design strategy over traditional layer-based solutions. This NPU's software stack supports prevalent frameworks like TensorFlow and ONNX, equipped with features such as mixed precision quantization and multi-job APIs. It’s particularly suitable for applications that require efficient processing of video, audio, and text-based neural networks, offering leading-edge performance in power-constrained environments.
Silicon Library's V-By-One HS technology offers a sophisticated solution for high-speed data transmission in displays. It provides a compact and efficient interface that supports high-resolution display panels, enhancing image quality with reduced latency. Ideal for automotive applications, as well as televisions and monitors, V-By-One HS supports a significant reduction in cabling needs, optimizing space and improving system reliability. The technology ensures minimal electromagnetic interference, crucial for maintaining signal integrity in sensitive environments. This interface is engineered to support high-bandwidth needs, making it suitable for applications requiring seamless data flow. Its efficiency in both power usage and data handling capabilities makes it an excellent choice for advanced multimedia systems seeking top-tier performance.
The LVDS/OpenLDI solution from Silicon Library supports high-speed, low-power data transmission for displays and other digital interfaces. This technology is suited for various applications where efficient and reliable data transfer is necessary, including automotive displays and advanced computing systems. With LVDS/OpenLDI, devices can achieve high data rates over long distances with minimal crosstalk and electromagnetic interference. Its robust performance ensures that data integrity is maintained, even in challenging environments. This makes it ideal for settings where reliability and performance cannot be compromised. As a part of advanced digital systems, LVDS/OpenLDI contributes to reducing overall power consumption, an essential feature for battery-operated devices. The technology’s flexibility and efficiency make it a preferred choice for engineers looking to streamline data communication across different electronic ecosystems.
The APB4 GPIO by Roa Logic is a fully customizable input/output interface solution that encourages flexible integration of general-purpose pins into a broad range of electronic designs. Tailored to the needs of various applications, this GPIO core is designed to support bidirectional communication, offering assurances of performance and functionality. Each pin in the APB4 GPIO can be individually configured to act as either an input or an output, providing extensive adaptability for unique system requirements. This capability enhances system flexibility, allowing for precise control in managing peripheral interactions and communication. Its straightforward design and comprehensive configuration options make the APB4 GPIO a functional component for a variety of projects, ranging from simple circuit design to complex embedded systems requiring multiple interfaces. Its user-definable features ensure that it can meet bespoke needs, supporting a range of industry applications with precision and reliability.
The LVDS/D-PHY Combo Receiver by Mixel is intended for high-throughput environments where compatibility with both LVDS and D-PHY standards is essential. It combines the benefits of a source-synchronous physical layer for MIPI D-PHY and the TIA/EIA-644 standard LVDS, offering significant versatility. Its high-performance architecture ensures rapid data provisioning with minimized energy requirements, making it ideal for use in devices where efficient power handling and robust communication interfaces are necessary.
The UART Serial Communication Controller is engineered to provide reliable asynchronous data transmission between processors and peripheral devices. The design includes support for variable data rates, ensuring flexibility in communication demands across different operational scenarios. This versatility makes it suitable for embedded systems where diverse data types and throughput requirements are needed. It supports the integration of various peripheral devices, thus enhancing the capability and scalability of the communications architecture within complex systems.
The UDP Offload Engine by Intilop showcases the company’s commitment to enhancing data throughput via hardware acceleration. Designed to manage UDP protocols efficiently, this engine assists in reducing system overheads, thereby enhancing network performance substantially. Tailored for environments that heavily rely on UDP traffic, such as video streaming and real-time data analytics, this engine ticks all the right boxes by delivering low-latency data handling and release from conventional CPU processing tasks. It provides a significant leap forward in terms of efficiency, as UDP traffic typically necessitates rapid packet processing. This IP's design is synonymous with robustness, ensuring high availability and sustained throughput in demanding networking scenarios. It marks itself as an essential component for any architect planning to deploy efficient and high-performance UDP-based networking systems.
The PolarFire FPGA Family by Microsemi is engineered to deliver cost-effectiveness alongside exceptional power efficiency, positioning itself as the optimal choice for mid-range FPGA applications. Crafted to offer transceivers ranging from 250 Mbps to a robust 12.7 Gbps, these FPGAs cater to diverse bandwidth requirements. With logic elements spanning 100K to 500K and incorporating up to 33 Mbits of RAM, the PolarFire series seamlessly addresses demanding processing needs while ensuring secure and reliable performance. At the heart of its design philosophy is a focus on best-in-class security features combined with high reliability, making it particularly relevant for industries like automotive, industrial, and communication infrastructures where failure is not an option. It supports applications that require low power consumption without sacrificing performance, which is increasingly important in today's energy-conscious environments. These FPGAs find their versatility in a range of applications, from driving advancements in ADAS in the automotive industry to supporting broadband and 5G mobile infrastructures in telecommunications. The family also extends its use cases to data center technologies, highlighting its adaptability and efficiency in both digital and analog processing fields. With such a broad spectrum of applicability, the PolarFire FPGA Family stands as a shining example in Microsemi's product arsenal, delivering solutions tuned for innovation and performance.
The Multi-Channel Flex DMA IP Core offers an adaptable solution for handling up to 16 streaming channels, each managed independently to prevent mutual obstruction. Users can customize the data rate for each channel to optimize interfacing simplicity while incorporating prioritized FIFO buffers to ensure crucial data streams maintain supremacy. Designed with streaming and co-processor applications in mind, this IP core reads data from any source, processes it, and disseminates it to designated targets. Additionally, the core includes mechanisms for monitoring CRC errors along PCI Express links, enabling the prompt identification and exclusion of assemblies with subpar signal integrity during production testing. This core is paramount in safety-critical applications, where signal integrity and real-time data management are vital, offering high reliability and responsiveness in demanding environments. Its blend of efficiency and precision makes it a favorite for being able to swiftly adapt to varied processing needs without compromising on performance quality.
The ABX Platform by Racyics utilizes Adaptive Body Biasing (ABB) technology to drive performance in ultra-low voltage scenarios. This platform is tailored for extensive applications requiring ultra-low power as well as high performance. The ABB generator, along with the standard cells and SRAM IP, form the core of the ABX Platform, providing efficient compensation for process variations, supply voltage fluctuations, and temperature changes.\n\nFor automotive applications, the ABX Platform delivers notable improvements in leakage power, achieving up to 76% reduction for automotive-grade applications with temperatures reaching 150°C. The platform's RBB feature substantially enhances leakage control, making it ideal for automotive uses. Beyond automotive, the ABX Platform's FBB functionality significantly boosts performance, offering up to 10.3 times the output at 0.5V operation compared to non-bias implementations.\n\nExtensively tested and silicon-proven, the ABX Platform ensures reliability and power efficiency with easy integration into standard design flows. The solution also provides tight cornering and ABB-aware implementations for improved Power-Performance-Area (PPA) metrics. As a turnkey solution, it is designed for seamless integration into existing systems and comes with a free evaluation kit for potential customers to explore its capabilities before committing.
The Mixed-Signal CODEC offered by Archband Labs stands out as a versatile solution integrating both analog and digital functionalities. This CODEC is designed to meet the demands of various audio and voice processing applications, ensuring high fidelity and low power consumption. Equipped with robust conversion capabilities, it's suitable for a range of environments from wearable tech to automotive systems, ensuring clear and precise sound reproduction. The CODEC forms a crucial part of devices like smart home appliances and AR/VR gadgets, where audio quality is paramount.
The Origin E6 NPU is engineered for high-performance on-device AI tasks in smartphones, AR/VR headsets, and other consumer electronics requiring cutting-edge AI models and technologies. This neural processing unit balances power and performance effectively, delivering between 16 to 32 TOPS per core while catering to a range of AI workloads including image transformers and point cloud analysis. Utilizing Expedera’s unique packet-based architecture, the Origin E6 offers superior resource utilization and ensures performance with deterministic latency, avoiding the penalties typically associated with tiled architectures. Origin E6 supports advanced AI models such as Stable Diffusion and Transformers, providing optimal performance for both current and predicted future AI workloads. The NPU integrates seamlessly into chip designs with a comprehensive software stack supporting popular AI frameworks. Its field-proven architecture, deployed in millions of devices, offers manufacturers the flexibility to design AI-enabled devices that maximize user experience while maintaining cost efficiency.
Intilop's 10G TCP Offload Engine epitomizes advanced network throughput technology through its ultra-low latency mechanisms. This engine is engineered to handle high-frequency data transactions with little to no delay, rendering it ideal for data center environments, cloud computing, and communication sectors where immediate data access and processing are critical. The ingress and egress latency is minimized, bringing forth seamless data flows that rival traditional software-driven networking solutions. This segment of Intilop's engine arsenal supports robust integration within existing infrastructures, maintaining versatility across various network configurations. Tailored for real-time data applications, its proactive offloading mechanism translates into side-stepping CPU-dependent bottlenecks, optimizing both performance and network resilience.
The C/D-PHY Combo is an advanced hybrid PHY designed for use in systems requiring both high flexibility and efficiency. As a dual-configuration PHY, it can switch between C-PHY and D-PHY configurations, functioning as a receiver or transmitter depending on application needs. This adaptability makes it particularly valuable for cutting-edge mobile and IoT devices, where it offers optimized performance under varying power conditions. The IP’s low-power consumption and support for multiple process nodes ensure it can be employed across diverse manufacturing landscapes.
The eSPI Master/Slave Controller effectively conforms to the Enhanced SPI specification, providing programmable functionality for master/slave configurations. With compliance to eSPI Bus Protocols, it supports various hardware interconnects, including AMBA AXI and AHB, making it suitable for both low and high-performance embedded systems. The controller is designed to address diverse operational needs, from consumer electronics to automotive applications, where reliability and accuracy in data transfers are critical. Its versatile architecture supports flexible deployment in complex system environments, enhancing communication efficiency across integrated networks.
Mobiveil's NVM Express Controller is engineered for both enterprise and client applications, designed to unleash the potential of PCIe-based SSDs. It features a flexible, configurable architecture optimized for thread management, reliability, and power efficiency while ensuring maximum performance. It can be integrated seamlessly with Mobiveil's PCI Express Controller and a variety of third-party NAND Flash controllers, further enhancing data throughput and overall system efficiency.
The SPI Master/Slave Controller by Digital Blocks is crafted for seamless integration into systems requiring robust serial data exchange. This Verilog IP core supports both master and slave operations over AMBA AXI, AHB, or APB interfaces. The architecture is optimized for efficient communication with external SPI master or slave devices, ensuring reliable data transfers in various industrial and consumer applications. Its adaptable design is particularly suited for environments where multi-faceted peripheral interfaces are necessary, facilitating complex system integrations with multiple SPI-enabled components.
The USB PHY is crafted to facilitate seamless data transfer and communication through USB 2.0 protocols. Capable of efficient data encoding and decoding, this technology supports various electronic devices that require high-speed communication. Designed with power efficiency in mind, the USB PHY minimizes energy consumption while delivering robust and reliable performance. Silicon Library’s USB PHY is engineered to ensure compatibility with a wide range of systems, making it an adaptable solution for diverse applications. From consumer electronics to industrial devices, it plays a critical role in managing data traffic and optimizing system operations. Featuring a high degree of integration, the USB PHY minimizes the need for additional components, ultimately reducing design complexity and cost. Its reliability and performance have made it a preferred choice for developers seeking to implement efficient and dependable USB communications.
The AXI Bridge for PCIe is a versatile Smartlogic solution featuring up to four AXI4 interfaces. This IP core seamlessly translates AXI read and write commands into PCIe Transaction Layer Packets, maintaining continuous parallel operations across all interfaces with zero interference. Unused interfaces can be deactivated to conserve logical resources, highlighting its efficiency-oriented design. The inclusion of a high-performance kernel mode driver enhances its operability on Windows and Linux systems, paving the way for easy software integration. This characteristic allows users to transfer payloads without delving into the complexities of PCIe packet formation. Ideal for various applications, especially in networking, this component provides dependable solutions where high throughput and low-latency data interactions are essential. It stands out for its ability to support dynamic Ethernet applications, ensuring that network environments function optimally at all times.
The AXI4 DMA Controller is a multi-channel Verilog RTL IP core that manages data transfers with exceptional throughput across several large and small data sets. Supporting configurations from 1 to 16 channels, it features independent DMA Read and Write Controllers, utilizing AXI3 and AXI4 protocols to ensure efficient data handling across memory and peripherals. Its design accommodates intricate data transfer requirements, offering features such as scatter-gather linked lists and user-defined AXI burst lengths up to 256 beats. The DMA controller is adept in facilitating multiple concurrent data streams, enhancing performance for high-bandwidth applications.