All IPs > Graphic & Peripheral > Peripheral Controller
Peripheral Controller semiconductor IPs play a crucial role in the seamless integration of peripherals with core processing units, enhancing the functionality and connectivity of various electronic devices. These IPs are designed to manage the communication between the central processing unit (CPU) and external devices such as keyboards, mice, printers, and other peripherals. By enabling efficient data transfer and control signals between components, Peripheral Controller IPs ensure that systems operate smoothly and efficiently.
A key application of Peripheral Controller semiconductor IPs is in consumer electronics, where they facilitate the connection of tablets, smartphones, and laptops to a multitude of accessories and networks. For example, Universal Serial Bus (USB) controllers, memory card readers, and audio interfaces are just a few of the peripherals that these IPs manage. This allows end-users to transfer data quickly, connect various devices seamlessly, and enjoy a more versatile computing experience.
In industrial and automotive sectors, Peripheral Controller IPs are vital for maintaining robust and reliable communication within complex electronic systems. They are used to interface with sensors, actuators, and other control systems, ensuring that necessary data is transmitted accurately and in real-time. This is critical for applications that require precise timing and synchronization, such as automated manufacturing systems, smart grids, and advanced driver-assistance systems (ADAS).
Moreover, the evolution of Internet of Things (IoT) devices has further expanded the importance of Peripheral Controller IPs. As IoT ecosystems continue to grow, the need for efficient data management and connectivity solutions becomes more prominent. Peripheral Controller IPs offer the adaptability and scalability required to support a wide array of IoT applications, ensuring that devices can connect, communicate, and interact with each other effectively in both personal and industrial settings.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features: Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0 Support for Single master and multiple slaves per interface port Single Data Rate (SDR) and Double Data Rate (DDR) support Source synchronous clocking Deep Power Down (DPD) enter and exit commands Eight IO ports in standard, expandable based on system requirements Optional Data Strobe (DS) for write masking bit wide SDR transfer support Profile 1.0 Commands for non-volatile memory device management Profile 2.0 Commands for read or write data for various slave devices Applications: Consumer Electronics Defense & Aerospace Virtual Reality Augmented Reality Medical Biometrics Automotive Devices Sensor Devices
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications: Supports PCIe Gen 6 and Pipe 5.X Specifications Core supports Flit and non-Flit Mode Lane Configurations: X16, X8, X4, X2, X1 AXI MM and Streaming supported Supports Gen1 to Gen6 modes Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s PAM support when operating at 64GT/s Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b Supports SerDes and non-SerDes architecture Optional DMA support as plugin module Support for alternate negotiation protocol Can operate as an endpoint or root complex Lane polarity control through register Lane de-skew supported Support for L1 states and L0P Support for SKP OS add/removal and SRIS mode No equalization support through configuration Deemphasis negotiation support at 5GT/s Supports EI inferences in all modes Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features: Supports UCIe 1.0 Specification Supports CXL 2.0 and CXL 3.0 Specifications Supports PCIe Gen6 Specification Supports PCIe Gen5 and older versions of PCIe specifications Supports single and two-stack modules Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers Supports CXL 3.0 256Byte flit mode Supports PCIe Gen6 flit mode Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules Supports sideband and Mainband signals Supports Lane repair handling Data to clock point training and eye width sweep support from transmitter and receiver ends UCIe controller can work as Downstream or Upstream Main Band Lane reversal supported Dynamic sense of normal and redundant clock and data lines activation UCIe enumeration through DVSEC Error logging and reporting supported Error injection supported through Register programming RDI/FDI PM entry, Exit, Abort flows supported Dynamic clock gang at adapter supported Configurable Options: Maximum link width (x1, x2, x4, x8, x16) MPS (128B to 4KB) MRRS (128B to 4KB) Transmit retry/Receive buffer size Number of Virtual Channels L1 PM substate support Optional Capability Features can be Configured Number of PF/VFDMA configurable Options AXI MAX payload size Variations Multiple CPI Interfaces (Configurable) Cache/memory configurable Type 0/1/2 device configurable
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features: CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X PCIe Compatibility: Supports PCIe spec 6.0/5.0 CPI Interface: Support for CPI Interface AXI Interface: Configurable AXI master, AXI slave Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16 Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode Register Checks: Configuration and Memory Mapped registers Dual Mode: Supports Dual Mode operation Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers CXL Support: Can function as both CXL host and device Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized) Power Management: Supports Power Management features Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD Testing: Compliance Testing and Error Scenarios support
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
KPIT Technologies offers sophisticated connected vehicle solutions that aim to bridge the gap between in-vehicle systems and the external digital ecosystem. These solutions enhance interaction, safety, and productivity for drivers by transforming vehicle cockpits into advanced digital platforms. KPIT's expertise in automotive infotainment, connectivity, and cloud integration services establishes it as a go-to partner for top-tier automotive OEMs and suppliers. The company provides well-researched platforms and tools that not only improve user experience but also offer innovative cockpit solutions that keep up with the fast-evolving digital consumer demands. KPIT's strength lies in its ability to integrate new technologies such as over-the-air (OTA) updates, cloud services, and data analytics seamlessly into automotive systems. The connected vehicle solutions include UI/UX development, digital cockpit components, and robust middleware for infotainment systems. By implementing cloud integration techniques and offering thorough support for OTA systems, KPIT ensures automotive systems are always up-to-date and functionally superior. KPIT's solutions have been widely adopted across millions of vehicles, underscoring the company's role in transforming the automotive landscape into one that is more digital, connected, and efficient. The firm's long-standing partnerships with OEMs and Tier-1 suppliers highlight the trust and reliability KPIT has earned in the automotive connectivity sector.
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The MIPITM SVTPlus-8L-F is an 8-lane serial video transmitter also engineered for FPGA uses. This transmitter aligns with CSI2 rev 2.0 and DPHY rev 1.2 standards, providing a throughput of 12Gbps. It supports high-performance video transmission with robust reliability and ease of integration. This IP solution is capable of handling multiple virtual channels, making it well-suited for applications that require high bandwidth and efficient data transfer mechanisms.
Controllers IP from Alma Technologies encompasses comprehensive SPI and SPI Flash memory controllers, offering robust performance for managing device communications and memory interactions within digital systems. These controllers enable seamless data exchanges across device networks, maintaining high data fidelity and operational efficiency. By facilitating streamlined data trajectories, they support the operational needs of various modern electronics from embedded systems to complex processor architectures. With their proven reliability, the controllers IP ensures compatibility and efficiency across numerous computational frameworks, thereby playing a pivotal role in the integration and management of current multi-device setups.
The SPI-MEM-CTRL is a sophisticated IP solution facilitating superior control over serial NOR and NAND flash memories, employing multi-I/O techniques to enhance data interactions and throughputs. Its configurable interface accommodates varied operational demands, simplifying the interface link between controller and memory. Specialized for high speed data access, it supports intensive read/write operations tailored to manage large volumes of quick-access data, crucial in fields benefiting from rapid response times. Implementing advanced bootlining and execution on-the-fly features, it caters to real-time processing requirements seen in high-performance computing. With a strong emphasis on flexibility and adaptability, the SPI-MEM-CTRL factors in both system-wide efficiency and user-led configurability for optimal functionality.
The MIPITM SVTPlus2500 is a 4-lane video transmitter robustly constructed for efficient video data transfer, adhering to the CSI2 rev 2.0 and DPHY rev 1.2 specifications. Notably, it features programmable timing parameters and PRBS support, accommodating 8 or 16 pixel inputs per clock. This transmitter is built for low clock ratings to facilitate simplified timing requirements, and can manage up to 16 virtual channels along with four streams each at 2.5Gbps, ensuring enhanced flexibility in a range of video applications.
AndeSight IDE is a comprehensive Integrated Development Environment designed to maximize productivity for developers working with AndesCore processors. This Eclipse-based IDE offers distinct versions including the standard edition, RDS, and a lite version, covering a wide array of development needs from high-performance to more minimalistic setups for IoT projects. With features such as refined user interfaces, efficient coding, and debugging tools, AndeSight fosters a seamless development experience. Its robust support for code profiling, performance analysis, and advanced debugging allows developers to refine and optimize their projects effectively. AndeSight also incorporates a wide range of tools including a compiler, linker, and simulator, providing a cohesive environment where software and hardware design converge. Furthermore, the IDE supports co-designing of hardware and software, facilitating integration and execution across diverse hardware configurations. Additional support for RTOS awareness and copilot functionalities extend the capabilities of AndeSight, making it an invaluable resource in developing applications that are efficient, robust, and tailored to specific business needs.
The AndeSoft SW Stack is a rich library of software components that provide robust support for developing applications on AndesCore processors. By leveraging the AndeSight IDE, developers can utilize an array of pre-verified components ranging from operating systems and middleware to extensive application frameworks. Designed to accelerate the development process, AndeSoft enables faster time-to-market by offering building blocks essential for smart devices and IoT applications. The stack provides access to a variety of open source and certified software from Andes partners, ensuring flexibility and high-quality standards for a range of development environments. Additionally, the software components within the stack are optimized to align with specific processor configurations, enhancing compatibility and performance across multiple hardware platforms. With comprehensive support for various protocols and APIs, AndeSoft offers unparalleled adaptability for the creation of versatile and efficient solutions.