All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Silicon Creations' Free Running Oscillators offer an efficient solution for timing applications that require reliability without the need for an external timing reference. These oscillators are available in various configurations to meet the diverse needs of modern electronic devices. Designed for low power consumption, these oscillators excel in applications like watchdog timers and core clock generators for microcontrollers (MCUs). They are engineered to maintain precise timing, even under challenging conditions, ensuring device stability across a wide range of temperatures and voltage fluctuations. With a focus on integration efficiency, these oscillators are optimized for baseline CMOS logic processes, requiring no additional external components. This makes them exceptionally compact yet precise, suitable for a broad spectrum of applications in consumer electronics and low-power chips, providing a consistent and dependable clock source.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
eSi-Connect is a sophisticated networking solution designed to enhance the communication efficiency between eSi-RISC cores and their peripherals. Utilizing the AMBA protocol, it provides seamless interconnections across processors, memory controllers, and various peripheral devices. This results in a streamlined design process and reduced complexity during system integration. Leveraging industry-standard architectures, eSi-Connect ensures that a wide range of third-party IP cores can be integrated smoothly, providing flexibility and choice in design customization. Its design optimally supports the scalability and compatibility requirements of complex embedded systems. eSi-Connect's robust framework is crafted to support a myriad of applications, from simple control systems to multiprocessor platforms requiring advanced data throughput and low latency. This adaptability makes it a pivotal component in the design of modern embedded systems, facilitating enhanced system performance and efficiency.
Silicon Creations' LVDS Interfaces provide a low-power, high-speed data communication solution ideal for connecting integrated circuits in close proximity. Known for their low noise and power efficiency, these interfaces are widely used in applications ranging from display technology to telecommunications. These robust LVDS solutions support high data rates and are highly adaptable to various process nodes from 90nm to more advanced 7nm FinFET, making them suitable for both legacy and cutting-edge technologies. They ensure data integrity and signal stability across different conditions and configurations, leveraging enhanced CDR architectures. With extensive configurations supporting uni-directional and bi-directional operation, the LVDS interfaces provide flexibility for custom communications setups and are compliant with multiple standards like Camera Link and FPD-Link. Their capability to manage high-speed data links with precision positions them as essential components in demanding electronic applications.
KPIT Technologies provides robust digital frameworks that enable advanced connectivity amongst vehicle systems, driven by software innovation. These solutions are integral in turning vehicles into hubs of data exchange and engaging passenger experiences. This includes state-of-the-art in-vehicle infotainment systems and augmented reality interfaces, aiming to improve user satisfaction through personalized, secure, and efficient vehicle interactions. KPIT enhances cloud-driven solutions that effectively integrate these technological marvels, ensuring elasticity in scaling and optimizing connectivity solutions for the modern mobility ecosystem.
The LC-PLLs from Silicon Creations are precision clocking solutions tailored for high-end applications, requiring ultra-low jitter and exceptional frequency integrity. These PLLs are crucial in domains such as analog front-end (AFE) systems, converters, and sophisticated RF clocking circuits. Known for their advanced Fractional-N design, these LC-PLLs minimize noise and spur interference while maintaining a remarkable bandwidth. They meet stringent industry standards for jitter performance, making them compliant with PCIe reference clock requirements. Highly efficient at sustaining signal integrity, they are well-suited to applications demanding high-frequency accuracy. Spanning nodes as advanced as 7nm FinFET, the LC-PLLs offer significant power savings and area efficiency. With their programmable loop bandwidth and robust noise cancellation features, they provide flexibility and resilience in demanding circuit environments, delivering top-tier performance in complex integration scenarios.
Silicon Creations' Analog Glue solutions enhance the clock management systems in semiconductors by providing essential analog macros that support the main silicon architectures. These solutions are vital in ensuring smooth on-chip operations by interconnecting various components reliably. These macros include components such as bandgap references, power-on reset (POR) generators, and clock distribution buffers, which significantly reduce integration complexities and enhance overall performance. They play a crucial role in maintaining the low-jitter operation and stable power conditions indispensable for advanced electronic systems. The Analog Glue macros are designed to complement PLLs and SerDes solutions, extending their functionality and broadening their applicability across different systems. By enabling efficient signal distribution and robust management, these components contribute critically to the performance and reliability of modern high-tech devices.
The Ring PLLs developed by Silicon Creations deliver comprehensive clocking solutions, specifically designed for modern system-on-chip (SoC) environments. Displaying a high level of adaptability, these PLLs excel in both general-purpose and specialized applications, efficiently addressing the clocking needs across various tech sectors. Fractional-N Ring PLLs exemplify the versatility of this lineup, offering multi-functional frequency synthesis capabilities with ultra-wide input and output ranges. With minimal jitter impact and moderate area consumption, these PLLs are well-suited for intricate clocking tasks in expansive SoC environments. They are particularly valuable in precision-timing applications such as data converters and SerDes clocking. Silicon Creations' Ring PLLs are recognized for their optimization potential, ensuring low power and low area occupancy without sacrificing performance. These qualities make them indispensable in devices that demand precision and reliability, from consumer electronics to advanced computing systems, all while providing excellent support for various process technologies.
The PDM-to-PCM Converter is a crucial element in digital audio processing, transforming pulse-density modulation signals into pulse-code modulation format. This conversion process ensures compatibility and improved sound clarity in digital audio systems. The converter is designed with flexibility in mind, easily integrating into existing systems to enhance audio capture and playback. Used extensively in consumer electronics such as smart speakers and headsets, it plays a vital role in delivering superior audio experiences. Its efficient design aligns with low power operation, benefiting mobile and portable audio devices.
The Origin E1 is a highly efficient neural processing unit (NPU) designed for always-on applications across home appliances, smartphones, and edge nodes. It is engineered to deliver approximately 1 Tera Operations per Second (TOPS) and is tailored for cost- and area-sensitive deployment. Featuring the LittleNPU architecture, the Origin E1 excels in low-power environments, making it an ideal solution for devices where minimal power consumption and area are critical. This NPU capitalizes on Expedera's innovative packet-based execution strategy, which allows it to perform parallel layer execution for optimal resource use, cutting down on latency, power, and silicon area. The E1 supports a variety of network types commonly used in consumer electronics, including Convolutional Neural Networks (CNNs), Recurrent Neural Networks (RNNs), and more. A significant advantage of Origin E1 is its scalability and market-leading power efficiency, achieving 18 TOPS/W and supporting standard, custom, and proprietary networks. With a robust software stack and support for popular AI frameworks like TensorFlow and ONNX, it ensures seamless integration into a diverse range of AI applications.
The Origin E8 neural processing unit (NPU) stands out for its extreme performance capabilities, designed to serve demanding applications such as high-end automotive systems and data centers. Capable of delivering up to 128 TOPS per core, this NPU supports the most advanced AI workloads seamlessly, whether in autonomous vehicles or data-intensive environments. By employing Expedera's packet-based architecture, Origin E8 ensures efficient parallel processing across layers and achieves impressive scalability without the drawbacks of increased power and area penalties associated with tiled architectures. It allows running extensive AI models that cater to both standard and custom requirements without compromising on model accuracy. The NPU features a comprehensive software stack and full support for a variety of frameworks, ensuring ease of deployment across platforms. Scalability up to PetaOps and support for resolutions as high as 8K make the Origin E8 an excellent solution for industries that demand unrivaled performance and adaptability.
Vehicle Engineering & Design Solutions by KPIT revolve around transforming vehicle development through cutting-edge design and simulation technologies. By employing advanced Computer Aided Design (CAD) and virtual prototyping, KPIT enhances product development and market entry speed. The focus is on aligning vehicle aesthetics with functional performance, ensuring that vehicles not only appeal to modern consumers but also comply with modern sustainability mandates. KPIT’s holistic approach offers comprehensive solutions that simplify the design and validation processes, fostering innovation in both conventional and electric vehicle configurations.
The AHB-Lite Timer from Roa Logic offers a robust timing solution compliant with the RISC-V Privileged 1.9.1 specification. This timer module provides essential timing functions within an embedded system, enabling precise control of tasks and schedule operations based on time criteria. Particularly suited to embedded applications, the AHB-Lite Timer ensures accurate timekeeping and scheduling capabilities. It is designed to deliver dependable performance over varied conditions, contributing to the robustness and reliability of embedded applications. Developers can integrate this timer into systems that require precise time management and event scheduling, supporting both simple and complex time-based functionalities. The AHB-Lite Timer is a critical component for applications where timing precision directly impacts system performance and reliability.
The Origin E2 is a versatile, power- and area-optimized neural processing unit (NPU) designed to enhance AI performance in smartphones, edge nodes, and consumer devices. This NPU supports a broad range of AI networks such as RNNs, LSTMs, CNNs, DNNs, and others, ensuring minimal latency while optimizing for power and area efficiency. Origin E2 is notable for its adaptable architecture, which facilitates seamless parallel execution across multiple neural network layers, thus maximizing resource utilization and providing deterministic performance. With performance capabilities scalable from 1 to 20 TOPS, the Origin E2 maintains excellent efficiency up to 18 TOPS per Watt, reflecting its superior design strategy over traditional layer-based solutions. This NPU's software stack supports prevalent frameworks like TensorFlow and ONNX, equipped with features such as mixed precision quantization and multi-job APIs. It’s particularly suitable for applications that require efficient processing of video, audio, and text-based neural networks, offering leading-edge performance in power-constrained environments.
The LVDS/OpenLDI solution from Silicon Library supports high-speed, low-power data transmission for displays and other digital interfaces. This technology is suited for various applications where efficient and reliable data transfer is necessary, including automotive displays and advanced computing systems. With LVDS/OpenLDI, devices can achieve high data rates over long distances with minimal crosstalk and electromagnetic interference. Its robust performance ensures that data integrity is maintained, even in challenging environments. This makes it ideal for settings where reliability and performance cannot be compromised. As a part of advanced digital systems, LVDS/OpenLDI contributes to reducing overall power consumption, an essential feature for battery-operated devices. The technology’s flexibility and efficiency make it a preferred choice for engineers looking to streamline data communication across different electronic ecosystems.
The APB4 GPIO by Roa Logic is a fully customizable input/output interface solution that encourages flexible integration of general-purpose pins into a broad range of electronic designs. Tailored to the needs of various applications, this GPIO core is designed to support bidirectional communication, offering assurances of performance and functionality. Each pin in the APB4 GPIO can be individually configured to act as either an input or an output, providing extensive adaptability for unique system requirements. This capability enhances system flexibility, allowing for precise control in managing peripheral interactions and communication. Its straightforward design and comprehensive configuration options make the APB4 GPIO a functional component for a variety of projects, ranging from simple circuit design to complex embedded systems requiring multiple interfaces. Its user-definable features ensure that it can meet bespoke needs, supporting a range of industry applications with precision and reliability.
The UART Serial Communication Controller is engineered to provide reliable asynchronous data transmission between processors and peripheral devices. The design includes support for variable data rates, ensuring flexibility in communication demands across different operational scenarios. This versatility makes it suitable for embedded systems where diverse data types and throughput requirements are needed. It supports the integration of various peripheral devices, thus enhancing the capability and scalability of the communications architecture within complex systems.
The Chimera GPNPU stands as a powerful neural processing unit tailor-made for on-device AI computing. This processor architecture revolutionizes the landscape of SoC design, providing a unified execution pipeline that integrates both matrix and vector operations with control code typically handled by separate cores. Such integration boosts developer productivity and enhances performance significantly. The Chimera GPNPU's ability to run diverse AI models—including classical backbones, vision transformers, and large language models—demonstrates its adaptability to future AI developments. Its scalable design enables handling of extensive computational workloads reaching up to 864 TOPs, making it suitable for a wide array of applications including automotive-grade AI solutions. This licensable processor core is built with a unique hybrid architecture that combines Von Neuman and 2D SIMD matrix instructions, facilitating efficient execution of a myriad array of data processing tasks. The Chimera GPNPU has been optimized for integration, allowing seamless incorporation into modern SoC designs for high-speed and power-efficient computing. Key features include a robust instruction set tailored for ML tasks, effective memory optimization strategies, and a systematic approach to on-chip data handling, all working to minimize power usage while maximizing throughput and computational accuracy. Furthermore, the Chimera GPNPU not only meets contemporary demands of AI processing but is forward-compatible with potential advancements in machine learning models. Through comprehensive safety enhancements, it addresses stringent automotive safety requirements, ensuring reliable performance in critical applications like ADAS and enhanced in-cabin monitoring systems. This combination of performance, efficiency, and scalability positions the Chimera GPNPU as a pivotal tool in the advancement of AI-driven technologies within industries demanding high reliability and long-term support.
The ABX Platform by Racyics utilizes Adaptive Body Biasing (ABB) technology to drive performance in ultra-low voltage scenarios. This platform is tailored for extensive applications requiring ultra-low power as well as high performance. The ABB generator, along with the standard cells and SRAM IP, form the core of the ABX Platform, providing efficient compensation for process variations, supply voltage fluctuations, and temperature changes.\n\nFor automotive applications, the ABX Platform delivers notable improvements in leakage power, achieving up to 76% reduction for automotive-grade applications with temperatures reaching 150°C. The platform's RBB feature substantially enhances leakage control, making it ideal for automotive uses. Beyond automotive, the ABX Platform's FBB functionality significantly boosts performance, offering up to 10.3 times the output at 0.5V operation compared to non-bias implementations.\n\nExtensively tested and silicon-proven, the ABX Platform ensures reliability and power efficiency with easy integration into standard design flows. The solution also provides tight cornering and ABB-aware implementations for improved Power-Performance-Area (PPA) metrics. As a turnkey solution, it is designed for seamless integration into existing systems and comes with a free evaluation kit for potential customers to explore its capabilities before committing.
The Mixed-Signal CODEC offered by Archband Labs stands out as a versatile solution integrating both analog and digital functionalities. This CODEC is designed to meet the demands of various audio and voice processing applications, ensuring high fidelity and low power consumption. Equipped with robust conversion capabilities, it's suitable for a range of environments from wearable tech to automotive systems, ensuring clear and precise sound reproduction. The CODEC forms a crucial part of devices like smart home appliances and AR/VR gadgets, where audio quality is paramount.
The Origin E6 NPU is engineered for high-performance on-device AI tasks in smartphones, AR/VR headsets, and other consumer electronics requiring cutting-edge AI models and technologies. This neural processing unit balances power and performance effectively, delivering between 16 to 32 TOPS per core while catering to a range of AI workloads including image transformers and point cloud analysis. Utilizing Expedera’s unique packet-based architecture, the Origin E6 offers superior resource utilization and ensures performance with deterministic latency, avoiding the penalties typically associated with tiled architectures. Origin E6 supports advanced AI models such as Stable Diffusion and Transformers, providing optimal performance for both current and predicted future AI workloads. The NPU integrates seamlessly into chip designs with a comprehensive software stack supporting popular AI frameworks. Its field-proven architecture, deployed in millions of devices, offers manufacturers the flexibility to design AI-enabled devices that maximize user experience while maintaining cost efficiency.
The Configurable I/O from SkyeChip encompasses a high-speed interface solution capable of supporting multiple I/O standards such as LVDS and POD. It enables signaling speeds up to 3.2 GT/s, accommodating a variety of voltage levels from 1.1V to 1.5V, enhancing its versatility across applications. This IP is engineered for flexibility, allowing integration with diverse system architectures, and supports various signaling standards effortlessly. Its design ensures robust data transmission capabilities, essential for high-performance computing and integrated system environments.
The GSHARK GPU IP accelerates graphics on embedded systems, delivering high performance with low power consumption while minimizing CPU load. Designed for embedded devices like digital cameras and automotive equipment, the GSHARK-IP leverages advanced proprietary architectures to achieve smooth graphics rendering akin to those seen on PCs and gaming consoles. Its proven track record with over a hundred million shipments highlights its reliability in commercial silicons.
The AXI4 DMA Controller is a multi-channel Verilog RTL IP core that manages data transfers with exceptional throughput across several large and small data sets. Supporting configurations from 1 to 16 channels, it features independent DMA Read and Write Controllers, utilizing AXI3 and AXI4 protocols to ensure efficient data handling across memory and peripherals. Its design accommodates intricate data transfer requirements, offering features such as scatter-gather linked lists and user-defined AXI burst lengths up to 256 beats. The DMA controller is adept in facilitating multiple concurrent data streams, enhancing performance for high-bandwidth applications.
Silicon Library's DisplayPort/eDP is crafted to deliver high-quality digital display interfaces for computing and multimedia devices. Supporting the latest standards for video and audio transmission, it enables seamless connectivity and communication between monitors, laptops, and graphic cards. This solution is engineered for high bandwidth efficiency, capable of handling high-definition video formats and high-fidelity audio without compromise. It’s suitable for a range of applications, from desktop monitors to embedded displays in portable devices, offering remarkable versatility and performance. With low power consumption and robust design, the DisplayPort/eDP ensures reliable and continuous operation in demanding environments. It supports the latest video protocols to facilitate advanced display technologies, meeting the growing demand for high-resolution and fast-refresh-rate environments.
The GV380 IP leverages OpenVG 1.1 standards to enhance vector graphic capabilities within embedded systems. This GPU IP focuses on reducing CPU load while boosting pixel performance, making it highly suited for environments requiring fast, efficient vector processing. Its architecture facilitates seamless graphics rendering that enriches user experiences across a variety of applications.
The KL730 AI SoC is equipped with a state-of-the-art third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computational power. This innovative architecture enhances computational efficiency, particularly with the latest CNN networks and transformer applications, while reducing DDR bandwidth demands. The KL730 excels in video processing, offering support for 4K 60FPS output and boasts capabilities like noise reduction, wide dynamic range, and low-light imaging. It is ideal for applications such as intelligent security, autonomous driving, and video conferencing.
The GV580 IP integrates both 2D and 3D graphics capabilities, adhering to OpenVG 1.1 and OpenGLES 1.1 standards. It provides a robust solution for rendering complex graphic scenes with high efficiency, promoting low power consumption and minimal CPU involvement. This GPU IP is designed for embedded systems that demand dynamic graphic displays while ensuring optimal system performance.
The I/O solutions provided by Analog Bits focus on delivering low-power, high-efficiency differential clocking and signaling capabilities. These IPs are designed for minimized transistor count while maintaining superior signaling quality, making them optimal for die-to-die communication. Customization is a key benefit, allowing for client-specific architectural arrangements that suit their exact needs while utilizing the smallest possible area and power budget.
The MIPI CSI2MUX-A1F is a CSI2 Video Multiplexer designed to aggregate inputs from up to four CSI2 cameras into a single output stream. Compliant with CSI2 rev 1.3 and DPHY rev 1.2, this video multiplexer can manage data transmission at 4 x 1.5Gbps. It's perfect for applications requiring efficient conversion from multiple image sources to a consolidated feed.
The DisplayPort Transmitter is designed to meet the VESA DisplayPort 1.4 standard, offering advanced functionality for high-performance video interface applications. This IP core is optimized for seamless integration into FPGA and ASIC platforms, facilitating high-speed data transfer for displays. With robust PHY interface options, it supports a wide range of process technologies, ensuring compatibility across different hardware setups.
The MIPI SVRPlus-8L-F is an advanced 8-lane, second-generation Serial Video Receiver designed specifically for FPGA applications. It supports CSI2 rev 2.0 and DPHY rev 1.2, allowing it to handle high-speed data transmission efficiently. The receiver can manage 16 virtual channels and provides 4 pixels output per clock cycle, complete with calibration support. Furthermore, it includes communication error statistics to ensure reliability.
The MIPI SVTPlus-8L-F is an innovative 8-lane, second-generation Serial Video Transmitter crafted for FPGA contexts. It aligns with CSI2 rev 2.0 and DPHY rev 1.2 standards, ensuring robust and efficient data transmission. Operating at a remarkable speed of 12Gbps, this transmitter is optimized for high-performance environments where precision and speed are paramount.
The RISC-V Hardware-Assisted Verification platform by Bluespec is engineered to offer an efficient and comprehensive approach to verifying RISC-V cores. It accelerates the verification process, allowing developers to confirm the functionality of their designs at both the core and system levels. The platform supports testing in diverse environments, including RTOS and Linux, which makes it versatile for a broad spectrum of applications. A distinguishing feature of this platform is its ability to verify standard ISA extensions as well as custom ISA extensions and accelerators. This capability is crucial for projects that require additional customization beyond the standard RISC-V instruction sets. Furthermore, by facilitating anytime, anywhere access through cloud-based solutions like AWS, it enhances the scalability and accessibility of verification processes. The platform is a valuable tool for developers who work on cutting-edge RISC-V applications, providing them with the confidence to validate their designs rigorously and efficiently. This verification tool is essential for developers aiming for high assurance in the correctness and performance of their systems.
The XCM_64X64_A provides a sophisticated architecture featuring 128 ADC 2-bit 1GSps with VGA front ends, designed for cross-correlation applications in NASA projects. Utilizing 45nm IBM SOI CMOS technology, it achieves ultra-low power consumption of approximately 0.5W for the entire array. The structure is geared towards synthetic radar receivers, radiometers, and spectrometers, operating at bandwidths from 10MHz to 500MHz. It integrates seamlessly into systems requiring precise data acquisition and processing, ideal for advanced research and observational instruments. With a focus on low power and high data throughput, the XCM_64X64_A addresses the challenges faced in high-energy physics and observational technology arenas. Its efficient power usage and robust design ensure long-term performance and reliability in demanding applications.
The Arria 10 System on Module (SoM) is designed with an emphasis on embedded and automotive vision applications. This compact module leverages Altera's Arria 10 SoC devices in a sleek 29x29 mm package, offering a plethora of interfaces while maintaining a small, efficient form factor. It features an Altera Arria 10 SoC FPGA with a range from 160 to 480 KLEs, coupled with a Cortex A9 Dual-Core CPU. This enables robust integration and performance for demanding applications. The module's power management system ensures a seamless power-up and -down sequence, requiring only a 12V supply from the baseboard. Its dual DDR4 memory interfaces provide up to 2.4 Gbit/s per pin, offering a total bandwidth of up to 230 Gbit/s for both CPU and FPGA memory systems. This module supports a wide array of high-speed interfaces, including PCIe Gen3 x8, 10/40 Gbit/s Ethernet, DisplayPort, and 12G SDI, making it suitable for complex imaging and communication tasks. Additional features include up to 32 LVDS lanes for configurable RX or TX, two USB interfaces with OTG support, and ARM I²C, SPI, and GPIO interface signals. Furthermore, the Arria 10 SoM includes pre-configured IP for memory controllers and an Angstrom Linux distribution, facilitating rapid development and deployment of applications.
The MVT4000D series are advanced digital temperature sensors designed to deliver precise and rapid temperature readings. Implementing Silicon Carbide MEMS technology, they guarantee excellent long-term stability and low power consumption. These sensors are especially useful in space-constrained environments due to their minute dimensions of 2.5 x 2.5 x 0.9 mm. They are calibrated digitally, providing high accuracy and fast response times, which make them suitable for applications where precise temperature monitoring is critical. The sensors can be integrated easily, thanks to their on-chip calibration, ensuring accuracy and reducing time-to-market for industrial, consumer, medical, and automotive applications. Featuring a digital I2C interface and supporting various resolutions from 8 to 14 bits, the MVT4000D sensors' technical highlights also include an operational temperature range between -40 to 125 °C. These features align them as optimal solutions for diverse and demanding application environments.
Analog Bits offers premier clocking solutions, known for their high customizability and low power consumption. These silicon-proven clocking solutions, available in 5nm nodes and onward, are renowned for ultra-low jitter and wide-range integer/fractional configurations. They are designed to serve diverse applications, such as consumer electronics, servers, and automotive technologies, ensuring the perfect balance of precision and performance. Their ability to adapt to specific customer needs makes them ideal for high-volume production environments.
The MIPI SVRPlus2500 is a sophisticated 4-lane video receiver that adheres to CSI2 rev 2.0 and DPHY rev 1.2 standards. Designed to support low clock ratings for simpler timing closure, it offers PRBS support and outputs 4/8/16 pixels per clock. This receiver incorporates 16 virtual channels and 1:16 input deserializers per lane, making it a versatile choice for intricate video applications. Handling data rates up to 4 x 2.5Gbps, it is built for high-efficiency environments.
The XCM_64X64 represents a complete cross-correlator solution with 64x64 channels, designed to cater to NASA's high-end synthetic radar receivers. Executed using IBM's 45nm SOI CMOS technology, this correlator emphasizes energy efficiency with a total power consumption of approximately 1.5W. It is engineered to support advanced radiometric and spectroscopic applications, with bandwidth capabilities ranging from 10MHz to 500MHz. The array's infrastructure supports precise signal analyses, making it ideal for use in scientific and exploratory sectors. Designed for optimum power-to-performance ratios, the XCM_64X64 excels in environments that demand high data integrity and reliable processing under stringent operational conditions. It is a vital component for synthetic aperture radar systems and other complex observational tools.
The Bluetooth Digital Clock in the Levo Series exemplifies cutting-edge wireless timekeeping solutions. This clock is particularly suited for settings that demand easy installation and the flexibility of wireless connectivity. It leverages Bluetooth technology to ensure precise time synchronization without the constraints of wired connections. Ideal for high-priority environments such as hospitals and educational institutions, the Levo Series offers unparalleled accuracy combined with the convenience of wireless operation. These digital clocks can quickly connect to a synchronized time source via Bluetooth, thereby maintaining the accurate and consistent time display required in such sensitive environments. Featuring a sleek and modern design, the Bluetooth Digital Clock fits seamlessly into any contemporary decor. Its digital display ensures clear readability from a distance, which is crucial in large spaces like lecture halls or hospital corridors. Moreover, the installation process is simplified due to the absence of complex wiring, making these clocks an excellent choice for dynamic environments looking to reduce installation time and cost. What sets the Levo Series apart is its adaptability and reliability, offering Bluetooth connectivity as a robust alternative to traditional networked clock systems. This ensures that time management remains unfettered by technical limitations typically associated with wired solutions, positioning it as the perfect blend of form and functionality for organizations looking to enhance their time synchronization infrastructure.
The DB9000AXI Display Controller is an advanced Verilog RTL IP core designed to interface frame buffer memory to various display panels, supporting resolutions from 320x240 to 1920x1080 Full HD, with capabilities expanding into 4K and 8K. It serves ASIC and FPGA design teams, providing a versatile platform for high-resolution display requirements. The controller supports on-chip AMBA interconnects to manage data flow between the processor, display, and frame buffer memory, ensuring optimal performance for graphics-rich applications. Optional features include hardware cursor, overlay windows, high dynamic range (HDR), and alpha blending, making it adaptable for diverse multimedia functionalities.
The Cortus Lotus 1 is a multifaceted microcontroller that packs a robust set of features for a range of applications. This cost-effective, low-power SoC boasts RISC-V architecture, making it suitable for advanced control systems such as motor control, sensor interfacing, and battery-operated devices. Operating up to 40 MHz, its RV32IMAFC CPU architecture supports floating-point operations and hardware-accelerated integer processing, optimizing performance for computationally demanding applications. Designed to enhance code density and reduce memory footprint, Lotus 1 incorporates 256 KBytes of Flash memory and 24 KBytes of RAM, enabling the execution of complex applications without external memory components. Its six independent 16-bit timers with PWM capabilities are perfectly suited for controlling multi-phase motors, positioning it as an ideal choice for power-sensitive embedded systems. This microcontroller's connectivity options, including multiple UARTs, SPI, and TWI controllers, ensure seamless integration within a myriad of systems. Lotus 1 is thus equipped to serve a wide range of market needs, from personal electronics to industrial automation, ensuring flexibility and extended battery life across sectors.
The MIPI SVTPlus2500 is an advanced 4-lane video transmitter that uses CSI2 rev 2.0 and DPHY rev 1.2 protocols. Optimized for easy timing closure through its low clock rating, it includes PRBS support and can handle 8/16 pixel input per clock. With the capability to manage 16 virtual channels at a speed of 4 x 2.5Gbps, this transmitter is ideal for dynamic video environments that demand flexibility and precise programmable timing parameters.
The SER12G is engineered for robust serialization of data streams from 8.5 to 11.3Gb/s, facilitating efficient signal integrity in high-speed data systems. Developed with IBM's 65nm 10LPe technology, it supports applications within SONET/SDH OC-192 transmitters and 10GbE systems. Focused on minimizing power usage, this serializer utilizes CML logic for high noise resistance, providing a line rate output data retiming at a 1V differential output swing. The SER12G’s well-structured CMU and PLL elements allow for seamless integration in high-performance systems requiring reliable data throughput. Fitting for use within advanced optical and backplane communication setups, the SER12G stands as an essential component in realizing high-speed, reliable data transmission. Its low power consumption aligns well with modern demands for energy-efficient network operations.