All IPs > Graphic & Peripheral
Graphic & Peripheral Semiconductor IPs are critical components in the design and development of electronics that require efficient and robust control over multimedia and peripheral functions. This category of semiconductor IP encompasses a wide array of technologies used to manage and optimize graphics rendering, audio processing, data communication, and peripheral interfaces in electronic devices such as computers, smartphones, tablets, and other smart gadgets.
In this vivid category, you'll find a variety of subcategories tailored to specific functionalities. For instance, the Graphics Processing Unit (GPU) semiconductor IPs are pivotal for rendering images and video, essential in gaming, virtual reality, and professional content creation. Audio Controllers handle sound processing, ensuring crisp and seamless audio output, crucial for devices prioritizing high-quality sound delivery.
Other key components in the Graphic & Peripheral category include Peripheral Controllers, which facilitate the integration of various input/output devices, enhancing the device's interactivity and user experience. DMA Controllers are responsible for moving data efficiently between memory and peripherals, minimizing the CPU load. These IPs enhance overall system performance by ensuring that data flow is smooth and uninterrupted.
From Clock Generators that synchronize the entire system's operations to Interrupt Controllers managing priority tasks, each semiconductor IP in this category plays a unique role in ensuring that electronic devices operate at peak efficiency. By exploring these subcategories, companies and developers can find the precise semiconductors needed to support cutting-edge multimedia and peripheral technologies in their next product launch.
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Silicon Creations' Free Running Oscillators deliver consistent and reliable clock outputs for applications that require high precision and low power. These oscillators are equipped to handle variations in power, temperature, and voltage (PVT) with minimal impact on performance. Their design ensures stability across these parameters, making them perfect for use in systems where consistent timing is crucial, such as communication systems and embedded devices. The low-power nature of these oscillators makes them especially suited to battery-powered devices, underscoring Silicon Creations’ focus on energy efficiency in cutting-edge semiconductor solutions.
Analog Glue solutions from Silicon Creations provide crucial analog functions such as differential buffers and multiplexers. These are essential for achieving low-jitter clock distribution and maintaining signal integrity across complex electronic systems. The analog glue functions integrate seamlessly with other Silicon Creations' IP and are tailored for low-power consumption, making them ideal for power-sensitive applications. By ensuring reliable power-on behavior and precision referencing, these solutions facilitate the smooth operation of various electronic applications that rely on precise analog functionalities.
The KL730 AI SoC is equipped with a state-of-the-art third-generation reconfigurable NPU architecture, delivering up to 8 TOPS of computational power. This innovative architecture enhances computational efficiency, particularly with the latest CNN networks and transformer applications, while reducing DDR bandwidth demands. The KL730 excels in video processing, offering support for 4K 60FPS output and boasts capabilities like noise reduction, wide dynamic range, and low-light imaging. It is ideal for applications such as intelligent security, autonomous driving, and video conferencing.
LVDS Interfaces by Silicon Creations are designed to facilitate high-speed and reliable data transmission. These interfaces are suitable for applications requiring efficient chip-to-chip communication, handling data rates up to 3.3Gbps. Featuring bi-directional capabilities and superb programmability, they can support a variety of standards and are engineered to deliver optimal signal integrity. Silicon Creations' use of robust PLLs and adaptive CDR technologies ensures the interfaces provide stable and precise alignment across all lanes. The impressive flexibility and performance of these interfaces make them ideal for a wide spectrum of modern digital applications.
KPIT provides state-of-the-art solutions for vehicle diagnostics and aftersales service, essential for the maintenance of software-intensive vehicles. The iDART framework offers comprehensive diagnostic functions and enhances service operations through AI-guided systems. This framework facilitates the transition to a unified, future-proof diagnostic ecosystem, reducing downtime and ensuring optimal vehicle performance. KPIT's solutions streamline complex diagnostic processes, making vehicles easier to manage and repair over their lifespans, enhancing customer satisfaction and loyalty.
KPIT's digital solutions harness cloud and edge analytics to modernize vehicle data management, optimizing efficiency and security in connected mobility. With a focus on overcoming data overload and ensuring compliance with regulatory standards, these solutions enable secure and scalable cloud environments for vehicle connectivity. The edge computing aspect enhances system responsiveness by processing data within vehicles, promoting innovation and dynamic feature development.
The LC-PLLs from Silicon Creations are characterized by their low jitter performance, making them suitable for demanding clocking tasks within integrated circuits. These PLLs integrate seamlessly into a variety of SoC architectures, providing ultra-low jitter thanks to their advanced design. Ideal for applications needing precision and stability, such as high-speed data transfer and timing critical operations, LC-PLLs feature a sophisticated design that supports both fractional-N and integer-N configurations. The focus on power efficiency and die area optimization makes them a valuable addition in environments where both performance and resource saving are crucial.
KPIT's engineering and design solutions focus on accelerating vehicle development through new-age design and simulation techniques. This approach enables cost-efficient transformation and adherence to sustainability standards, offering integrated electrification solutions and cutting-edge design methodologies. KPIT's solutions in vehicle engineering support electric and hybrid vehicle innovation with advanced CAD tools, virtual prototyping, and AI augmentation.
The Aries fgOTN processor family is engineered according to the ITU-T G.709.20 fgOTN standard. This line of processors handles a variety of signals, including E1/T1, FE/GE, and STM1/STM4, effectively monitoring and managing alarms and performance metrics. Aries processors excel at fine-grain traffic aggregation, efficiently channeling fgODUflex traffic across OTN lines to support Ethernet, SDH, PDH client services. Their capacity to map signals to fgODUflex containers, which are then multiplexed into higher order OTN signals, demonstrates their versatility and efficiency. By allowing cascaded configurations with other Aries devices or Apodis processors, Aries products optimize traffic routes through OTN infrastructures, positioning them as essential components in optical networking and next-generation access scenarios.
Origin E1 neural engines are expertly adjusted for networks that are typically employed in always-on applications. These include devices such as home appliances, smartphones, and edge nodes requiring around 1 TOPS performance. This focused optimization makes the E1 LittleNPU processors particularly suitable for cost- and area-sensitive applications, making efficient use of energy and reducing processing latency to negligible levels. The design also incorporates a power-efficient architecture that maintains low power consumption while handling always-sensing data operations. This enables continuous sampling and analysis of visual information without compromising on efficiency or user privacy. Additionally, the architecture is rooted in Expedera's packet-based design which allows for parallel execution across layers, optimizing performance and resource utilization. Market-leading efficiency with up to 18 TOPS/W further underlines Origin E1's capacity to deliver outstanding AI performance with minimal resources. The processor supports standard and proprietary neural network operations, ensuring versatility in its applications. Importantly, it accommodates a comprehensive software stack that includes an array of tools such as compilers and quantizers to facilitate deployment in diverse use cases without requiring extensive re-designs. Its application has already seen it deployed in over 10 million devices worldwide, in various consumer technology formats.
Archband Labs offers a PDM-to-PCM Converter that excels in translating Pulse Density Modulated (PDM) audio signals into Pulse Code Modulated (PCM) format. This conversion is crucial in audio signal processing where digital formats require conversions for accurate playback or further audio processing. Ideal for modern multimedia systems and portable audio devices, the PDM-to-PCM Converter provides high fidelity in signal conversion, ensuring sound quality is preserved during the process. This IP is highly efficient, making it perfect for applications where power conservation is important, such as battery-powered gadgets and smart wearables. Its compact design provides easy integration into existing systems, facilitating upgrades without significant redesigns. With reliable performance, this converter supports the growing demand for adaptable and high-efficiency audio processing solutions, aiding engineers in achieving cutting-edge audio clarity.
The AHB-Lite Timer is a peripheral module aligned with the RISC-V Privileged 1.9.1 specification, offering precise timekeeping capabilities within embedded systems. This timer IP is integral for applications requiring accurate timing operations and management, enhancing control over timing-related tasks.
Designed for high-performance environments such as data centers and automotive systems, the Origin E8 NPU cores push the limits of AI inference, achieving up to 128 TOPS on a single core. Its architecture supports concurrent running of multiple neural networks without context switching lag, making it a top choice for performance-intensive tasks like computer vision and large-scale model deployments. The E8's flexibility in deployment ensures that AI applications can be optimized post-silicon, bringing performance efficiencies previously unattainable in its category. The E8's architecture and sustained performance, alongside its ability to operate within strict power envelopes (18 TOPS/W), make it suitable for passive cooling environments, which is crucial for cutting-edge AI applications. It stands out by offering PetaOps performance scaling through its customizable design that avoids penalties typically faced by tiled architectures. The E8 maintains exemplary determinism and resource utilization, essential for running advanced neural models like LLMs and intricate ADAS tasks. Furthermore, this core integrates easily with existing development frameworks and supports a full TVM-based software stack, allowing for seamless deployment of trained models. The expansive support for both current and emerging AI workloads makes the Origin E8 a robust solution for the most demanding computational challenges in AI.
Silicon Creations provides a wide range of ring PLLs, offering robust clocking solutions for modern SoC environments. These PLLs deliver highly programmable frequency synthesis with considerations for power efficiency and minimal jitter. With flexibility in both fractional-N and integer-N configurations, they cater to diverse application needs ranging from system clocking to precision converter timing. Particularly notable is the capability to achieve excellent jitter performance with substantial power and area savings when compared to traditional designs. This makes Silicon Creations' ring PLLs a go-to choice for applications spanning battery-operated devices and high-performance computing systems.
The Apodis family of Optical Transport Network processors adheres to ITU-T standards, offering a comprehensive suite for signal termination, processing, and multiplexing. Designed to handle both SONET/SDH and Ethernet client services, these processors map signals to Optical Transport Network (OTN), empowering versatile any-port, any-service configurations. Apodis processors are notable for their capacity to support up to 16 client ports and four 10G OTN line ports, delivering bandwidth scalability up to 40G, crucial for wireless backhaul and fronthaul deployments. With a robust, non-blocking OTN switching fabric, Apodis facilitates seamless client-to-line and line-to-line connections while optimally managing network bandwidth. This adaptability makes the Apodis processors an ideal choice for next-generation access networks and optical infrastructures.
The Origin E2 family of NPU cores is tailored for power-sensitive devices like smartphones and edge nodes that seek to balance power, performance, and area efficiency. These cores are engineered to handle video resolutions up to 4K, as well as audio and text-based neural networks. Utilizing Expedera’s packet-based architecture, the Origin E2 ensures efficient parallel processing, reducing the need for device-specific optimizations, thus maintaining high model accuracy and adaptability. The E2 is flexible and can be customized to fit specific use cases, aiding in mitigating dark silicon and enhancing power efficiency. Its performance capacity ranges from 1 to 20 TOPS and supports an extensive array of neural network types including CNNs, RNNs, DNNs, and LSTMs. With impressive power efficiency rated at up to 18 TOPS/W, this NPU core keeps power consumption low while delivering high performance that suits a variety of applications. As part of a full TVM-based software stack, it provides developers with tools to efficiently implement their neural networks across different hardware configurations, supporting frameworks such as TensorFlow and ONNX. Successfully applied in smartphones and other consumer electronics, the E2 has proved its capabilities in real-world scenarios, significantly enhancing the functionality and feature set of devices.
The AI Camera Module from Altek is an innovative integration of image sensor technology and intelligent processing, designed to cater to the burgeoning needs of AI in imaging. It combines rich optical design capabilities with software-hardware amalgamation competencies, delivering multiple AI camera models that assist clients in achieving differentiated AI + IoT needs. This flexible camera module excels in edge computing by supporting high-resolution requirements such as 2K and 4K, thereby becoming an indispensable tool in environments demanding detailed image analysis. The AI Camera Module allows for superior adaptability in performing functions such as facial detection and edge computation, thus broadening its applicability across industries. Altek's collaboration with major global brands fortifies the AI Camera Module's position in the market, ensuring it meets diverse client specifications. Whether used in security, industrial, or home automation applications, this module effectively integrates into various systems to deliver enhanced visual processing capabilities.
The KL630 AI SoC embodies next-generation AI chip technology with a pioneering NPU architecture. It uniquely supports Int4 precision and transformer networks, offering superb computational efficiency combined with low power consumption. Utilizing an ARM Cortex A5 CPU, it supports a range of AI frameworks and is built to handle scenarios from smart security to automotives, providing robust capability in both high and low light conditions.
Digital Blocks' UART Serial Communication Controller provides a reliable and efficient solution for synchronous and asynchronous serial data communication. Supporting a range of baud rates, this controller is designed to interface with microprocessors via AMBA buses and can be configured to suit various communication protocols and settings. The IP core's flexibility and robust performance make it suitable for use in embedded systems, industrial control, and any application requiring dependable serial communication.
Digital Blocks' AXI4 DMA Controller is engineered for high-efficiency data transfer in embedded systems. It is a multi-channel controller that allows for 1 to 16 independent data transfers, with adaptability for various data sizes and configurations. This controller supports complex data transfer schemes like scatter-gather with linked-lists, interrupt reporting, and can handle large bursts of data efficiently due to its extensive support for both AXI3 and AXI4 protocols. It's designed for uses requiring high throughput and reliability, making it particularly suitable for performance-critical aerospace and communications applications.
XDS offers a specialized platform for the design and simulation of RF and microwave circuits. Its precision-focused tools provide detailed insights into electromagnetic performance critical to the development of modern RF systems. XDS excels in modeling the complex interactions inherent in these high-frequency designs, facilitating optimized circuit performance and reliability. With its robust simulation capabilities, XDS empowers designers to visualize and address potential performance challenges before practical implementation. This foresight in design allows for the crafting of circuits that are not only efficient but also resilient to real-world interferences and stresses. Engineers utilizing XDS benefit from its ability to streamline the design process, reducing development time while enhancing product functionality and performance. The tool is a vital asset for those focused on advancing RF technologies and maintaining best-in-class standards in microwave circuit design.
The ABX Platform by Racyics utilizes Adaptive Body Biasing (ABB) technology to drive performance in ultra-low voltage scenarios. This platform is tailored for extensive applications requiring ultra-low power as well as high performance. The ABB generator, along with the standard cells and SRAM IP, form the core of the ABX Platform, providing efficient compensation for process variations, supply voltage fluctuations, and temperature changes.\n\nFor automotive applications, the ABX Platform delivers notable improvements in leakage power, achieving up to 76% reduction for automotive-grade applications with temperatures reaching 150°C. The platform's RBB feature substantially enhances leakage control, making it ideal for automotive uses. Beyond automotive, the ABX Platform's FBB functionality significantly boosts performance, offering up to 10.3 times the output at 0.5V operation compared to non-bias implementations.\n\nExtensively tested and silicon-proven, the ABX Platform ensures reliability and power efficiency with easy integration into standard design flows. The solution also provides tight cornering and ABB-aware implementations for improved Power-Performance-Area (PPA) metrics. As a turnkey solution, it is designed for seamless integration into existing systems and comes with a free evaluation kit for potential customers to explore its capabilities before committing.
The APB4 GPIO core is fully parameterized, offering customizable general-purpose input/output configurations tailored to user specifications. This flexibility makes it ideal for various applications where diverse IO functionalities are needed, supporting bidirectional data flow with minimal integration complexity.
The Configurable I/O from SkyeChip encompasses a high-speed interface solution capable of supporting multiple I/O standards such as LVDS and POD. It enables signaling speeds up to 3.2 GT/s, accommodating a variety of voltage levels from 1.1V to 1.5V, enhancing its versatility across applications. This IP is engineered for flexibility, allowing integration with diverse system architectures, and supports various signaling standards effortlessly. Its design ensures robust data transmission capabilities, essential for high-performance computing and integrated system environments.
The RISC-V Hardware-Assisted Verification platform by Bluespec is engineered to offer an efficient and comprehensive approach to verifying RISC-V cores. It accelerates the verification process, allowing developers to confirm the functionality of their designs at both the core and system levels. The platform supports testing in diverse environments, including RTOS and Linux, which makes it versatile for a broad spectrum of applications. A distinguishing feature of this platform is its ability to verify standard ISA extensions as well as custom ISA extensions and accelerators. This capability is crucial for projects that require additional customization beyond the standard RISC-V instruction sets. Furthermore, by facilitating anytime, anywhere access through cloud-based solutions like AWS, it enhances the scalability and accessibility of verification processes. The platform is a valuable tool for developers who work on cutting-edge RISC-V applications, providing them with the confidence to validate their designs rigorously and efficiently. This verification tool is essential for developers aiming for high assurance in the correctness and performance of their systems.
The G-Series Controller is designed for high-speed data processing tasks in graphical and video-intensive applications. It supports JEDEC-compliant GDDR6 for speeds up to 18 Gbps, offering dual channels with integrated automatic retry features and a highly flexible design architecture. Its support for a hardware and software calibration routine ensures accurate performance across platforms. The G-Series solution delivers the throughput needed for AI, ADAS, and advanced gaming technologies, establishing itself as a formidable solution for next-generation high-performance applications.
Designed for sprite graphics, the GH310 IP focuses on delivering high pixel processing capabilities while maintaining a minimal gate count. This efficiency makes it an ideal solution for embedded systems where space and power efficiency are critical. With its ability to balance high performance and low resource usage, GH310 is perfect for applications that require consistent and rapid 2D image rendering. It helps maintain performance even under demanding conditions, enhancing user experiences in devices ranging from consumer electronics to automotive displays.
The MIPITM CSI2MUX-A1F operates as a sophisticated CSI2 video multiplexor designed to handle multiple camera inputs simultaneously. In compliance with CSI2 rev 1.3 and DPHY rev 1.2 standards, this multiplexor can manage inputs from up to four CSI2 cameras, consolidating them into a single comprehensive video stream. Engineered for high-efficiency video streamlining, it operates at a data rate of 4 x 1.5Gbps, ensuring real-time processing and efficient data throughput. The ability to integrate multiple video feeds into a single output makes it suitable for systems requiring complex multimedia handling and advanced video applications. This multiplexor provides solutions for systems where video data from various sources needs to be aggregated efficiently, optimizing space and resource utilization across video interfaces. Its seamless integration expands its utility across multiple paradigms, making it a staple in any comprehensive video system architecture.
Origin E6 NPU cores are cutting-edge solutions designed to handle the complex demands of modern AI models, specializing in generative and traditional networks such as RNN, CNN, and LSTM. Ranging from 16 to 32 TOPS, these cores offer an optimal balance of performance, power efficiency, and feature set, making them particularly suitable for premium edge inference applications. Utilizing Expedera’s innovative packet-based architecture, the Origin E6 allows for streamlined multi-layer parallel processing, ensuring sustained performance and reduced hardware load. This helps developers maintain network adaptability without incurring latency penalties or the need for hardware-specific optimizations. Additionally, the Origin E6 provides a fully scalable solution perfect for demanding environments like next-generation smartphones, automotive systems, and consumer electronics. Thanks to a comprehensive software suite based around TVM, the E6 supports a broad span of AI models, including transformers and large language models, offering unparalleled scalability and efficiency. Whether for use in AR/VR platforms or advanced driver assistance systems, the E6 NPU cores provide robust solutions for high-performance computing needs, facilitating numerous real-world applications.
The Chimera GPNPU series stands as a pivotal innovation in the realm of on-device artificial intelligence computing. These processors are engineered to address the challenges faced in machine learning inference deployment, offering a unified architecture that integrates matrix, vector, and scalar operations seamlessly. By consolidating what traditionally required multiple processors, such as NPUs, DSPs, and real-time CPUs, into a single processing core, Chimera GPNPU reduces system complexity and optimizes performance. This series is designed with a focus on handling diverse, data-parallel workloads, including traditional C++ code and the latest machine learning models like vision transformers and large language models. The fully programmable nature of Chimera GPNPUs allows developers to adapt and optimize model performance continuously, providing a significant uplift in productivity and flexibility. This capability ensures that as new neural network models emerge, they can be supported without the necessity of hardware redesign. A remarkable feature of these processors is their scalability, accommodating intensive workloads up to 864 TOPs and being particularly suited for high-demand applications like automotive safety systems. The integration of ASIL-ready cores allows them to meet stringent automotive safety standards, positioning Chimera GPNPU as an ideal solution for ADAS and other automotive use cases. The architecture's emphasis on reducing memory bandwidth constraints and energy consumption further enhances its suitability for a wide range of high-performance, power-sensitive applications, making it a versatile solution for modern automotive and edge computing.
Silicon Library's DisplayPort/eDP IP delivers a versatile solution for high-definition display interfaces, empowering a wide range of electronic devices to transmit and receive vivid visual content. Compatible with the latest DisplayPort standards, this IP supports robust data throughput, making it ideal for demanding applications like high-resolution monitors, gaming displays, and sophisticated multimedia setups. The DisplayPort Tx/Rx IP supports a data rate of up to 8.1 Gbps per channel, enabling efficient transmission of complex visual streams and ensuring clarity and depth in displayed content. This makes it suitable for devices that require high-bandwidth audio-visual data communication, enforcing seamless integration into electronic products ranging from PCs and tablets to monitors and high-end home cinema systems. With strong focus on performance and reliability, DisplayPort/eDP IP employs advanced protocols to manage bandwidth allocation while maintaining signal integrity over various transmission lengths. Optional integration of HDCP (High-bandwidth Digital Content Protection) ensures secure data exchange, reinforcing content protection across transmission networks.
GV380 provides advanced vector graphics capabilities with a focus on OpenVG 1.1 compliance. This GPU utilizes a fourth-generation architecture designed to reduce CPU load while maximizing pixel processing efficiency. GV380 targets embedded systems that require efficient and seamless vector graphics rendering, significantly reducing the processing burden on the main CPU. By delivering high pixel performance, this IP is instrumental in enabling enhanced human-machine interfaces and improving graphical user experiences on embedded platforms.
The Orion MFH IP Cores are designed for optimal performance in 4G mobile fronthaul networks, compliant with the ITU-T specifications for CPRI signal multiplexing. They adeptly handle various CPRI options, ranging from 2.4576 Gbps to 12.16512 Gbps, ensuring high compatibility and performance. Featuring both muxponder and transponder configurations, Orion cores facilitate the efficient mapping and transport of CPRI signals via Optical Transport Network infrastructures, ideal for modern telecommunications frameworks. Their advanced capabilities enable telecommunications providers to enhance their network reliability and service delivery, adapting seamlessly to different fronthaul scenarios.
The xcore.ai platform stands as an economical and high-performance solution for intelligent IoT applications. Designed with a unique multi-threaded micro-architecture, it supports applications requiring deterministic performance with low latency. The architecture features 16 logical cores, split between two multi-threaded processor tiles, which are equipped with 512 kB of SRAM and a vector unit for both integer and floating-point computations. This platform excels in enabling high-speed interprocessor communications, allowing tight integration among processors and across multiple xcore.ai SoCs. The xcore.ai offers scalable performance, adapting the tile clock frequency to meet specific application requirements, which optimizes power consumption. Its ability to handle DSP, AI/ML, and I/O processing within a singular development environment makes it a versatile choice for creating smart, connected products. The adaptability of the xcore.ai extends to various market applications such as voice and audio processing. It supports embedded PHYs for MIPI, USB, and LPDDR control processing, and utilizes FreeRTOS across multiple threads for robust multi-threading performance. On an AI and ML front, the platform includes a 256-bit vector processing unit that supports 8-bit to 32-bit operations, delivering exceptional AI performance with up to 51.2 GMACC/s. All these features are packaged within a development environment that simplifies the integration of multiple application-specific components. This makes xcore.ai an essential platform for developers aiming to leverage intelligent IoT solutions that scale with application needs.
The DisplayPort Transmitter from Trilinear Technologies offers a robust solution for high-quality video and audio signal transmission. Designed with compliance and compatibility in mind, this transmitter ensures seamless integration with various display devices, supporting a wide array of resolutions and audio formats. Its advanced features facilitate reliable performance across multiple platforms, upholding Trilinear's reputation for excellence in connectivity products. Engineered to handle the intricacies of digital video transfer, Trilinear's DisplayPort Transmitter integrates smoothly into systems, delivering high-speed data transfer while minimizing signal disruptions. This IP's architecture supports adaptive sync technologies, optimizing refresh rates for improved picture clarity and reduced latency. Through rigorous in-lab testing, it consistently meets industry standards, providing manufacturers with a dependable component for their product designs. Incorporating the DisplayPort Transmitter into a design not only boosts the performance but also extends the product life cycle by ensuring that it stays aligned with emerging digital protocol standards. Its design is forward-thinking, allowing for updates and upgrades as new technology becomes available, thus safeguarding investments. This IP is crucial for any developer aiming to produce top-tier, future-ready display solutions.
Combining 2D and 3D rendering capabilities, GV580 is engineered to optimize both OpenVG 1.1 and OpenGLES 1.1 graphics standards. This IP integrates high-performance rendering with low power consumption and minimal CPU dependency, making it suitable for embedded systems demanding advanced graphical capabilities. The IP enables immersive graphical experiences and applications that range from high-definition user interfaces to complex scenes in automotive and consumer electronics. By merging advanced graphics technology with efficient energy use, GV580 is a robust choice for multifaceted embedded graphics applications.
Dolphin Technology's I/O products encompass a vast selection of interface IPs known for their high-performance capabilities. These I/O components are designed to complement various process technologies, ensuring reliability and efficiency in applications ranging from core limited designs to flip-chip utilizations. The product range includes standard I/O, high-speed I/O, and specialty interface I/O that can be customized for specific design requirements. The portfolio comprises various specialized I/Os like High Voltage Tolerant GPIO, LVDS Tx/Rx, and several DDR and SD IO variations, each built to meet demanding design specifications. Dolphin Technology’s offerings are fully equipped with compilers that allow for customization, ensuring each I/O library can be tailored to address process and chip-specific needs, thereby delivering optimal performance and versatility. These I/O solutions are available in multiple forms, including inline styles and flip-chip arrangements, which assist in the efficient use of space and signal integrity in complex semiconductor designs. The capability to integrate with different technology levels further broadens the applicability of these products, making them suitable for a diverse set of industry requirements.
The Mixed-Signal CODEC offered by Archband Labs is engineered to enhance the performance of audio and voice devices, handling conversions between analog and digital signals efficiently. Designed to cater to various digital audio interfaces such as PWM, PDM, PCM conversions, I2S, and TDM, it ensures seamless integration into complex audio systems. Well-suited for low-power and high-performance applications, this CODEC is frequently deployed in audio systems across consumer electronics, automotive, and edge computing devices. Its robust design ensures reliable operation within wearables, smart home devices, and advanced home entertainment systems, handling pressing demands for clarity and efficiency in audio signal processing. Engineers benefit from its extensive interfacing capabilities, supporting a spectrum of audio inputs and outputs. The CODEC's compact architecture ensures ease of integration, allowing manufacturers to develop innovative and enhanced audio platforms that meet diverse market needs.
The APB4 Multiplexer is designed to allow a single APB4 Master to interface with multiple APB4 Slaves using a common communication bus. This IP is pivotal in simplifying connections within a system, enabling efficient data routing among peripheral devices. The functionality of the APB4 Multiplexer is crucial in optimizing the use of resources in an embedded system environment.
The Digital Blocks DB9000-AXI Multi-Channel DMA Controller is a robust IP core supporting extensive data transfer protocols through its multi-channel architecture. Each channel operates independently, enabling efficient management of diverse data streams concurrently. Designed for high throughput, this controller supports various burst transfer sizes and integrates seamlessly with the AXI interconnect fabric, offering exceptional performance in data-heavy applications such as computing and network processing. Its architecture supports user-programmed features to tailor data transfer strategies, optimizing system performance and reducing power consumption.
GSHARK is a family of GPU cores targeted for embedded devices, such as digital cameras and automotive systems. Known for its high performance and low power consumption, GSHARK effectively minimizes the CPU load while maintaining outstanding graphic rendering capabilities. This solution supports high reliability, proven by millions of shipments within commercial silicon. The architecture of GSHARK adapts PC, smartphone, and console-grade graphics technologies to embedded systems, enhancing the user experience in human-machine interfaces. Its capability to handle dynamic graphics with low resource usage makes it an ideal choice for embedded systems.
xT CDx is an advanced genomic profiling solution used for comprehensive tumor and normal matched testing in oncology. With a focus on solid tumors, xT CDx leverages extensive gene coverage to aid in clinical decision-making. The system utilizes high-depth sequencing to provide actionable insights, aligning genomic findings with targeted therapy options. The platform is renowned for its substantial coverage of exons and is accredited for detecting a wide array of variants that contribute significantly to personalized medicine. As an in vitro diagnostic system, xT CDx is designed to serve as a companion diagnostic tool for oncologists, particularly in tailoring treatments that align with existing therapeutic guidelines. Its sophisticated analytical capabilities ensure that oncologists have the support they need to match patient profiles with clinical trials and approved treatments promptly. This facilitates a genomic-centric approach, integrating DNA sequencing insights into the broader clinical workflow. Incorporating both tumor and normal tissue comparisons, xT CDx is able to discern hereditary traits that might influence cancer treatment. This dual-approach testing enhances the diagnosis accuracy and optimizes treatment pathways, setting a new standard in oncology precision testing.
The ADQ35 is a versatile dual-channel digitizer designed for high-performance data acquisition at a sampling rate of 10 GSPS. With its flexible configuration, the ADQ35 supports both a two-channel operation at 5 GSPS and a single-channel mode at the full 10 GSPS. The device is DC-coupled with a bandwidth capacity of up to 2.5 GHz, which suits it for a variety of conditions where signal integrity is key. A highlight of the ADQ35 is its open onboard Xilinx Kintex Ultrascale KU115 FPGA, offering extensive capabilities for custom digital signal processing. This device also facilitates peer-to-peer streaming at a rapidity of 14 Gbyte/s, enabling direct and efficient data transfer to GPUs or CPUs. This makes it exceptional for applications that rely on large-scale data handling and processing efficiency. The ADQ35 is engineered for use in various high-demand applications such as Time-of-Flight Mass Spectrometry, LiDAR systems, and scientific instrumentation. This flexibility is further enhanced by an array of standard and optional firmware packages, which empower users to tailor the device's capabilities according to specific project needs.
The Cortus Lotus 1 is a multifaceted microcontroller that packs a robust set of features for a range of applications. This cost-effective, low-power SoC boasts RISC-V architecture, making it suitable for advanced control systems such as motor control, sensor interfacing, and battery-operated devices. Operating up to 40 MHz, its RV32IMAFC CPU architecture supports floating-point operations and hardware-accelerated integer processing, optimizing performance for computationally demanding applications. Designed to enhance code density and reduce memory footprint, Lotus 1 incorporates 256 KBytes of Flash memory and 24 KBytes of RAM, enabling the execution of complex applications without external memory components. Its six independent 16-bit timers with PWM capabilities are perfectly suited for controlling multi-phase motors, positioning it as an ideal choice for power-sensitive embedded systems. This microcontroller's connectivity options, including multiple UARTs, SPI, and TWI controllers, ensure seamless integration within a myriad of systems. Lotus 1 is thus equipped to serve a wide range of market needs, from personal electronics to industrial automation, ensuring flexibility and extended battery life across sectors.