All IPs > Analog & Mixed Signal > PLL
The Analog & Mixed Signal PLL (Phase-Locked Loop) category of semiconductor IP at Silicon Hub encompasses a collection of sophisticated circuit designs used primarily for frequency synthesis, clock management, and timing in integrated circuits. PLLs are indispensable in a variety of electronic applications where synchronized frequency and phase-locked signals are crucial. This class of semiconductor IPs is pivotal for ensuring stable and reliable operations in digital and analog systems alike.
PLLs are widely utilized in communication systems, consumer electronics, and computing devices. In communication systems, they play a critical role in modulating and demodulating signals, ensuring accurate data transmission. Consumer electronics, such as smartphones, tablets, and gaming devices, leverage PLL technology to maintain accurate system clocks, which is essential for digital signal processing and multimedia performance. In computing, PLLs help in maintaining synchronous operations between processors and memory, allowing seamless multitasking and high-speed data processing.
Within this category, you will find a variety of PLL designs and architectures, each tailored to specific application needs, including fractional-N PLLs, integer-N PLLs, and Delay-Locked Loops (DLLs). These variants offer different advantages, such as reduced phase noise, higher frequency stability, and improved design flexibility. Additionally, some advanced PLL IPs incorporate features like spread spectrum clocking to minimize electromagnetic interference, making them suitable for use in sensitive electronic environments.
Overall, the Analog & Mixed Signal PLL semiconductor IPs available at Silicon Hub are integral components that help optimize the performance, efficiency, and reliability of modern electronic systems. They enable designers and engineers to tackle complex clocking requirements and achieve precise control over signal timing, which is a cornerstone of innovation in technology sectors ranging from telecom to computing and beyond.
The CoreVCO represents a dual wideband VCO solution, crucial for applications requiring extensive frequency ranges and minimal phase noise. Utilizing both SiGe CMOS and BJT technologies, it offers superior performance across a broad spectrum, from 0.7GHz to 6.6GHz. Designed with radiation hardening, this VCO is highly reliable for demanding environments like space and defense communications, encapsulated in a compact QFN48 package optimized for high-efficiency RF output.
LC-PLLs by Silicon Creations are engineered for ultra-low jitter and high precision across demanding applications such as analog front-end converters and RF clocking. They introduce advanced fractional-N architecture, highlighted by a small footprint and low power operation. Proven in cutting-edge process nodes like 7nm FinFET, these LC-PLLs deliver jitter metrics that meet stringent industry standards. With customizable loop bandwidths and fine-tuned jitter attenuation mechanisms, they excel in scenarios requiring high-speed, low-noise clock references, such as PCI Express applications.
The pPLL03F-GF22FDX is part of Perceptia's second-generation all-digital PLLs, tailored for high-stakes clocking needs in performance computing applications. Designed for clocking solutions with critical timing demands, this PLL provides fractional multiplication up to 4GHz with exceptionally low jitter. Its architecture allows the pPLL03F to fit in compact areas, under 0.01 sq mm, while maintaining power consumption below 5mW. Such attributes make it a prime candidate for SoCs with extensive clock domains, where each domain might be individually driven by a PLL. The design includes built-in regulation, enabling shared power supplies between the PLL and its associated blocks, simplifying integration. pPLL03F incorporates dual PLL outputs from separate postscalers, programmable up to a factor of 2,040, and offers enhanced testability through standard ATPG vectors. Its versatile application potential spans high-speed digital processing and moderate-SNR ADC/DAC setups, further enriched by Perceptia's support services for customization and migration.
Ring PLLs are a cornerstone in Silicon Creations' clocking solutions, providing flexibility and robustness across a range of applications. These PLLs offer a broad operational range, making them suitable for generating clocks for diverse system-on-chip (SoC) applications. They feature attributes like fractional multiplication, jitter cleaning capabilities, and programmable loop bandwidths, which cater to both general-purpose and specialized demands. Available across major foundries and process nodes including the latest FinFETs, these IPs ensure low jitter and power consumption, making them an excellent choice for precision-centric designs.
VCOMB12G is a multi-band differential LC VCO, designed for low noise operations. With its tested configuration on an ASIC, it covers a wide frequency range and provides support for various clocking modes suited for phase-locked loops and fiber optic applications. This block enhances power efficiency and performance, optimized for critical communications applications.
The CorePLL is a highly versatile frequency synthesizer that combines low power consumption with top-notch performance in a compact package. Drawing just 18mA from a 1.35V power supply, the CorePLL integrates multiple phase-locked loops with voltage-controlled oscillators and loop filters, supporting inter-band carrier aggregation. Suited for a wide array of applications, from wireless systems to automotive, the CorePLL caters to the need for high-frequency precision with its scalable design that adapts to various frequency bands.
The Integer-N PLL-based HF Frequency Synthesizer and Clock Generator is a high-frequency solution that generates square-wave frequencies within a selected range. Engineered with an integrated loop filter and VCO, this IP is capable of producing constant frequency outputs with exceptional precision. Ideal for high-speed communication systems, this synthesizer is silicon-proven in XFAB's XT018 technology and can be adapted to other technology nodes. It is perfect for demanding communication and data transfer applications requiring stable and accurate clock signals.
The High-Speed PLL offered by SkyeChip is a precision-optimized phase lock loop solution supporting a reference clock frequency range from 100 MHz to 350 MHz. The output frequency spans from 300 MHz to 3.2 GHz, facilitated by a flexible FBDIV and POSTDIV configuration, accommodating various frequency divisions. This PLL is tailored for applications requiring high-frequency clock generation, offering a robust solution for integrated circuit designs necessitating fast and reliable clock synchronization in electronically dense environments.
The pPLL08 Family is a set of all digital fractional-N RF frequency synthesizer PLLs, specifically designed for RF applications like 5G and WiFi. These PLLs are notable for their exceptionally low jitter and compact area, enabling optimal performance in high-frequency environments up to 8GHz. Employing a second-generation digital PLL architecture, the pPLL08 family features a LC tank oscillator to achieve industry-leading phase noise performance while maintaining low power consumption below 15mW. Its design ensures minimal interference from other chip components, crucial for supporting high SNDR in RF systems. This makes it particularly suitable for use as a local oscillator or for clocking ADCs/DACs with stringent SNR requirements. Available in multiple technologies, including prominent foundries like Samsung and TSMC, the pPLL08 family boasts flexibility and integration simplicity, complete with models and views essential for backend flows. Additionally, Perceptia offers customization and technical support to adapt this PLL to various deployment scenarios, ensuring that it fits perfectly within its intended application environment.
The VCO24G is a 24GHz VCO built on the robust Colpitts design which is appreciated for its low noise characteristics. It is developed using the cost-effective TowerJazz's 0.18um SiGe technology. Given its architectural efficacy in minimizing noise, it's an excellent component for PLLs and broadband test and measurement equipment, offering a balance between cost and high-frequency performance.
M31's Analog Phase-Locked Loop (PLL) IP is a versatile frequency synthesizer featuring a broad input reference range between 10 and 240 MHz, with an output scaling from 1.5 to 3.0 GHz. Designed with a Type-II architecture utilizing a sigma delta modulator for fractional frequency adjustments, this PLL achieves notable power supply noise rejection, crucial for operating within noisy SoC environments. Its streamlined integration approach eliminates complex configurations, providing a no-fuss solution for applications needing robust frequency control. This IP offers wide compatibility and flexibility for deployment in a multitude of consumer and industrial electronic applications.
CoreHW's mmWave PLL IP is engineered for high-frequency applications, combining a high-precision fractional-N PLL with a low-noise VCO to produce clear, low-phase noise carriers. Operating across 19.00-20.15 GHz and scaling up to radar-optimized frequencies, this PLL is customizable for diverse wireless communication applications. Offering integrated bandgap and LDOs, it ensures stability and precision under varying conditions, with a focus on noise reduction and temperature resilience.
The OT3122t130 is an adaptable Phase-Locked Loop (PLL) created for the TSMC 130nm Low Power and General Purpose CMOS processes. This PLL serves as a clock multiplier, capable of handling a wide scope of input and output frequencies, proving vital for precision timing systems. Leveraging a multi-stage balanced VCO, it minimizes cycle-to-cycle jitter, essential for high-performance applications. Enhanced configuration flexibility is provided through its wide range of integer dividers (N, M, P) and an output frequency ranging between 40MHz to 600MHz. It demonstrates outstanding jitter performance at 18pS RMS when operating at 400MHz. Additional features include lock-detect functionality, startup control for predictable operation, and bypass capabilities to fine-tune system deployment. The OT3122t130 is engineered for efficiency, with a small cell area of 0.022mm² and a power consumption of typically 2mW. The design incorporates 1.8V digital and analog supplies while maintaining compatibility throughout TSMC's 0.13µ process.
PLL12G is a sophisticated Clock Multiplier Unit (CMU) supporting multiple clocking modes and delivering an 8.5-11.3GHz output clock. Used extensively within OC-192 compliant systems, this IP ensures superior performance across various communication scenarios by offering efficient clock setups like FEC+G.709, FEC-only configurations. This flexibility and power efficiency make it ideal for high-demand telecommunications applications.
The pPLL02F series is a versatile set of all-digital fractional-N PLLs designed for a wide range of clocking applications. These PLLs are optimized for low jitter and compact form factor, making them ideal for moderate-speed microprocessor and other digital systems. With output frequencies reaching up to 2GHz, they are capable of serving as clock generators for various logic applications. Built on Perceptia's second-generation digital PLL technology, the pPLL02F family assures consistent performance across multiple fabrication processes. Its architecture accommodates fractional and integer multiplication, enhancing flexibility in selecting input and output clock frequencies. The compact design allows seamless integration into systems with numerous clock domains, supported by an onboard power supply regulator that permits shared power lines. Engineered for straightforward integration, the pPLL02F supports multi-PLL configurations, each instance maintaining a minimal size under 0.01 sq mm and consuming less than 3.5mW. This IP block also includes all necessary deliverables, such as a detailed datasheet, integration guide, and verification reports, ensuring no complications during implementation.
The VCO25G is a 25.5GHz Colpitts architecture Voltage Controlled Oscillator (VCO), known for its low noise differential design. This IP employs a cost-effective 0.18um SiGe process by TowerJazz, making it a suitable choice for PLLs and broadband test and measurement equipment. The VCO25G provides a reliable solution for generating stable high-frequency signals, benefiting various RF applications demanding low phase noise and precise frequency control.
Aeonic Generate provides innovative clock generation solutions for modern SoCs, featuring remarkable observability and efficiency. This product family is designed for applications ranging from data centers to automotive digital processing units. With the smallest area footprint for its category, it offers distributed clocking and integrates a droop response system for enhanced digital voltage and frequency scaling (DVFS). The family's design is based on synthesizable digital architecture, making it easily adaptable across various process nodes, and supports advanced telemetry for clock health monitoring and silicon lifecycle management.
The DIV50G1 is a versatile programmable prescaler supporting division ratios of 1, 2, 4, 8, and 16, handling frequencies up to 50GHz. Testing ensures verification of maximum frequency and power performance. This IP, using TowerJazz's 0.18um SiGe SBC18HX process, supports both single-ended and differential inputs with differential outputs, making it ideal for applications such as PLLs and equipment requiring broadband measurement capabilities.
The DIV60G is a differential frequency divider capable of handling frequencies up to 60GHz. It comes equipped with an active balun for input and provides I/Q differential outputs. This IP is tested on a bare die to ascertain the maximum dividing frequency capability, making it particularly suitable for high-frequency applications such as PLLs and broadband test equipment. Utilizing TowerJazz's 0.18um SiGe SBC18HX process, this IP offers a wide frequency range from DC to 60GHz with both single-ended and differential input options, making it ideal for high-frequency prescaler functions.
Movellus's Aeonic Power product family aims to transform power delivery mechanisms with its capable on-die voltage regulation solutions. Designed to meet the intricate power needs of today's complex chips, the architecture supports wide-range configurability, aiding in significant energy and bill-of-materials (BOM) optimization. Its design enables sophisticated telemetry and observability into power behaviors, offering key insights that influence power distribution and droop mitigation strategies across chips and chiplets. Aeonic Power is foundational for building future-ready SoCs with a focus on energy conservation and process portability.
The Digital-PLL from M31 is designed to deliver high-performance frequency synthesis for diverse semiconductor applications. Featuring a pure core voltage design and a compact size, the PLL supports a range of operational modes, including Fractional-N PLL and Spread Spectrum Clocking (SSC). It offers outstanding power noise immunity and meticulous integration for seamless embedding in ASICs and SoCs. The PLL is particularly adept for environments like noisy ASICs, ensuring high reliability with power-efficient operations. This digital PLL supports various crystal oscillator frequencies, underscoring its adaptability and effectiveness for high-precision electronic systems.
The pPLL05 Family encompasses a series of low power, all digital fractional-N PLLs suited for IoT and embedded systems with power constraints. These PLLs are crafted to function under low voltage conditions without compromising on jitter performance or integration ease. Built on advanced digital PLL technology, the pPLL05 series promises identical performance across various processes regardless of PVT variations. It supports clock frequencies up to 1GHz, making it appropriate as a reliable clock source for moderate-speed microprocessor blocks. The power consumption is remarkably low, less than 1.0mW, complementing its ultra-compact design that occupies less than 0.01 sq mm. This product series is designed to integrate seamlessly into any SoC layout, with deliverables covering datasheets, characterization reports, and thorough guides for both design integration and testing. The pPLL05 can serve either as an integer-N or fractional-N, providing the flexibility needed in choosing the best input-output frequency combinations for specific applications. Perceptia supports these PLLs with extensive customization and support services, ensuring they meet diverse client requirements.