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Brainchip's Akida Neural Processor IP represents a groundbreaking approach to edge AI processing by employing a neuromorphic design that mimics natural brain function for efficient and accurate data processing directly on the device. This IP stands out due to its event-based processing capability, which significantly reduces power consumption while providing high-speed inferencing and on-the-fly learning. Akida's architecture is designed to operate independently of traditional cloud services, thereby enhancing data privacy and security. This localized processing approach enables real-time systems to act on immediate sensor inputs, offering instantaneous reactions. Additionally, the architecture supports flexible neural network configurations, allowing it to adapt to various tasks by tailoring the processing nodes to specific application needs. The Akida Neural Processor IP is supported by Brainchip's MetaTF software, which simplifies the creation and deployment of AI models by providing tools for model conversion and optimization. Moreover, the platform's inherent scalability and customization features make it versatile for numerous industry applications, including smart home devices, automotive systems, and more.
The 2nd Generation Akida platform is a substantial advancement in Brainchip's neuromorphic processing technology, expanding its efficiency and applicability across more complex neural network models. This advanced platform introduces support for Temporal Event-Based Neural Nets and Vision Transformers, aiming to enhance AI performance for various spatio-temporal and sensory applications. It's designed to drastically cut model size and required computations while boosting accuracy. Akida 2nd Generation continues to enable Edge AI solutions by integrating features that improve energy efficiency and processing speed while keeping model storage requirements low. This makes it an ideal choice for applications that demand high-performance AI in Edge devices without needing cloud connectivity. Additionally, it incorporates on-chip learning, which eliminates the need to send sensitive data to the cloud, thus enhancing security and privacy. The platform is highly flexible and scalable, accommodating a wide array of sensory data types and applications, from real-time robotics to healthcare monitoring. It's specifically crafted to run independently of the host CPU, enabling efficient processing in compact hardware setups. With this generation, Brainchip sets a new standard for intelligent, power-efficient solutions at the edge.
Overview: CMOS Image Sensors (CIS) often suffer from base noise, such as Additive White Gaussian Noise (AWGN), which deteriorates image quality in low-light environments. Traditional noise reduction methods include mask filters for still images and temporal noise data accumulation for video streams. However, these methods can lead to ghosting artifacts in sequential images due to inconsistent signal processing. To address this, this IP offers advanced noise reduction techniques and features a specific Anti-ghost Block to minimize ghosting effects. Specifications:  Maximum Resolution o Image : 13MP o Video : 13MP@30fps  -Input formats : YUV422–8 bits  -Output formats o DVP : YUV422-8 bits o AXI : YUV420, YUV422  -8 bits-Interface o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) Features:  Base Noise Correction: AWGN reduction for improved image quality  Mask Filter: Convolution-based noise reduction for still images  Temporal Noise Data Accumulation: Gaussian Distribution-based noise reduction for video streams using 2 frames of images  3D Noise Reduction (3DNR): Sequential image noise reduction with Anti-ghost Block  Motion Estimation and Adaptive: Suppresses ghosting artifacts during noise reduction  Real-Time Processing: Supports Digital Video Port (DVP) and AXI interfaces for seamless integration  Anti-Ghost  Real time De-noising output
0.75V ESD power protection. The ESD clamp is designed to provide protection for 0.75 V Analog and Core domain using 0.75V FinFet transistors in TSMC N3E process. The target ESD robustness can be selected.
Overview: Lens distortion is a common issue in cameras, especially with wide-angle or fisheye lenses, causing straight lines to appear curved. Radial distortion, where the image is expanded or reduced radially from the center, is the most prominent type. Failure to correct distortion can lead to issues in digital image analysis. The solution involves mathematically modeling and correcting distortion by estimating parameters that determine the degree of distortion and applying inverse transformations. Automotive systems often require additional image processing features, such as de-warping, for front/rear view cameras. The Lens Distortion Correction H/W IP comprises 3 blocks for coordinate generation, data caching, and interpolation, providing de-warping capabilities for accurate image correction. Specifications:  Maximum Resolution: o Image: 8MP (3840x2160) o Video: 8MP @ 60fps  Input Formats: YUV422 - 8 bits  Output Formats: o AXI: YUV420, YUV422, RGB888 - 8 bits  Interface: o ARM® AMBA APB BUS interface for system control o ARM® AMBA AXI interface for data Features:  Programmable Window Size and Position  Barrel Distortion Correction Support  Wide Angle Correction up to 192°  De-warping Modes: o Zoom o Tilt o Pan o Rotate o Side-view  Programmable Parameters: o Zoom Factor: controls Distance from the Image Plane to the Camera (Sensor)
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features:  True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications.  Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data.  Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection.  Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification.  RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: RCCC and RCCB in ISP refer to Red and Blue Color Correction Coefficients, respectively. These coefficients are utilized in Image Signal Processing to enhance red and blue color components for accurate color reproduction and balance. They are essential for color correction and calibration to ensure optimal image quality and color accuracy in photography, video recording, and visual displays. The IP is designed to process RCCC pattern data from sensors, where green and blue pixels are substituted by Clear pixel, resulting in Red or Clear (Monochrome) format after demosaicing. It supports real-time processing with Digital Video Port (DVP) format similar to CIS output. RCCB sensors use Clear pixels instead of Green pixels, enhancing sensitivity and image quality in low-light conditions compared to traditional RGB Bayer sensors. LOTUS converts input from RCCB sensors to a pattern resembling RGB Bayer sensors, providing DVP format interface for real-time processing. Features:  Maximum Resolution: 8MP (3840h x 2160v)  Maximum Input Frame Rate: 30fps  Low Power Consumption  RCCC/RCCB Pattern demosaicing
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
The agileADC analog-to-digital converter is a traditional Charge-Redistribution SAR ADC that is referenced to VDD, VSS. The architecture can achieve up to 12-bit resolution at sample rates up to 64 MSPS. It includes a 16-channel input multiplexor that can be configured to be buffered or unbuffered, and support differential or single-ended inputs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Advanced Peripheral Bus (APB) is one of the Advanced Microcontroller Bus Architecture (AMBA) family protocols. It is a low-cost interface that is designed for low power consumption and interface simplicity. Unlike AHB, it is a non-pipelined protocol for connecting low-bandwidth peripherals. Mostly used to link external peripherals to the SOC. Every APB transfer requires at least two clock cycles (SETUP Cycle and ACCESS Cycle) to finish. The APB interface is designed for accessing the programmable control registers of peripheral devices. The APB protocol has two independent data buses, one for read data and one for write data. The buses can be 8, 16, or 32 bits wide. The read and write data buses must have the same width. Data transfers cannot occur concurrently because the read data and write data buses do not have their own individual handshake signals.
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARM® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications:  Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps  Input Formats: Bayer-8, 10, 12, 14 bits  Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits  Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features:  Defective Pixel Correction: On-The-Fly Defective Pixel Correction  14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment  Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5%  2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction  High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm  Color Correction Matrix: 3x3 Matrix  Bayer Gamma Correction: 19 points  RGB Gamma Correction: 19 points  Color Enhancement: Hue/Sat/∆-L Control for R/G/B/C/M/Y Channels  High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction  High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control  Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting  Auto White Balance: Based on R/G/B Feed-Forward Method  Auto Focus: 2-Type 6-Region AF Value Return
Overview: Human eyes have a wider dynamic range than CMOS image sensors (CIS), leading to differences in how objects are perceived in images or videos. To address this, CIS and IP algorithms have been developed to express a higher range of brightness. High Dynamic Range (HDR) based on Single Exposure has limitations in recreating the Saturation Region, prompting the development of Wide Dynamic Range (WDR) using Multi Exposure images. The IP supports PWL companding mode or Linear mode to perform WDR. It analyzes the full-image histogram for global tone mapping and maximizes visible contrast in local areas for enhanced dynamic range. Specifications:  Maximum Resolution: o Image: 13MP o Video: 13MP @ 60fps (Input/Output)  Input Formats (Bayer): o HDR Linear Mode: Max raw 28 bits o Companding Mode: Max PWL compressed raw 24 bits  Output Formats (Bayer): 14 bits  Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Video data stream interface Features:  Global Tone Mapping based on histogram analysis o Adaptive global tone mapping per Input Images  Local Tone Mapping for adaptive contrast enhancement  Real-Time WDR Output  Low Power Consumption and Small Gate Count  28-bit Sensor Data Interface
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The agilePMU Subsystem is an efficient and highly integrated power management unit for SoCs/ASICs. Featuring a power-on-reset, multiple low drop-out regulators, and an associated reference generator. The agilePMU Subsystem is designed to ensure low power consumption while providing optimal power management capabilities. Equipped with an integrated digital controller, the agilePMU Subsystem offers precise control over start-up and shutdown, supports supply sequencing, and allows for individual programmable output voltage for each LDO. Status monitors provide real-time feedback on the current state of the subsystem, ensuring optimal system performance. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Overview: The DDR5 RCD Controller is a registering clock driver utilized in DDR5 RDIMMs and LRDIMMs. It buffers the Command/Address (CA) bus, chip selects, and clock signals between the host controller and DRAMs. Additionally, it establishes a BCOM bus to control data buffers in LRDIMMs. Key Features:  Compliance with JEDEC's JESD82-511  Maximum SCL Operating speed of 12.5MHz in I3C mode  DDR5 server speeds up to 4800MT/s  Dual-channel configuration with 32-bit data width per channel  Support for power-saving mechanisms  Rank 0 & rank 1 DIMM configurations  Loopback and pass-through modes  BCOM sideband bus for LRDIMM data buffer control  In-band Interrupt support  Packet Error Check (PEC)  CCC Packet Error Handling  Error log register  Parity Error Handling  Interrupt Arbitration  I2C Fast-mode Plus (FM+) and I3C Basic compatibility  Switch between I2C mode and I3C Basic  Clearing of Status Registers  Compliance with JESD82-511 specification  I3C Basic Common Command Codes (CCC) Applications:  RDIMM  LRDIMM  AI (Artificial Intelligence)  HPC (High-Performance Computing)  Data-intensive applications
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features:  Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0  Support for Single master and multiple slaves per interface port  Single Data Rate (SDR) and Double Data Rate (DDR) support  Source synchronous clocking  Deep Power Down (DPD) enter and exit commands  Eight IO ports in standard, expandable based on system requirements  Optional Data Strobe (DS) for write masking  bit wide SDR transfer support  Profile 1.0 Commands for non-volatile memory device management  Profile 2.0 Commands for read or write data for various slave devices Applications:  Consumer Electronics  Defense & Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics  Automotive Devices  Sensor Devices
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features:  Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security.  Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes.  SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance.  RTL Delivery: Delivered as RTL for ease of integration into SoC designs.  Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to:  Wearables  Smart/Connected Devices  Metrology  Entertainment Applications  Networking Equipment  Consumer Appliances  Automotive  Industrial Control Systems  Security Systems  Any SoC application that requires executing authenticated firmware in a simple but secure manner.
AMBA AHB is a bus interface designed for high-performance synthesizable applications. It specifies the interface between components such as initiator , interconnects, and targets. AMBA AHB incorporates the features needed for high-performance, high clock frequency systems. The most common AHB targets are internal memory devices, external memory interfaces, and high-bandwidth peripherals.
The Advanced eXtensible Interface(AXI) bus is a high-performance parallel bus that connects on-chip peripheral circuits (or IP blocks) to processor cores. The AXI bus employs "channels" to divide read and write transactions into semi-independent activities that can run at their own pace. The Read Address and Read Data channels send data from the target to the initiator, whereas the Write Address, Write Data, and Write Response channels transfer data from the initiator to the target.
The SPD5 Hub Function IP has been developed to interface I3C/I2C Host Bus and it allows an isolation of local devices like Temperature Sensor(TS), from master host bus. This SPD5 has Two wire serial interface like SCL, SDA
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features:  Supports UCIe 1.0 Specification  Supports CXL 2.0 and CXL 3.0 Specifications  Supports PCIe Gen6 Specification  Supports PCIe Gen5 and older versions of PCIe specifications  Supports single and two-stack modules  Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers  Supports CXL 3.0 256Byte flit mode  Supports PCIe Gen6 flit mode  Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules  Supports sideband and Mainband signals  Supports Lane repair handling  Data to clock point training and eye width sweep support from transmitter and receiver ends  UCIe controller can work as Downstream or Upstream  Main Band Lane reversal supported  Dynamic sense of normal and redundant clock and data lines activation  UCIe enumeration through DVSEC  Error logging and reporting supported  Error injection supported through Register programming  RDI/FDI PM entry, Exit, Abort flows supported  Dynamic clock gang at adapter supported Configurable Options:  Maximum link width (x1, x2, x4, x8, x16)  MPS (128B to 4KB)  MRRS (128B to 4KB)  Transmit retry/Receive buffer size  Number of Virtual Channels  L1 PM substate support  Optional Capability Features can be Configured  Number of PF/VFDMA configurable Options  AXI MAX payload size Variations  Multiple CPI Interfaces (Configurable)  Cache/memory configurable  Type 0/1/2 device configurable
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features:  CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X  PCIe Compatibility: Supports PCIe spec 6.0/5.0  CPI Interface: Support for CPI Interface  AXI Interface: Configurable AXI master, AXI slave  Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16  Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode  Register Checks: Configuration and Memory Mapped registers  Dual Mode: Supports Dual Mode operation  Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers  CXL Support: Can function as both CXL host and device  Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers  FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass  Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized)  Power Management: Supports Power Management features  Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD  Testing: Compliance Testing and Error Scenarios support
The bus converter module transforms wide initiator data buses to smaller target data buses or vice-versa. A narrow target on a wide bus, only requires external logic and no internal design changes. * APB: 32-bit wide initiator data buses to 16-bit target data buses. * AHB: 64-bit wide initiator data buses to 32-bit target data buses. * AXI: 256-bit wide initiator data buses to 64-bit target data buses A wide target on a narrow bus, only requires external logic and no internal design changes. * APB: 16-bit wide initiator data buses to 32-bit target data buses. * AHB: 32-bit wide initiator data buses to 64-bit target data buses. * AXI: 64-bit wide initiator data buses to 256-bit target data buses.
Overview: RGB-IR features in ISP enable the capture and processing of Red, Green, Blue, and Infrared (IR) light data in an Image Signal Processing (ISP) system. This functionality enhances image quality by extracting additional information not visible to the human eye in standard RGB images. By integrating IR and RGB data into the demosaic processing pipeline, the ISP can enhance scene analysis, object detection, and image clarity in applications such as surveillance, automotive, and security systems. Features:  IR Core - 4Kx1EA:  4K Maximum Resolution: 3840h x 2160v @ 30fps  IR Color Correction 3.99x support  IR data Full-size output / 1/4x subsample support (Pure IR Pixel data)  Only RGB-IR 4x4 pattern support  IR data Crop support
The Wishbone System-on-Chip (SoC) Interconnection Architecture for Portable IP Cores is a versatile design approach for semiconductor IP cores. Its goal is to promote design reuse by addressing system-on-chip integration issues. This is accomplished by providing a standard interface for IP cores. This increases the system's mobility and stability, resulting in a shorter time-to-market for end users.
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-CSI-2 version 3.0  Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0  Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0  Compatibility with I2C and I3C (SDR, DDR) for CCI interface  Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer  Processor Interfaces: AHB Lite/APB/AXI for configuration  Lane Merging Function for consolidating packet data in CSI-2 Receiver  De-skew detection in D-PHY and sync word detection in C-PHY  Pixel Formats Supported: YUV, RGB, and RAW data  Virtual Channels: 16 for D-PHY, 32 for C-PHY  Error detection, interleaving, scrambling, and descrambling support  Byte to pixel conversion in LLP layer Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features:  Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements.  BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment.  Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to:  Secured and Certified iSIM & iUICC  EMVco Payment  Hardware Cryptocurrency Wallets  FIDO2 Web Authentication  V2X HSM Protocols  Smart Car Access  Secured Boot  Secure OTA Firmware Updates  Secure Debug  Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
The agileDSCL is a compact digital standard cell library customizable for specific foundries and processes, and optimized for low-power, ultra-low-leakage, high-density or high-speed applications. It provides a selection of standard cells with functionalities essential to implement digital designs, with additional power management library to support the implementation of low-power designs. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
Avalon interfaces make system design easier by allowing you to connect components in Intel FPGAs. The Avalon interface family defines interfaces that can stream high-speed data, read and write registers and memory, and operate off-chip devices. Platform Designer components incorporate these standard interfaces. Furthermore, you can include Avalon APIs in custom components, increasing the interoperability of designs.
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features:  Compliance with MIPI-I3C Basic v1.0  Backward compatibility with I2C  Two-wire serial interface up to 12.5MHz using Push-Pull  Dynamic and Static Addressing support  Single Data Rate messaging (SDR)  Broadcast and Direct Common Command Code (CCC) Messages support  In-Band Interrupt capability  Hot-Join Support Applications:  Consumer Electronics  Defense  Aerospace  Virtual Reality  Augmented Reality  Medical  Biometrics (Fingerprints, etc.)  Automotive Devices  Sensor Devices
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features:  Compliance with JEDEC's JESD300-5  Support for speeds up to 12.5MHz  Bus Reset functionality  SDA arbitration support  Enabled Parity Check  Support for Packet Error Check (PEC)  Switch between I2C and I3C Basic Mode  Default Read address pointer Mode  Write and read operations for SPD5 Hub with or without PEC  In-band Interrupt (IBI) support  Write Protection for NVM memory blocks  Arbitration for Interrupts  Clearing of Device Status and IBI Status Registers  Error handling for Packet Error Check and Parity Errors  Common Command Codes (CCC) for I3C Basic Mode  Dynamic IO Operation Mode Switching  Bus Clear and Bus Reset capabilities  SPD5 Command features for NVM memory and Register Space  Read and Write access to NVM memory  Support for Offline Tester operation Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
Silicon Creations' Free Running Oscillators offer an efficient solution for timing applications that require reliability without the need for an external timing reference. These oscillators are available in various configurations to meet the diverse needs of modern electronic devices. Designed for low power consumption, these oscillators excel in applications like watchdog timers and core clock generators for microcontrollers (MCUs). They are engineered to maintain precise timing, even under challenging conditions, ensuring device stability across a wide range of temperatures and voltage fluctuations. With a focus on integration efficiency, these oscillators are optimized for baseline CMOS logic processes, requiring no additional external components. This makes them exceptionally compact yet precise, suitable for a broad spectrum of applications in consumer electronics and low-power chips, providing a consistent and dependable clock source.
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications:  Supports PCIe Gen 6 and Pipe 5.X Specifications  Core supports Flit and non-Flit Mode  Lane Configurations: X16, X8, X4, X2, X1  AXI MM and Streaming supported  Supports Gen1 to Gen6 modes  Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s  PAM support when operating at 64GT/s  Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b  Supports SerDes and non-SerDes architecture  Optional DMA support as plugin module  Support for alternate negotiation protocol  Can operate as an endpoint or root complex  Lane polarity control through register  Lane de-skew supported  Support for L1 states and L0P  Support for SKP OS add/removal and SRIS mode  No equalization support through configuration  Deemphasis negotiation support at 5GT/s  Supports EI inferences in all modes  Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
The NMP-750 is engineered as a performance accelerator tailored for edge computing applications that demand robust processing power and versatility. It is ideally deployed in environments such as automotive, AMR and UAV systems, AR/VR applications, as well as smart infrastructure projects like smart buildings, factories, and cities. Its design principles aim to enhance security and surveillance systems while supporting advanced telecommunications solutions. This comprehensive IP can attain up to 16 TOPS, thereby addressing needs for high throughput and efficiency in data processing tasks. The NMP-750 includes up to 16 MB of local memory, utilizing either RISC-V or Arm Cortex-R or A 32-bit CPUs to manage operational complexity through three 128-bit AXI4 interfaces for host, CPU, and data processes. This infrastructure not only ensures rapid data-handling capabilities but also optimizes system-level operations for various emerging technologies. Ideal for managing multi-camera stream processing and enhancing spectral efficiency, it is equally suited for mobility and autonomous control systems—key to future smart city and factory applications. The NMP-750's support for comprehensive automation and data analytics offers companies the potential to develop cutting-edge technologies, driving industry standards across domains.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features:  Compliance with MIPI-DSI-2 version 2.0  Compliance with C-PHY version 2.0 for DSI-2 Version-2  Compliance with D-PHY version 1.2 for DSI-2 Version-2.0  Compliance with D-PHY version 2.0 for DSI-2 Version-2.0  Compliance with D-PHY version 3.0 for DSI-2 Version-2.0  Compliance with MIPI SDF specification  Compliance with DBI-2 and DPI-2  Pixel to Byte conversion support from Application layer to LLP layer  Support for Command Mode and Video Mode  Continuous clock behavior in clock lane for D-PHY physical layer  De-skew sequence pattern for video mode support  Lane Distribution Function for distributing packet bytes across N-Lanes  Connectivity with two, three, or four DSI Receivers  HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY  Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications:  Imaging  Surveillance  Gaming  Sensor devices  Internet of Things (IoT)  Wearable devices  Virtual Reality  Augmented Reality  Automotive Systems
KPIT Technologies is a forerunner in developing AUTOSAR-compliant platforms that support the evolution of software-defined vehicles. Their solutions facilitate efficient software integration, middleware development, and high-level application performance optimization. By using advanced tools and methodologies, KPIT helps speed up the production timelines of modern vehicles, ensuring compliance with both AUTOSAR Classic and Adaptive frameworks. Their technologies enable automakers to minimize platform validation times and reduce integration complexities, thereby enhancing the scalability and functionality of vehicle systems.
CoreVCO is a high-performance, radiation-hardened VCO solution offering excellent phase noise characteristics. Engineered for demanding environments such as space and military applications, CoreVCO includes dual VCOs with wide frequency coverage ranging from 0.7 to 6.6 GHz. Its robust design ensures stability and reliability in high-radiation settings. CoreVCO's architecture integrates unique SiGe technology, providing superb intrinsic noise resistance and wide frequency fidelity. The solution is characterized by an integrated bandgap reference, LDOs, and a smart output power adjustment feature, enhancing its usability in various applications. This VCO solution supports digital calibration to counter process and temperature variations, demonstrating adaptive performance across a range of temperature and voltage conditions. CoreVCO is packaged compactly, making it a valuable component in compact designs needing efficient frequency synthesis.
The agileDAC is a digital-to-analog converter that uses a traditional capacitive DAC architecture. The agileDAC uses its own internal reference voltage. The architecture can achieve up to 10-bit resolution at sample rates up to 16 MSPS. Agile Analog designs are based on tried and tested architectures to ensure reliability and functionality. Our automated design methodology is programmatic, systematic and repeatable leading to analog IP that is more verifiable, more robust and more reliable. Our methodology also allows us to quickly re-target our IP to different process options. Our highly configurable and multi-node analog IP products are developed to meet the customer’s exact requirements. These digitally-wrapped and verified solutions can be seamlessly integrated into any SoC, significantly reducing complexity, time and costs.
An interconnect component connects multi initiators and multi targets in a system. A single initiator system simply requires a decoder and multiplexor.
eSi-Connect is a sophisticated networking solution designed to enhance the communication efficiency between eSi-RISC cores and their peripherals. Utilizing the AMBA protocol, it provides seamless interconnections across processors, memory controllers, and various peripheral devices. This results in a streamlined design process and reduced complexity during system integration. Leveraging industry-standard architectures, eSi-Connect ensures that a wide range of third-party IP cores can be integrated smoothly, providing flexibility and choice in design customization. Its design optimally supports the scalability and compatibility requirements of complex embedded systems. eSi-Connect's robust framework is crafted to support a myriad of applications, from simple control systems to multiprocessor platforms requiring advanced data throughput and low latency. This adaptability makes it a pivotal component in the design of modern embedded systems, facilitating enhanced system performance and efficiency.
TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. TileLink is intended for use in a System On-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complicated devices, utilising a fast, scalable interconnect that provides both low latency and high-throughput transfers.
Operating at 24GHz, the VCO24G is a Colpitts-type Voltage-Controlled Oscillator developed to bring precision and low-noise performance to RF and broadband applications. Constructed with the TowerJazz 0.18um SiGe process, this VCO emphasizes cost-efficiency without sacrificing quality. Its differential design architecture reduces phase noise, thus enhancing the signal clarity essential for PLLs and broadband test and measurement systems. The frequency range offers the adaptability needed for varied applications, ensuring the VCO24G's capability in handling different RF requirements effectively. With its cost-effective process and high-performance specs, the VCO24G stands as a reliable option for OEMs seeking solid RF solutions. Its deployment spans scenarios that require exact frequency control and operational stability in challenging environments.
Silicon Creations' LVDS Interfaces provide a low-power, high-speed data communication solution ideal for connecting integrated circuits in close proximity. Known for their low noise and power efficiency, these interfaces are widely used in applications ranging from display technology to telecommunications. These robust LVDS solutions support high data rates and are highly adaptable to various process nodes from 90nm to more advanced 7nm FinFET, making them suitable for both legacy and cutting-edge technologies. They ensure data integrity and signal stability across different conditions and configurations, leveraging enhanced CDR architectures. With extensive configurations supporting uni-directional and bi-directional operation, the LVDS interfaces provide flexibility for custom communications setups and are compliant with multiple standards like Camera Link and FPD-Link. Their capability to manage high-speed data links with precision positions them as essential components in demanding electronic applications.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features:  Maximum Operating speed of 12.5MHz  Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support  Multi-Time Programmable Non-Volatile Memory Interface  Programmable and DIMM-specific registers for customization  Error log registers for tracking  Packet Error Check (PEC) and Parity Error Check functions  Bus Reset function  Support I3C Basic mode  In-Band Interrupt (IBI) support  Write, read, and default read operations in I2C mode  Error handling for PEC, Parity errors, and CCC errors  I3C Basic Common Command Codes (CCC) support Applications:  DDR5 DIMM Application Environment  DDR5 NVDIMM Application Environment  Automotive Devices  Memory Devices  Power Management Devices  Defense/Aerospace/Customer Electronics
The SerDes Interfaces from Silicon Creations feature cutting-edge capabilities for high-speed serial data transmission in semiconductor devices. Supporting a vast range of industry protocols, these interfaces offer both flexibility and performance, making them ideal for varied high-bandwidth applications. These interfaces accommodate rates from as low as 100Mbps to an impressive 32.75Gbps, covering a wide spectrum of technologies from JESD204 to PCIe and V-by-One. They include programmable serialization and deserialization features, along with advanced techniques for reducing latency, ensuring the rapid delivery and reception of data streams. Built on proven IP platforms, the SerDes interfaces integrate advanced PLLs to manage jitter and power consumption effectively. With adaptability to a multitude of fabrication nodes, these solutions meet the diverse needs of networked devices and high-speed interconnects, showcasing Silicon Creations’ expertise in providing industry-leading communication solutions.
SkyeChip's Coherent Network-on-Chip (NOC) is an innovative, scalable solution designed to support memory coherent systems. Engineered to decrease routing congestion in many-core systems, it effectively utilizes nodes like ACE4, ACE5, and CHI protocols. Operating efficiently at frequencies up to 2GHz, it complements SkyeChip’s Non-Coherent NOC for integrated and partitioned interconnect systems. The solution’s focus on reducing silicon usage makes it a prime candidate for applications where performance and area efficiency are paramount, ensuring seamless system integration with high coherency requirements.
KPIT's Connected Vehicle Solutions leverage modern cloud and edge computing to enhance the connectivity features of today’s vehicles. This technology supports secure data management, advanced analytics, and comprehensive solutions for real-time vehicle connectivity. The platform is engineered to provide enriched data-driven insights, enabling OEMs to better handle vehicle data, improve cybersecurity measures, and ensure compliance with emerging regulatory standards. By transforming data into strategic advantages, KPIT aids automotive manufacturers in delivering enhanced user experiences and operational efficiencies.