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The Akida neural processor IP is a groundbreaking solution, touted as BrainChip's first-to-market digital neuromorphic processor. It emulates the human brain, processing only essential sensor inputs at the point of acquisition. This technology remarkably reduces latency, boosts precision, and significantly lowers power consumption compared to traditional methods. One of the IP's most compelling features is its ability to keep AI/ML tasks local, eliminating the need for cloud dependency while enhancing data security and privacy. Designed for both inference and on-chip learning at the edge, Akida offers a fully customizable event-based AI neural processor. Its scalable architecture supports up to 256 nodes connected via a mesh network, and each node comprises four Neural Network Layer Engines with configurable SRAM. This allows the processor to adjust dynamically for either convolutional or fully connected operations. Moreover, the processor is event-driven, meaning it utilizes data sparsity in activations and weights, drastically cutting down operations. This nature allows for efficient processing across various applications without the energy demands of a typical neural network accelerator, making it an optimal choice for high-speed, low-power computing needs.
BrainChip's Akida 2nd Generation is an enhanced version of their pioneering neuromorphic technology, designed to support a wider range of complex network models through advanced event-based processing. This iteration adds significant features such as 8-bit support for weights and activations, improving both energy efficiency and computational accuracy. The 2nd Generation builds upon the foundational Akida technology by expanding its capabilities for more sophisticated applications without increasing the need for cloud reliance. It is set to bring remarkable improvements in the deployment of intelligent applications across a variety of edge devices, supporting crucial functionalities like vision transformers and temporal event-based neural networks (TENNs). This platform is versatile and scalable, enabling processing across 1 to 128 nodes. Its design prioritizes privacy and security by ensuring that sensitive data remains on-device. Its unique advantage lies in reducing model storage requirements and offers increased operational efficiency, catering to the diverse needs of industries like automotive, healthcare, and industrial IoT.
Overview: CMOS Image Sensors (CIS) often suffer from base noise, such as Additive White Gaussian Noise (AWGN), which deteriorates image quality in low-light environments. Traditional noise reduction methods include mask filters for still images and temporal noise data accumulation for video streams. However, these methods can lead to ghosting artifacts in sequential images due to inconsistent signal processing. To address this, this IP offers advanced noise reduction techniques and features a specific Anti-ghost Block to minimize ghosting effects. Specifications: Maximum Resolution o Image : 13MP o Video : 13MP@30fps -Input formats : YUV422–8 bits -Output formats o DVP : YUV422-8 bits o AXI : YUV420, YUV422 -8 bits-Interface o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) Features: Base Noise Correction: AWGN reduction for improved image quality Mask Filter: Convolution-based noise reduction for still images Temporal Noise Data Accumulation: Gaussian Distribution-based noise reduction for video streams using 2 frames of images 3D Noise Reduction (3DNR): Sequential image noise reduction with Anti-ghost Block Motion Estimation and Adaptive: Suppresses ghosting artifacts during noise reduction Real-Time Processing: Supports Digital Video Port (DVP) and AXI interfaces for seamless integration Anti-Ghost Real time De-noising output
0.75V ESD power protection. The ESD clamp is designed to provide protection for 0.75 V Analog and Core domain using 0.75V FinFet transistors in TSMC N3E process. The target ESD robustness can be selected.
Overview: Lens distortion is a common issue in cameras, especially with wide-angle or fisheye lenses, causing straight lines to appear curved. Radial distortion, where the image is expanded or reduced radially from the center, is the most prominent type. Failure to correct distortion can lead to issues in digital image analysis. The solution involves mathematically modeling and correcting distortion by estimating parameters that determine the degree of distortion and applying inverse transformations. Automotive systems often require additional image processing features, such as de-warping, for front/rear view cameras. The Lens Distortion Correction H/W IP comprises 3 blocks for coordinate generation, data caching, and interpolation, providing de-warping capabilities for accurate image correction. Specifications: Maximum Resolution: o Image: 8MP (3840x2160) o Video: 8MP @ 60fps Input Formats: YUV422 - 8 bits Output Formats: o AXI: YUV420, YUV422, RGB888 - 8 bits Interface: o ARM® AMBA APB BUS interface for system control o ARM® AMBA AXI interface for data Features: Programmable Window Size and Position Barrel Distortion Correction Support Wide Angle Correction up to 192° De-warping Modes: o Zoom o Tilt o Pan o Rotate o Side-view Programmable Parameters: o Zoom Factor: controls Distance from the Image Plane to the Camera (Sensor)
Speedcore embedded FPGA (eFPGA) IP represents a notable advancement in integrating programmable logic into ASICs and SoCs. Unlike standalone FPGAs, eFPGA IP lets designers tailor the exact dimensions of logic, DSP, and memory needed for their applications, making it an ideal choice for areas like AI, ML, 5G wireless, and more. Speedcore eFPGA can significantly reduce system costs, power requirements, and board space while maintaining flexibility by embedding only the necessary features into production. This IP is programmable using the same Achronix Tool Suite employed for standalone FPGAs. The Speedcore design process is supported by comprehensive resources and guidance, ensuring efficient integration into various semiconductor projects.
Overview: RCCC and RCCB in ISP refer to Red and Blue Color Correction Coefficients, respectively. These coefficients are utilized in Image Signal Processing to enhance red and blue color components for accurate color reproduction and balance. They are essential for color correction and calibration to ensure optimal image quality and color accuracy in photography, video recording, and visual displays. The IP is designed to process RCCC pattern data from sensors, where green and blue pixels are substituted by Clear pixel, resulting in Red or Clear (Monochrome) format after demosaicing. It supports real-time processing with Digital Video Port (DVP) format similar to CIS output. RCCB sensors use Clear pixels instead of Green pixels, enhancing sensitivity and image quality in low-light conditions compared to traditional RGB Bayer sensors. LOTUS converts input from RCCB sensors to a pattern resembling RGB Bayer sensors, providing DVP format interface for real-time processing. Features: Maximum Resolution: 8MP (3840h x 2160v) Maximum Input Frame Rate: 30fps Low Power Consumption RCCC/RCCB Pattern demosaicing
Overview: Human eyes have a wider dynamic range than CMOS image sensors (CIS), leading to differences in how objects are perceived in images or videos. To address this, CIS and IP algorithms have been developed to express a higher range of brightness. High Dynamic Range (HDR) based on Single Exposure has limitations in recreating the Saturation Region, prompting the development of Wide Dynamic Range (WDR) using Multi Exposure images. The IP supports PWL companding mode or Linear mode to perform WDR. It analyzes the full-image histogram for global tone mapping and maximizes visible contrast in local areas for enhanced dynamic range. Specifications: Maximum Resolution: o Image: 13MP o Video: 13MP @ 60fps (Input/Output) Input Formats (Bayer): o HDR Linear Mode: Max raw 28 bits o Companding Mode: Max PWL compressed raw 24 bits Output Formats (Bayer): 14 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Video data stream interface Features: Global Tone Mapping based on histogram analysis o Adaptive global tone mapping per Input Images Local Tone Mapping for adaptive contrast enhancement Real-Time WDR Output Low Power Consumption and Small Gate Count 28-bit Sensor Data Interface
Overview: The Camera ISP IP is an Image Signal Processing (ISP) IP developed for low-light environments in surveillance and automotive applications, supporting a maximum processing resolution of 13 Mega or 8Mega Pixels (MP) at 60 frames per second (FPS). It offers a configurable ISP pipeline with features such as 18x18 2D/8x6 2D Color Shading Correction, 19-Point Bayer Gamma Correction, Region Color Saturation, Hue, and Delta L Control functions. The ISP IP enhances image quality with optimal low-light Noise/Sharp filters and offers benefits such as low gate size and memory usage through algorithm optimization. The IP is also ARM® AMBA 3 AXI protocol compliant for easy control via an AMBA 3 APB bus interface. Specifications: Maximum Resolution: o Image: 13MP/8MP o Video: 13MP @ 60fps / 8MP @ 60fps Input Formats: Bayer-8, 10, 12, 14 bits Output Formats: o DVP: YUV422, YUV444, RGB888 - 8, 10, 12 bits o AXI: YUV422, YUV444, YUV420, RGB888 - 8, 10, 12 bits Interface: o ARM® AMBA APB BUS interface for ISP system control o ARM® AMBA AXI interface for data o Direct connection to sensor stream data (DVP) o Features: Defective Pixel Correction: On-The-Fly Defective Pixel Correction 14-Bit Bayer Channel Gain Support: Up to x4 / x7.99 with Linear Algebra for Input Pixel Level Adjustment Gb/Gr Unbalance Correction: Maximum Correction Tolerance Gb/Gr Rate of 12.5% 2D Lens-Shading Correction: Supports 18x18 / 8x6 with Normal R/Gb/Gr/B Channel Shading Correction and Color Stain Correction High-Resolution RGB Interpolation: Utilizes ES/Hue-Med/Average/Non-Directional Based Hybrid Type Algorithm Color Correction Matrix: 3x3 Matrix Bayer Gamma Correction: 19 points RGB Gamma Correction: 19 points Color Enhancement: Hue/Sat/∆-L Control for R/G/B/C/M/Y Channels High-Performance Noise Reduction: For Bayer/RGB/YC Domain Noise Reduction High-Resolution Sharpness Control: Multi-Sharp Filter with Individual Sharp Gain Control Auto Exposure: Utilizes 16x16 Luminance Weight Window & Pixel Weighting Auto White Balance: Based on R/G/B Feed-Forward Method Auto Focus: 2-Type 6-Region AF Value Return
MetaTF is a comprehensive development environment for neural networks, perfectly aligned with BrainChip's vision of enhancing Edge AI. It simplifies the creation, training, and testing of neural networks for use on BrainChip’s Akida neural processor by supporting the automatic conversion of TensorFlow models. This tool leverages the Python programming language and popular libraries like NumPy and Jupyter notebooks, allowing developers to work within a familiar ecosystem. A standout feature of MetaTF is its ability to transform Convolutional Neural Networks (CNNs) into Spiking Neural Networks (SNNs), optimizing them for low-latency, energy-efficient applications at the edge without necessitating new framework learning. In addition to the conversion capabilities, MetaTF offers a range of pre-created network models in their model zoo. This rich repository provides a variety of quantized Keras models converted using CNN2SNN, giving developers a head start in building efficient, performant solutions. Its integration with BrainChip's Akida explores true on-device intelligence by allowing developers to innovate without limitations traditionally posed by less efficient networks.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Overview: The DDR5 RCD Controller is a registering clock driver utilized in DDR5 RDIMMs and LRDIMMs. It buffers the Command/Address (CA) bus, chip selects, and clock signals between the host controller and DRAMs. Additionally, it establishes a BCOM bus to control data buffers in LRDIMMs. Key Features: Compliance with JEDEC's JESD82-511 Maximum SCL Operating speed of 12.5MHz in I3C mode DDR5 server speeds up to 4800MT/s Dual-channel configuration with 32-bit data width per channel Support for power-saving mechanisms Rank 0 & rank 1 DIMM configurations Loopback and pass-through modes BCOM sideband bus for LRDIMM data buffer control In-band Interrupt support Packet Error Check (PEC) CCC Packet Error Handling Error log register Parity Error Handling Interrupt Arbitration I2C Fast-mode Plus (FM+) and I3C Basic compatibility Switch between I2C mode and I3C Basic Clearing of Status Registers Compliance with JESD82-511 specification I3C Basic Common Command Codes (CCC) Applications: RDIMM LRDIMM AI (Artificial Intelligence) HPC (High-Performance Computing) Data-intensive applications
Overview: Cybersecurity IPs offer a range of essential security features to protect your digital assets and sensitive information. From True Random Number Generators (TRNG) to advanced encryption algorithms like AES, DES, 3DES, and cryptographic hash functions like SHA, as well as RSA for secure key exchange and digital signatures, the IPs provide a comprehensive suite of tools to safeguard your data. Key Features: True Random Number Generator (TRNG): Generates unpredictable and unbiased random numbers for cryptographic applications. Advanced Encryption Standard (AES): Provides robust encryption with symmetric key algorithms for securing data. Data Encryption Standard (DES) and Triple DES (3DES): Implement legacy encryption algorithms for data protection. Hash Functions: Includes secure cryptographic hash functions like SHA (Secure Hash Algorithm) for data integrity verification. RSA: Enables secure key exchange, encryption, and digital signatures for secure communication. These cybersecurity IPs are designed to meet the stringent security requirements of modern applications, ensuring the confidentiality, integrity, and authenticity of your data.
Overview: RGB-IR features in ISP enable the capture and processing of Red, Green, Blue, and Infrared (IR) light data in an Image Signal Processing (ISP) system. This functionality enhances image quality by extracting additional information not visible to the human eye in standard RGB images. By integrating IR and RGB data into the demosaic processing pipeline, the ISP can enhance scene analysis, object detection, and image clarity in applications such as surveillance, automotive, and security systems. Features: IR Core - 4Kx1EA: 4K Maximum Resolution: 3840h x 2160v @ 30fps IR Color Correction 3.99x support IR data Full-size output / 1/4x subsample support (Pure IR Pixel data) Only RGB-IR 4x4 pattern support IR data Crop support
Overview: The Secure Enclave IPs are Common Criteria (CC) EAL5+PP0084/PP0117 and EAL5+PP0117 certification-ready Secure Enclaves, respectively. They are available as hard macros for seamless integration into SoCs. These Secure Enclave IPs provide the highest level of security for an SoC, incorporating patented design techniques and countermeasures against side-channel and perturbation attacks to ensure robust security while minimizing power consumption. Key Features: Cryptographic Hardware Accelerators: Efficiently support standard cryptography and security operations to increase throughput while adhering to power constraints and security requirements. BootROM and Secondary Boot Loader: Manage the certified life cycle of the Secure Enclave, enforcing and assuring security from manufacturing to deployment. Proprietary IP: Based on proprietary IP that is free of 3rd party rights and royalties. Benefits: The Secure Enclave IPs offer robust security measures, efficient cryptographic support, and secure life cycle management, making them ideal for applications that require the highest levels of security and reliability. Applications: The Secure Enclave IP is versatile and suitable for a wide range of applications, including but not limited to: Secured and Certified iSIM & iUICC EMVco Payment Hardware Cryptocurrency Wallets FIDO2 Web Authentication V2X HSM Protocols Smart Car Access Secured Boot Secure OTA Firmware Updates Secure Debug Any design requiring a Secure Enclave, Secure Element, or Hardware Root of Trust protected against side-channel and perturbation fault attacks. Compliance and Support: The Secure Enclave is compliant with and ready for CC EAL5+ and EMVCo certification. It is delivered with an SDK and pre-certified CryptoLibrary and secure Boot Loader for seamless integration and enhanced security.
Overview: The Secure Boot IP is a turnkey solution that provides a secure boot facility for an SoC. It implements the Post Quantum secure Leighton-Micali Signature (LMS) as specified in NIST SP800-208. The Secure Boot IP operates as a master or slave peripheral to an Application Processor, serving as a secure enclave that securely stores keys to ensure their integrity and the integrity of the firmware authentication process. Features: Post Quantum Secure LMS Signature: Utilizes a robust Post-Quantum secure algorithm for enhanced security. Firmware Updates: Supports up to 32 thousand firmware updates with a minimal signature size of typically less than 5KBytes. SESIP Level 3 Pre-Certification: Pre-certified to SESIP Level 3 for added security assurance. RTL Delivery: Delivered as RTL for ease of integration into SoC designs. Proprietary IP: Based on proprietary IP with no 3rd party rights or royalties. Operation: The Secure Boot IP operates as a master, managing the boot process of the Application Processor to ensure that it only boots from and executes validated and authenticated firmware. The Secure Boot IP also functions as a slave peripheral, where the Application Processor requests validation of the firmware as part of its boot process, eliminating the need for managing keys and simplifying the boot process. Applications: The Secure Boot IP is versatile and suitable for a wide range of applications, including but not limited to: Wearables Smart/Connected Devices Metrology Entertainment Applications Networking Equipment Consumer Appliances Automotive Industrial Control Systems Security Systems Any SoC application that requires executing authenticated firmware in a simple but secure manner.
Overview: The Expanded Serial Peripheral Interface (xSPI) Master/Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy SPI devices. It is designed to connect xSPI Master/Slave devices in computing, automotive, Internet of Things, embedded systems, and mobile processors to various peripherals such as non-volatile memories, graphics peripherals, networking devices, FPGAs, and sensor devices. Key Features: Compliance with JEDEC standard JESD251 eXpanded SPI for Non-Volatile Memory Devices, Version 1.0 Support for Single master and multiple slaves per interface port Single Data Rate (SDR) and Double Data Rate (DDR) support Source synchronous clocking Deep Power Down (DPD) enter and exit commands Eight IO ports in standard, expandable based on system requirements Optional Data Strobe (DS) for write masking bit wide SDR transfer support Profile 1.0 Commands for non-volatile memory device management Profile 2.0 Commands for read or write data for various slave devices Applications: Consumer Electronics Defense & Aerospace Virtual Reality Augmented Reality Medical Biometrics Automotive Devices Sensor Devices
Overview: PCIe Gen6 is a high-speed, layered protocol interconnect interface supporting speeds up to 64GT/s, featuring multi-lanes and links. The Transport, Data Link, and Physical layers specified in the PCIe specification are implemented, along with PIPE interface logic connecting to PHY and AXI Bridging logic for application connectivity. Specifications: Supports PCIe Gen 6 and Pipe 5.X Specifications Core supports Flit and non-Flit Mode Lane Configurations: X16, X8, X4, X2, X1 AXI MM and Streaming supported Supports Gen1 to Gen6 modes Data rate support of 2.5 GT/s, 5 GT/s, 8 GT/s, 16 GT/s, 32 GT/s, 64 GT/s PAM support when operating at 64GT/s Encoding/Decoding Support: 8b/10b, 128b/130b, 1b/1b Supports SerDes and non-SerDes architecture Optional DMA support as plugin module Support for alternate negotiation protocol Can operate as an endpoint or root complex Lane polarity control through register Lane de-skew supported Support for L1 states and L0P Support for SKP OS add/removal and SRIS mode No equalization support through configuration Deemphasis negotiation support at 5GT/s Supports EI inferences in all modes Supports PTM, OBFF, MSI, MSIX, Power management, and all message formats
Overview: The Multi-Protocol Accelerator IP is a versatile technology designed to support low latency and high bandwidth accelerators for efficient CPU-to-device and CPU-to-memory communication. It also enables switching for fan-out to connect more devices, memory pooling for increased memory utilization efficiency, and provides memory capacity with support for hot-plug, security enhancements, persistent memory support, and memory error reporting. Key Features: CXL 3.0 Support: Compliant with CXL spec V3.X/V2.X PCIe Compatibility: Supports PCIe spec 6.0/5.0 CPI Interface: Support for CPI Interface AXI Interface: Configurable AXI master, AXI slave Bus Support: PIPE/FLEX bus, Lane x1,x2,x4,x8,x16 Protocol Support: Gen3, Gen4, Gen5 & Gen6, Fallback Mode Register Checks: Configuration and Memory Mapped registers Dual Mode: Supports Dual Mode operation Transfer Support: HBR/PBR & LOpt Transfers, Standard Cache and Mem Transfers CXL Support: Can function as both CXL host and device Data Transfer: Supports Standard IO, 68Byte Flit, and 256Byte Flit Transfers FlexBus Features: FlexBus Link Features, ARB/MUX, ARB/MUX Bypass Optimization: Latency Optimization, Credit Return Forcing, Empty Flits (Latency Optimized) Power Management: Supports Power Management features Enhancements: CXL IDE, RAS Features, Poison & Viral Handling, MLD/SLD Testing: Compliance Testing and Error Scenarios support
Overview: The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets. Key Features: Supports UCIe 1.0 Specification Supports CXL 2.0 and CXL 3.0 Specifications Supports PCIe Gen6 Specification Supports PCIe Gen5 and older versions of PCIe specifications Supports single and two-stack modules Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers Supports CXL 3.0 256Byte flit mode Supports PCIe Gen6 flit mode Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules Supports sideband and Mainband signals Supports Lane repair handling Data to clock point training and eye width sweep support from transmitter and receiver ends UCIe controller can work as Downstream or Upstream Main Band Lane reversal supported Dynamic sense of normal and redundant clock and data lines activation UCIe enumeration through DVSEC Error logging and reporting supported Error injection supported through Register programming RDI/FDI PM entry, Exit, Abort flows supported Dynamic clock gang at adapter supported Configurable Options: Maximum link width (x1, x2, x4, x8, x16) MPS (128B to 4KB) MRRS (128B to 4KB) Transmit retry/Receive buffer size Number of Virtual Channels L1 PM substate support Optional Capability Features can be Configured Number of PF/VFDMA configurable Options AXI MAX payload size Variations Multiple CPI Interfaces (Configurable) Cache/memory configurable Type 0/1/2 device configurable
Overview: The MIPI CSI-2 (Camera Serial Interface) defines an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Support for C-PHY 2.0, D-PHY 2.5, A-PHY, M-PHY with configurable PHY layer Processor Interfaces: AHB Lite/APB/AXI for configuration Lane Merging Function for consolidating packet data in CSI-2 Receiver De-skew detection in D-PHY and sync word detection in C-PHY Pixel Formats Supported: YUV, RGB, and RAW data Virtual Channels: 16 for D-PHY, 32 for C-PHY Error detection, interleaving, scrambling, and descrambling support Byte to pixel conversion in LLP layer Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
KPIT's contributions to AUTOSAR (Automotive Open System Architecture) are geared towards providing robust and scalable software platform solutions across vehicle electronics systems. Their AUTOSAR offerings span classic and adaptive platforms, which are pivotal in high-performance computing and real-time critical ECUs. Their KSAR Classic platform offers ASIL-D certified solutions that encompass base software stack needed for safety-critical applications, supporting a wide range of automotive applications with integrated configuration and code generation tools. Meanwhile, KSAR Adaptive introduces a service-oriented architecture suitable for high-compute environments, aligning with modern needs for flexibility and high performance. KPIT also extends software integration services that encompass over two decades of experience, providing domain-specific solutions that integrate seamlessly with their AUTOSAR stack. Such offerings are essential for ensuring system reliability, cybersecurity, and regulatory compliance, affirming the company's role as a leader in vehicle software architecture. The partnership with various OEMs and industry consortiums reinforces KPIT's influence and capabilities in establishing standardized software solutions across the automotive industry. Their commitment to sustaining and advancing AUTOSAR technology demonstrates a forward-thinking approach that keeps pace with evolving vehicular demands.
The Speedster7t FPGA family is crafted for high-bandwidth tasks, tackling the usual restrictions seen in conventional FPGAs. Manufactured using the TSMC 7nm FinFET process, these FPGAs are equipped with a pioneering 2D network-on-chip architecture and a series of machine learning processors for optimal high-bandwidth performance and AI/ML workloads. They integrate interfaces for high-paced GDDR6 memory, 400G Ethernet, and PCI Express Gen5 ports. This 2D network-on-chip connects various interfaces to upward of 80 access points in the FPGA fabric, enabling ASIC-like performance, yet retaining complete programmability. The product encourages users to start with the VectorPath accelerator card which houses the Speedster7t FPGA. This family offers robust tools for applications such as 5G infrastructure, computational storage, and test and measurement.
Overview: The MIPI I3C Controller IP Core is fully compliant with the latest I3C specification, offering high bandwidth and scalability for integrating multiple sensors into mobile, automotive, and IoT system-on-chips (SoCs). This controller support in-band interrupts within the 2-wire interface, reducing pin count, simplifying board design, and lowering power and system costs. Backward compatibility with I2C ensures future-proof designs, and the controller's operating modes enable efficient connectivity for systems with multiple ICs and sensors on a single I3C bus. The ARM® AMBA® Advanced High-Performance Bus (AHB) facilitates seamless integration of the IP into the SoC. Key Features: Compliance with MIPI-I3C Basic v1.0 Backward compatibility with I2C Two-wire serial interface up to 12.5MHz using Push-Pull Dynamic and Static Addressing support Single Data Rate messaging (SDR) Broadcast and Direct Common Command Code (CCC) Messages support In-Band Interrupt capability Hot-Join Support Applications: Consumer Electronics Defense Aerospace Virtual Reality Augmented Reality Medical Biometrics (Fingerprints, etc.) Automotive Devices Sensor Devices
Our Expanded Serial Peripheral Interface (JESD251) Slave controller offers high data throughput, low signal count, and limited backward compatibility with legacy Serial Peripheral Interface (SPI) devices. It is used to connect xSPI Master devices in computing, automotive, Internet of Things, embedded systems, and mobile system processors to non-volatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports Single Data Rate (SDR) and Double Data Rate (DDR). • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for timing reference. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands for reading or writing data for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
Overview: The MIPI DSI Transmitter IP is designed to transmit data to the host processor, providing the mobile industry with a standard, robust, scalable, low-power, high-speed, and cost-effective interface that supports a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-DSI-2 version 2.0 Compliance with C-PHY version 2.0 for DSI-2 Version-2 Compliance with D-PHY version 1.2 for DSI-2 Version-2.0 Compliance with D-PHY version 2.0 for DSI-2 Version-2.0 Compliance with D-PHY version 3.0 for DSI-2 Version-2.0 Compliance with MIPI SDF specification Compliance with DBI-2 and DPI-2 Pixel to Byte conversion support from Application layer to LLP layer Support for Command Mode and Video Mode Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern for video mode support Lane Distribution Function for distributing packet bytes across N-Lanes Connectivity with two, three, or four DSI Receivers HS mode and Escape mode support for transmission of Packets in both C-PHY and D-PHY Symbol slip detection code and sync symbol insertion in C-PHY physical layer Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
KPIT Technologies offers sophisticated connected vehicle solutions that aim to bridge the gap between in-vehicle systems and the external digital ecosystem. These solutions enhance interaction, safety, and productivity for drivers by transforming vehicle cockpits into advanced digital platforms. KPIT's expertise in automotive infotainment, connectivity, and cloud integration services establishes it as a go-to partner for top-tier automotive OEMs and suppliers. The company provides well-researched platforms and tools that not only improve user experience but also offer innovative cockpit solutions that keep up with the fast-evolving digital consumer demands. KPIT's strength lies in its ability to integrate new technologies such as over-the-air (OTA) updates, cloud services, and data analytics seamlessly into automotive systems. The connected vehicle solutions include UI/UX development, digital cockpit components, and robust middleware for infotainment systems. By implementing cloud integration techniques and offering thorough support for OTA systems, KPIT ensures automotive systems are always up-to-date and functionally superior. KPIT's solutions have been widely adopted across millions of vehicles, underscoring the company's role in transforming the automotive landscape into one that is more digital, connected, and efficient. The firm's long-standing partnerships with OEMs and Tier-1 suppliers highlight the trust and reliability KPIT has earned in the automotive connectivity sector.
KPIT's powertrain solutions cover both electric and conventional vehicles, facilitating a faster time-to-market for OEMs and Tier-1 suppliers by providing software platforms and accelerators for electric components. With over 15 years of experience, KPIT offers ready-to-use software for electric vehicle components that are compliant with industry standards such as AUTOSAR. The provided solutions include production-ready components for vehicle and energy management systems, battery management systems (BMS), and smart chargers. KPIT supports the entire development cycle from prototype to production, encompassing embedded system challenges and offering end-to-end validation options, including Software-in-the-Loop (SIL), Model-in-the-Loop (MIL), and Hardware-in-the-Loop (HIL) testing. KPIT positions itself as a key partner through its strategic alliances and extensive expertise in control systems engineering. By addressing emerging needs in hybrid and electric domains, the company ensures compliance with global standards across multiple vehicle architectures. Additionally, KPIT's collaborative approach along with its partnerships with global leaders, facilitates innovations in electrified mobility, fostering advancements in electrification architecture while mitigating interoperability challenges.
Overview: The SPD5 Hub controller IP is designed to interface with the I3C/I2C Host Bus, allowing for the isolation of local devices such as Temperature Sensors (TS) from the master host bus. It features a Two-wire serial interface with SCL and SDA busses. Key Features: Compliance with JEDEC's JESD300-5 Support for speeds up to 12.5MHz Bus Reset functionality SDA arbitration support Enabled Parity Check Support for Packet Error Check (PEC) Switch between I2C and I3C Basic Mode Default Read address pointer Mode Write and read operations for SPD5 Hub with or without PEC In-band Interrupt (IBI) support Write Protection for NVM memory blocks Arbitration for Interrupts Clearing of Device Status and IBI Status Registers Error handling for Packet Error Check and Parity Errors Common Command Codes (CCC) for I3C Basic Mode Dynamic IO Operation Mode Switching Bus Clear and Bus Reset capabilities SPD5 Command features for NVM memory and Register Space Read and Write access to NVM memory Support for Offline Tester operation Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
The NMP-750 is engineered for edge computing, targeting markets like automotive, augmented and virtual reality, smart infrastructure, and communications. It's designed to address advanced applications such as mobility management, autonomous control, multi-camera processing, and energy management. This IP can provide up to 16 TOPS of performance with a memory capacity reaching 16 MB, featuring a choice between a RISC-V or Arm Cortex-R/A 32-bit CPU. It also includes 3 x AXI4 interfaces at 128 bits each, supporting high-throughput and low-latency operations vital for real-time applications and large-scale data processing needs.
KPIT's digital connected solutions offer an innovative framework for automotive companies aiming to leverage the vast possibilities of cloud and AI technologies. The focus is on enabling advanced vehicle management features from remote software operation to predictive analytics, transforming the role of software in the automotive industry. These solutions allow the seamless integration of cloud services with vehicle systems, enhancing end-user experiences through data-driven insights. KPIT offers customized platforms that streamline vehicle diagnostics, improve operational efficiencies, and enable features such as predictive maintenance and remote updates. Comprehensive service offerings ensure that customers benefit from vast data collection, robust asset management, and integrated analytics. KPIT not only provides the technical structure necessary for managing connected systems but also plays a pivotal role in crafting strategic roadmaps for deployment. The evolution of connected solutions by KPIT aims to simplify the management of automotive software, offering flexibility through remote service management and vehicle-to-cloud interactions. These advancements demonstrate KPIT’s commitment to pushing the boundaries of automotive technology.
Our Expanded Serial Peripheral Interface (JESD251) Master controller features a low signal count and high data bandwidth, making it ideal for use in computing, automotive, Internet of Things, embedded systems, and mobile system processors. It connects multiple sources of Serial Peripheral Interface (xSPI) slave devices, including nonvolatile memories, graphics peripherals, networking peripherals, FPGAs, and sensor devices. Features • Compliant with JEDEC standard JESD251 expanded Serial Peripheral Interface (xSPI) for Non-Volatile Memory Devices, Version 1.0. • Supports a single master and multiple slaves per interface port. • Supports Single Data Rate and Double Data Rate. • Supports source synchronous clocking. • Supports data transfer rates up to: o 400MT/s (200MHz Clock) o 333MT/s (167MHz Clock) o 266MT/s (133MHz Clock) o 200MT/s (100MHz Clock) • Supports Deep Power Down (DPD) enter and exit commands. • Standard support for eight IO ports, with the possibility to increase IO ports based on system performance requirements. • Optional support for Data Strobe (DS) for writemasking. • Supports 1-bit wide SDR transfer. • Supports Profile 1.0 commands to manage nonvolatile memory devices. • Supports Profile 2.0 commands to read or writedata for any type of slave device. • Compatible with non-volatile memory arrays such as NOR Flash, NAND Flash, FRAM, and nvSRAM. • Compatible with volatile memory arrays such as SRAM, PSRAM, and DRAM. • Supports register-mapped input/output functions. • Supports programmable function devices such as FPGAs. Application • Consumer Electronics. • Defence & Aerospace. • Virtual Reality. • Augmented Reality. • Medical. • Biometrics (Fingerprints, etc). • Automotive Devices. • Sensor Devices. Deliverables • Verilog Source code. • User Guide. • IP Integration Guide. • Run and Synthesis script. • Encrypted Verification Testbench Environment. • Basic Test-suite.
The Analog Glue solutions by Silicon Creations serve as essential support macros within complex SoC environments. These include components like bandgap references, POR generators, and CML buffers vital for enhancing the performance and reliability of clock systems. These elements work in tandem with Silicon Creations' PLLs and interfaces to provide low-jitter clock distribution throughout the chip, helping reduce risk and improve signal integrity. They are essential for complementing the main IP offerings, ensuring smooth integration and high performance in the end applications.
KPIT offers a comprehensive suite of solutions for Advanced Driver Assistance Systems (ADAS) and autonomous driving, aimed at facilitating the transition of prototype technologies into production-ready solutions. With expertise in system engineering, KPIT addresses the entire product lifecycle, from the development of system requirements to the functional safety analysis and implementation. The company's approach to achieving this involves a robust process derived from aerospace engineering, which ensures a safe and efficient system architecture at every level of the functionality. KPIT has leveraged its decades of experience and assembled an extensive engineering team dedicated to ADAS and autonomous driving, offering services from feature development through to software integration. Collaboration with more than 25 industry-leading OEMs and Tier-1 suppliers has resulted in extensive partnerships, delivering solutions that meet the high standards of ISO, NHTSA, NCAP, and SAE. The company's offerings also encompass end-to-end platform integration, ensuring seamless interoperability between software components to meet the unique demands of each client. Moreover, KPIT's software development methodologies incorporate advanced techniques such as AI and machine learning, which are pivotal in refining sensor fusion algorithms and localization tasks essential for autonomous vehicle operations.
The IDesignSpec GDI is a highly efficient graphical design interface offering an integrated platform for semiconductor design. It is aimed at enhancing the design process by providing a unified environment that supports the generation of development collateral from high-level specifications. The product facilitates seamless integration with other design and verification tools, ensuring that all teams remain aligned and efficient. One of its standout features is the ability to automatically update all output files whenever a specification changes, which significantly reduces manual errors and synchronizes the workflow across design, verification, and documentation stages. Designed with versatility in mind, IDesignSpec GDI supports the development of SOC, ASIC, and FPGA products. It offers features that streamline processes such as UVM Testbench creation, RTL design code generation, and system-level SoC validation. Its automated flow replaces the need for manual coding, allowing design teams to maintain focus on essential engineering tasks. This product is integral for teams keen on minimizing development time while maximizing productivity and accuracy across all stages of semiconductor development. Moreover, IDesignSpec GDI is known for its excellent support for various semiconductor elements such as registers and memories, standard IP, and custom sequences. It caters efficiently to the needs of design engineers, embedded programmers, and post-silicon lab teams, providing a robust framework for managing every developmental aspect. By ensuring consistency between firmware and software code, it upholds high standards, thereby guaranteeing the quality and reliability of the final product.
KPIT's vehicle engineering and design solutions encompass a comprehensive range of services that integrate traditional engineering principles with advanced technologies. This approach is designed to accelerate the development of next-generation vehicles by harnessing innovations in AI, simulation, and digital twins. Their offerings touch every aspect of vehicle development, from concept to completion, including integrated electrification solutions, and AI-driven CAE simulations. By employing digital twin technology and advanced CAD services, KPIT empowers automakers to optimize vehicle design processes, boosting efficiency and performance. The company provides full-spectrum engineering services that include new product design, value engineering, and virtual validation. These services ensure concepts transform into market-ready vehicles, maintaining high standards in both aesthetic and functional aspects of design. KPIT's expertise in classical mechanical engineering, conceptualized through a modern lens with smart harness solutions, facilitates the development of intelligent systems that align with the evolving needs of the automotive landscape. This synergy of classical and innovative methods showcases KPIT's comprehensive capabilities in leading engineering solutions.
The AES Block Cipher core from Alma Technologies implements highly efficient and flexible cryptographic operations, suitable for bolstering data security across various digital platforms. This core addresses a multitude of secure processing needs, ranging from enterprise safety measures to protecting personal user information in smart technologies. By accommodating the most prevalent modes of AES operation, this IP core is poised for effortless integration into numerous ciphered systems. Its ability to manage secure transactions and data patterns underscores its value in a security-first digital architecture, vital for data-heavy processes requiring encryption integrity and resource scalability within the tech industry.
The iDART platform by KPIT revolutionizes vehicle diagnostics and aftersales transformation by providing tools and services aimed at enhancing vehicle life-cycle management. The cloud-based system is designed to tackle the complexities of software-defined vehicle (SDV) diagnostics through improved connectivity and digitized services. iDART addresses the entire spectrum of diagnostics and aftersales services, from the development of electronic and electrical functions to maintaining the service lifecycle with competitive diagnostics solutions. It is crafted to manage the transition towards SDVs, emphasizing real-time diagnostics and predictive maintenance capabilities. The platform integrates a diverse range of tools for validating diagnostic functions, optimizing vehicle management, and providing solutions for advanced problem-solving and data management. Automakers benefit from substantial cost savings and improved efficiency in service delivery, supported by KPIT’s deep domain knowledge and strategic partnerships. KPIT's comprehensive approach ensures that the iDART platform supports a variety of contemporary requirements, from cybersecurity compliance to advanced system-of-chip diagnostics, maintaining high standards of service and innovation in automotive diagnostics.
Crafted to achieve a minuscule power footprint, the CM1014ff Current Bias IP delivers an ultra-low power performance of just 15.5nA with output trimming features. This characteristic is tailored for applications necessitating minimal power usage while maintaining high stability and precision. The output current trimming capability ensures that the circuit can be finely tuned to specific needs, thereby enhancing overall performance in targeted applications.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports EP & RC. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
The LVDS interfaces from Silicon Creations are engineered to enable bi-directional communication with high data rates, extending up to 3.3Gbps per lane in certain configurations. Compatible with a variety of standards such as miniLVDS and Camera Link, these interfaces are mainly used for video and chip-to-chip communication. They feature dynamic phase alignment and offer excellent signal integrity, aided by trimmable on-die terminations and robust word alignment. By leveraging their PLL technologies, these interfaces deliver substantial bandwidth with reliable performance across various environmental conditions, ensuring seamless connectivity between components.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
These oscillators by Silicon Creations are designed for critical applications like watchdog timers and core clock generators in microcontrollers. Characterized by their compact design and self-contained operation, these oscillators operate efficiently over a broad range of nodes, from 3nm to 65nm. They boast low power consumption below 30uW, coupled with precision in frequency stability post-trimming, offering reliable performance over extensive temperature and voltage ranges. Their ease of integration without the need for external components makes them highly desirable for low-power chip designs.
Overview: The Power Management IC (PMIC) is specifically designed for DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. It includes switching and LDO regulators to efficiently manage power distribution. The PMIC utilizes a MIPI-I3C Interface to select appropriate power settings for various application environments and is capable of operating at speeds up to 12.5MHz. Key Features: Maximum Operating speed of 12.5MHz Flexible Open-Drain IO (I2C) and Push-Pull (I3C) IO Support Multi-Time Programmable Non-Volatile Memory Interface Programmable and DIMM-specific registers for customization Error log registers for tracking Packet Error Check (PEC) and Parity Error Check functions Bus Reset function Support I3C Basic mode In-Band Interrupt (IBI) support Write, read, and default read operations in I2C mode Error handling for PEC, Parity errors, and CCC errors I3C Basic Common Command Codes (CCC) support Applications: DDR5 DIMM Application Environment DDR5 NVDIMM Application Environment Automotive Devices Memory Devices Power Management Devices Defense/Aerospace/Customer Electronics
LC-PLLs by Silicon Creations are engineered for ultra-low jitter and high precision across demanding applications such as analog front-end converters and RF clocking. They introduce advanced fractional-N architecture, highlighted by a small footprint and low power operation. Proven in cutting-edge process nodes like 7nm FinFET, these LC-PLLs deliver jitter metrics that meet stringent industry standards. With customizable loop bandwidths and fine-tuned jitter attenuation mechanisms, they excel in scenarios requiring high-speed, low-noise clock references, such as PCI Express applications.
Overview: The MIPI CSI-2 (Camera Serial Interface) Transmitter IP establishes an interface between a peripheral device (camera) and host processor (application engine) for mobile applications. It offers the mobile industry a standard, robust, scalable, low-power, high-speed, and cost-effective interface that caters to a wide range of imaging solutions for mobile devices. Key Features: Compliance with MIPI-CSI-2 version 3.0 Compliance with C-PHY 2.0 for MIPI CSI-2 Version 3.0 Compliance with D-PHY 2.5 for MIPI CSI-2 Version 3.0 Compatibility with I2C and I3C (SDR, DDR) for CCI interface Pixel to Byte conversion support from Application layer to LLP layer Continuous clock behavior in clock lane for D-PHY physical layer De-skew sequence pattern in Data Lane Module Lane Distribution Function for distributing packet bytes across N-Lanes Sync word insertion through PPI command in C-PHY physical layer Insertion of Filler bytes in LLP layer for packet footer alignment Setting specific bits in packet header Defining frame blanking period Seed selection in scrambler and de-scrambler by Sync word Support for C-PHY/D-PHY/A-PHY/M-PHY with one PHY layer configuration Target Applications: Imaging Surveillance Gaming Sensor devices Internet of Things (IoT) Wearable devices Virtual Reality Augmented Reality Automotive Systems
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuraon. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Oponal DMA support as plugin module. • Support for alternate negoaon protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuraon. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
Silicon Creations' SerDes interfaces are tailored for modern data applications requiring rapid and reliable data transfer across chip interfaces. These interfaces are operable in processes from 12nm to 180nm, delivering data rates up to 32.75Gbps. They support a vast array of protocols such as PCIe, JESD204, and SATA, amongst others, making them highly versatile. Employing ring PLLs, they achieve superior signal integrity, low jitter, and minimal power and area footprints. The architectures are compliant with the latest standards and ensure seamless interoperability in various technological ecosystems, particularly beneficial in networking and communication setups.
The PolarFire FPGA series delivers cost-efficient and power-saving solutions in the mid-range FPGA market. These devices are capable of operating transceivers at speeds from 250 Mbps to 12.7 Gbps and contain logic elements ranging from 100K to 500K, along with up to 33 Mbits of RAM. This family champions best-in-class security and dependability, making it highly suitable for a wide spectrum of applications that require reliable and secure data handling. Their architecture is designed for optimal power efficiency, catering to industries that require stringent energy management. The versatility of the PolarFire range promises adaptability and responsiveness to evolving industry needs. Its implementation in sectors such as communications and industrial applications underscores its capacity to meet diverse and demanding technological requirements.
The CoreVCO represents a dual wideband VCO solution, crucial for applications requiring extensive frequency ranges and minimal phase noise. Utilizing both SiGe CMOS and BJT technologies, it offers superior performance across a broad spectrum, from 0.7GHz to 6.6GHz. Designed with radiation hardening, this VCO is highly reliable for demanding environments like space and defense communications, encapsulated in a compact QFN48 package optimized for high-efficiency RF output.