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All IPs > Interface Controller & PHY > D2D > Universal Chiplet Interconnect Express(UCIe) VIP

Universal Chiplet Interconnect Express(UCIe) VIP

From MAXVY Technologies Pvt Ltd

Description

MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.

Features
  • Supports Universal Chiplet Interconnect Express Specification Version 1.0
  • Support for single and multiple stacks, single and multiple modules, and single and multi-lane configurations
  • Support for different flit modes, such as raw flit, CXL68B enhanced flit, standard and latency-optimized 256B flit
  • Support for ARB/MUX, CRC retry, link state management, parameter negotiation, power management link states, link training, scrambling/descrambling, sideband training transfers, lane repair, lane reversal, mainband/sideband interfaces, FDI/RDI interfaces, etc.
  • Support for native SystemVerilog (UVM) and Verilog languages, as well as all major simulators such as cadence xcelium, synopsys VCS, siemens Questasim, xilinx vivado, Aldec Riviera.
  • Support for directed and randomized flit generation, error injection at multiple levels, protocol checkers, layered protocol debugging trace files, throughput measurement, compliance test suite, etc.
  • Support for UCIe PCIe extended config space, unit-level FDI/RDI driver mode BFMs for standalone PHY testing, RDI BFM for simplified direct protocol/D2D only testing, etc
  • Support for functional coverage for complete UCIe features, monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • Support for runtime configurable BFM settings.
Tech Specs
Class Value
Categories Interface Controller & PHY > D2D
Compliant Standard UCIe Specification version 1.0
Part Number UCIe
Availability All Countries & Regions
Applications
  • High Performance Computing (HPC)
  • Cloud Computing
  • Mobile Devices
  • Automotive Systems
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