Overview:
The UCIe IP supports multiple protocols (CXL/PCIe/Streaming) to connect chiplets, reducing overall development cycles for IPs and SOCs. With flexible application and PHY interfaces, The UCIe IP is ideal for SOCs and chiplets.
Key Features:
Supports UCIe 1.0 Specification
Supports CXL 2.0 and CXL 3.0 Specifications
Supports PCIe Gen6 Specification
Supports PCIe Gen5 and older versions of PCIe specifications
Supports single and two-stack modules
Supports CXL 2.0 68Byte flit mode with Fallback mode for PCIe non-flit mode transfers
Supports CXL 3.0 256Byte flit mode
Supports PCIe Gen6 flit mode
Configurable up to 64-lane configuration for Advanced UCIe modules and 16 lanes for Standard UCIe modules
Supports sideband and Mainband signals
Supports Lane repair handling
Data to clock point training and eye width sweep support from transmitter and receiver ends
UCIe controller can work as Downstream or Upstream
Main Band Lane reversal supported
Dynamic sense of normal and redundant clock and data lines activation
UCIe enumeration through DVSEC
Error logging and reporting supported
Error injection supported through Register programming
RDI/FDI PM entry, Exit, Abort flows supported
Dynamic clock gang at adapter supported
Configurable Options:
Maximum link width (x1, x2, x4, x8, x16)
MPS (128B to 4KB)
MRRS (128B to 4KB)
Transmit retry/Receive buffer size
Number of Virtual Channels
L1 PM substate support
Optional Capability Features can be Configured
Number of PF/VFDMA configurable Options
AXI MAX payload size Variations
Multiple CPI Interfaces (Configurable)
Cache/memory configurable
Type 0/1/2 device configurable
