All IPs > Interface Controller & PHY > PCI
The PCI (Peripheral Component Interconnect) category within semiconductor IPs focuses on providing robust solutions for high-speed data communication between a CPU and peripheral devices. In today's technology-driven world, PCI semiconductor IPs are essential in ensuring efficient and reliable connections across a wide range of applications, from personal computers to enterprise servers.
Products within this category are designed to support various PCI versions, including PCI, PCI-X, and the more advanced PCI Express. These IP solutions include interface controllers and PHYs (Physical Layer Transceivers) that facilitate the seamless integration of PCI technology into new and existing systems. By enabling higher bandwidth and improved data transfer rates, these IPs are crucial for applications requiring rapid data processing and high-performance computing.
Utilizing PCI semiconductor IPs can significantly enhance the operational capabilities of systems, making them ideal for use in industries that demand superior data handling capacities, such as data centers, high-performance workstations, and network infrastructure. The versatility and scalability of PCI IP solutions allow designers to customize and optimize their products to meet specific architecture requirements and performance goals.
Moreover, PCI semiconductor IPs provide manufacturers with a competitive edge by allowing for rapid development cycles and reduced time to market. By leveraging pre-validated and highly efficient designs, companies can focus on innovation and strategic advancements while relying on proven technologies for foundational elements. This not only ensures compatibility and interoperability but also drives innovation in creating cutting-edge technology solutions for the modern era.
Primesoc's PCIE GEn7 IP is dual mode controller , supporting upto 128Gbps per lane data rate , which can work as root complex or as an endpoint. This is a soft IP which can support serdes and non serdes architectures and PIPE interface of 64bit and lanes configurable from 1/2/4/8/16.
Silicon Creations' SerDes Interfaces are crafted to handle high-speed data transmission challenges over varied processes, ranging from 12nm to 180nm. Addressing multiple protocols such as CPRI, PCIe, and SATA, these interfaces demonstrate flexibility by supporting data transmission speeds from 100 Mbps to beyond 32 Gbps. The architecture incorporates a host of advanced features including adaptive equalization techniques and programmable de-serialization widths, making it stand out in terms of performance and signal integrity even under challenging conditions. With ultra-low latency PMAs, they sustain excellent operational speed and efficiency, imperative for sophisticated communication applications. Moreover, Silicon Creations partners with leading entities to provide comprehensive solutions, including complete PCIe PHY integrations. This synergy ensures that SerDes Interfaces are fully optimized for operational excellence, delivering stable and reliable communication signals. With an emphasis on low power and minimized area requirements, they cater to burgeoning industry needs for power-efficient and space-conservative designs.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuraon. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports serdes and non – serdes architecture. • Oponal DMA support as plugin module. • Support for alternate negoaon protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuraon. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
PCIE is a layered protocol high speed interconnect interface supporting speeds up to 128Gbps and multi lanes and links. The layers speci_ied in PCIE speci_ication Transport, Datalink, Physical layers (digital packet) are implemented in PRIMEXPRESS IP along with PIPE interface logic connecting to PHY and AXI Bridging logic to connect to applications. Features: • Supports PCIE Gen 7 draft Spec. • Supports Pipe 6.X Spec. • PCIE Gen 7.0 Core supports Flit and non – Flit Mode. • Supports X16, X8, X4, X2, X1 Lane Configuration. • AXI MM and Streaming supported. • Supports Gen 1, Gen 2, Gen 3, Gen 4, Gen 5, Gen 6, Gen 7 modes. • Data rate support of 2.5 Gbps, 5 Gbps, 8 Gbps, 16 Gbps, 32 Gbps, 64 Gbps, 128 Gbps. • PAM support when operating at 64Gbps/ 128Gbps. • 8b/10b,128b/130b,1b/1b encoding , decoding support. • Supports EP & RC. • Supports serdes and non – serdes architecture. • Optional DMA support as plugin module. • Support for alternate negotiation protocol. • Lane polarity thru register control. • Lane deskew supported. • Support for L1 states. • L0P Supported. • SKP OS add/removal. • SRIS mode supported. • No equalization support thru configuration. • Deemphasis negotiation support at 5GT/s. • EI inferences in all modes. • PTM, OBFF, MSI, MSIX, Power management and all message format supports.
The PCIe Gen 5 Chiplet from YorChip is designed to meet the demands of high-speed data transfer applications. Aimed at supporting next-generation PCI Express technology, this chiplet offers enhanced bandwidth to satisfy the increasing data rate requirements of modern computing environments. Its architecture supports the integration into larger chiplet systems, facilitating the creation of high-performance, scalable semiconductor solutions. By leveraging cutting-edge technology, the PCIe Gen 5 Chiplet ensures low latency and high efficiency, making it ideal for applications requiring fast and reliable data throughput. Its design is optimized for compatibility with various process nodes, ensuring its adaptability to different manufacturing needs. This flexibility and performance make it a vital component for reducing costs and improving performance in complex electronic systems. Additional technical specifications and unique features enhance its robustness and reliability, ensuring it meets the high standards expected in enterprise-grade computing environments. Overall, this chiplet represents a significant step forward in PCI Express technology, providing a scalable and efficient solution suitable for a wide range of applications.
The CT25205 Digital IP core is engineered to provide the core building blocks for 10BASE-T1S Ethernet applications, including PMA, PCS, and PLCA Reconciliation Sublayer adherence. Written in Verilog 2005 HDL, it is fully synthesizable with standard cells and FPGA, working cohesively with standard IEEE CSMA/CD Ethernet MAC via MII. The unit supports advanced PLCA features, enabling seamless communication with existing MAC devices. Connectivity is ensured through a standard OPEN Alliance 10BASE-T1S PMD Interface, creating an optimal solution for Zonal Gateway SoCs and MCUs adopting innovative 10BASE-T1S communication.
Panmnesia's CXL 3.1 Switch represents a pivotal innovation in memory expansion and connectivity solutions, bridging the gap between diverse computing resources. This cutting-edge device utilizes CXL 3.1 technology to create a seamless communication link between different system components, such as GPUs, CPUs, and memory expanders. By leveraging such advanced interconnect technology, the switch enables a more flexible and scalable infrastructure, capable of supporting a wide range of devices within a data center environment. The switch's architecture is designed for high scalability, allowing for sophisticated multi-level switching and port-based routing. This flexibility not only enhances scalability across multiple servers but also ensures that various types of computing devices can be easily integrated into a unified system framework. The switch's support for CXL mem, cache, and I/O protocols ensures broad compatibility and optimal performance across a multitude of applications. As part of its development, the switch incorporates advanced features that facilitate memory sharing and resource pooling. This positions it as a key component in the construction of high-performance data centers, enabling significant reductions in operational costs while improving overall system efficiency. With its robust connectivity capabilities, the CXL 3.1 Switch is central to creating AI clusters and accelerating modern AI applications, establishing Panmnesia as a leader in cutting-edge technological solutions for tomorrow's data infrastructure.
The AXI Bridge for PCIe is a versatile Smartlogic solution featuring up to four AXI4 interfaces. This IP core seamlessly translates AXI read and write commands into PCIe Transaction Layer Packets, maintaining continuous parallel operations across all interfaces with zero interference. Unused interfaces can be deactivated to conserve logical resources, highlighting its efficiency-oriented design. The inclusion of a high-performance kernel mode driver enhances its operability on Windows and Linux systems, paving the way for easy software integration. This characteristic allows users to transfer payloads without delving into the complexities of PCIe packet formation. Ideal for various applications, especially in networking, this component provides dependable solutions where high throughput and low-latency data interactions are essential. It stands out for its ability to support dynamic Ethernet applications, ensuring that network environments function optimally at all times.
The G-Series Controller from MEMTECH is conceived for graphics-heavy computing environments, balancing high bandwidth and low power demands. This controller supports GDDR6 devices at speeds reaching up to 18 Gbps. It incorporates dual-channel support, advanced scheduling, and error detection ensuring robust data throughput with minimal latency. Suitable for applications such as gaming, video processing, and AI, the G-Series Controller facilitates efficient integration and supports various power-saving features.
The Titanium Ti375 FPGA from Efinix boasts a high-density, low-power configuration, ideal for numerous advanced computing applications. Built on the well-regarded Quantum compute fabric, this FPGA integrates a robust set of features including a hardened RISC-V block, SerDes transceiver, and LPDDR4 DRAM controller, enhancing its versatility in challenging environments. The Ti375 model is designed with an intuitive I/O interface, allowing seamless communication and data handling. Its innovative architecture ensures minimal power consumption without compromising on processing speed, making it highly suitable for portable and edge devices. The inclusion of MIPI D-PHY further expands its applications in image processing and high-speed data transmission tasks. This FPGA is aligned with current market demands, emphasizing efficiency and scalability. Its architecture allows for diverse design challenges, supporting applications that transcend traditional boundaries. Efinix’s commitment to delivering sophisticated yet energy-efficient solutions is embodied in the Titanium Ti375, enabling new possibilities in the realm of computing.
The D2200 is a high-performance PCIe SSD designed by Swissbit for enterprise and data center applications. It combines exceptional data speeds with low power consumption to enhance system performance. This SSD is equipped with state-of-the-art NAND technology, ensuring sustained performance even under intense workloads. The D2200's design prioritizes temperature and performance management, making it resilient against environmental extremes and suitable for mission-critical applications.
The ePHY-5616 product is crafted to handle data rates from 1 to 56Gbps. Operating prominently on 16 and 12nm technology nodes, this solution is ideal for applications that demand scalable insertion loss and data rate adaptability. The architecture is robust, leveraging advanced DSP techniques to provide exceptional clock data recovery and superior BER (Bit Error Rate), catering to both enterprise and data center needs. Its utility extends to routers, switches, and other critical data infrastructure components.
The U9 Flash Memory Controller is specifically designed to meet industrial requirements while also featuring a USB 3.1 interface. It incorporates advanced hyReliability™ flash management, ensuring the efficient handling of flash memory with support for flexible ECC up to 96-Bit/1K. This controller emphasizes security, boasting high-performance AES 128 and 256 encryption engines and customizable firmware extensions. By providing a robust solution with continuously updated flash memory support, the U9 is ideal for designing reliable eUSB, USB flash drives, and USB security solutions.
The DisplayPort Transmitter from Trilinear Technologies is designed to deliver high-performance video and audio transmission for an array of display applications. It adheres to the latest standards to guarantee seamless integration with contemporary devices. Optimized for efficiency, it provides not only superior video quality but also minimizes latency to ensure a smooth user experience. Engineered with flexibility in mind, the DisplayPort Transmitter supports various resolutions and refresh rates, making it suitable for a wide range of multimedia interfaces. It is developed to handle complex signal processing while remaining energy-efficient, a critical feature for applications requiring prolonged usage without substantial power consumption. This transmitter's robust architecture ensures compatibility and reliability, standing as a testament to Trilinear's commitment to quality. It undergoes rigorous testing to meet industry standards, ensuring that each product can withstand varying operational conditions without compromising on performance or reliability, which is indispensable in today's dynamic tech environment.
The Multi-Channel Flex DMA IP Core offers an adaptable solution for handling up to 16 streaming channels, each managed independently to prevent mutual obstruction. Users can customize the data rate for each channel to optimize interfacing simplicity while incorporating prioritized FIFO buffers to ensure crucial data streams maintain supremacy. Designed with streaming and co-processor applications in mind, this IP core reads data from any source, processes it, and disseminates it to designated targets. Additionally, the core includes mechanisms for monitoring CRC errors along PCI Express links, enabling the prompt identification and exclusion of assemblies with subpar signal integrity during production testing. This core is paramount in safety-critical applications, where signal integrity and real-time data management are vital, offering high reliability and responsiveness in demanding environments. Its blend of efficiency and precision makes it a favorite for being able to swiftly adapt to varied processing needs without compromising on performance quality.
Efinix's Topaz FPGA series is engineered for mass-market applications, delivering a perfect mix of efficiency and adaptability. These FPGAs encapsulate a highly efficient architecture, combined with the industry's essential features and protocols, such as PCIe Gen3, MIPI, and LPDDR4. This configuration allows users to harness substantial performance while maintaining ample room for future innovations. Topaz FPGAs are optimized for high-volume production environments where cost-effectiveness and swift integration are paramount. Their design promotes ease of implementation in various applications, spanning from automotive to deeply embedded systems, where reliability and robustness are key. Featuring a streamlined architecture, Topaz series FPGAs support modern connectivity standards and data processing capabilities. These devices are tailored for industries requiring scalable solutions that can adapt to evolving technological landscapes, ensuring that Efinix customers remain competitive in their respective fields.
Dream Chip Technologies' Arria 10 System on Module (SoM) emphasizes embedded and automotive vision applications. Utilizing Altera's Arria 10 SoC Devices, the SoM is compact yet packed with powerful capabilities. It features a dual-core Cortex A9 CPU and supports up to 480 KLEs of FPGA logic elements, providing ample space for customization and processing tasks. The module integrates robust power management features to ensure efficient energy usage, with interfaces for DDR4 memory, PCIe Gen3, Ethernet, and 12G SDI among others, housed in a form factor measuring just 8 cm by 6.5 cm. Engineered to support high-speed data processing, the Arria 10 SoM includes dual DDR4 memory interfaces and 12 transceivers at 12 Gbit/s and above. It provides comprehensive connectivity options, including two USB ports, Gigabit Ethernet, and multiple GPIOs with level-shifting capabilities. This level of integration makes it optimal for developing solutions for automotive systems, particularly in scenarios requiring high-speed data and image processing. Additionally, the SoM comes with a suite of reference designs, such as the Intel Arria 10 Golden System Reference Design, to expedite development cycles. This includes pre-configured HPS and memory controller IP, as well as customized U-Boot and Angström Linux distributions, further enriching its utility in automotive and embedded domains.
The CANmodule-III is a highly advanced Controller Area Network (CAN) controller designed for sophisticated applications that require full CAN2.0B compliance. This IP module optimizes communication on the CAN bus by efficiently handling message transactions with support for FIFO and mailbox-based architectures. With a focus on system reliability, the CANmodule-III ensures seamless data flow and is versatile for various industry applications such as automotive and aerospace networks. The CANmodule-III supports an expansive set of features including enhanced diagnostic capabilities, making it ideal for applications that demand high reliability and advanced fault-tolerant functionalities. Its modular design is key for dynamic environments where scalability and flexibility are paramount. By utilizing a robust design approach based on Bosch's fundamental CAN architecture, this controller ensures compatibility and conformance with international standards, streamlining integration into existing systems. Inicore's commitment to excellence is embodied in the CANmodule-III’s design, which not only simplifies the integration process but also provides users the ability to customize functionalities. Whether the need is for rapid prototyping using FPGAs or volume production with ASICs, the CANmodule-III stands out as a preferred choice owing to its proven performance and adaptability.
The CANmodule-IIIx represents an evolution in CAN controller IP, offering an advanced set of features and capabilities for high-demand applications. This module builds upon the strengths of its predecessor with extended mailbox support, featuring 32 receive and 32 transmit mailboxes which enhance message handling capacity and ensure higher data throughput and reduced latency. For industries such as industrial automation and telecommunications, where complex data transactions are constant, the CANmodule-IIIx provides a robust platform capable of managing these requirements with efficiency and reliability. The IP module supports customization and can be seamlessly integrated into larger system architectures, enabling greater functionality and performance tuning for specific application needs. Designed with a focus on flexibility, this module adheres to CAN2.0B standards while offering unique enhancements for user-defined add-ons. These features allow for superior adaptability and scalability, making CANmodule-IIIx a versatile solution across various sectors requiring sophisticated CAN bus communications.
Trilinear Technologies' DisplayPort Receiver is crafted to facilitate high-definition video and audio reception for modern display systems. Emphasizing low power consumption, it is tailored for devices that require extended operational periods without sacrificing performance. This receiver is adaptable to various settings, accommodating different display resolutions and delivering crisp, vibrant visuals consistently. Its advanced signal processing capabilities reduce potential interference, thus maintaining signal integrity across numerous scenarios. Such features are particularly beneficial for both commercial and consumer multimedia products. Reliability is at the heart of the DisplayPort Receiver’s design, featuring a resilient structure capable of withstanding tough environments while ensuring consistent output. Trilinear Technologies ensures each unit meets stringent compliance standards, equipping clients with a durable receiver that seamlessly integrates into diverse digital architecture setups.
Algo-Logic's FPGA Tick-To-Trade platform focuses on optimizing the critical path in high-frequency trading by incorporating trading algorithms into FPGA-based systems for rapid execution. The solution significantly enhances the performance of order management systems by reducing the time between receiving and executing trading data, termed as 'Tick-To-Trade.' This reduction in latency is especially beneficial for proprietary trading firms and market makers who thrive on the speed of trade execution. This platform capitalizes on the speed advantage inherent in FPGA technology, combined with Algo-Logic’s proprietary logic designs aimed at providing deterministic performance. By minimizing variables such as jitter and latency, the Tick-To-Trade solution ensures that trading algorithms can execute trades as quickly as the market environment allows. Supported across multiple FPGA platforms from industry giants like Cisco and Xilinx, Algo-Logic’s solution integrates seamlessly into existing infrastructures, allowing clients to leverage ultra-low latency networking capabilities without overhauling their current systems. The emphasis on adaptability and robustness makes it a preferred choice for institutions investing in high-frequency trading architectures.
The Multi-Channel AXI DMA Engine excels in bridging AXI Stream and AXI Memory mapped operations, managed by a potent DMA engine. Capable of processing data from 16 AXI Stream Slave inputs, it ensures efficient data writing and reading into DDR memories. AXI Stream Masters can extract information, enabling further DSP processing across multiple streams. The inclusion of programmable address generators allows non-linear data storage, simplifying the retrieval process for algorithmic units by categorizing data in easily manageable sections or Regions of Interest (ROI). This functionality greatly aids subsequent data sorting and processing activities. By facilitating compatibility with GStreamer and offering Linux driver support, this IP core is versatile for use in SoC-based environments that demand seamless data handling and processing. Its adaptability extends to non-SoC FPGAs requiring efficient DDR data buffering, making it indispensable for a wide array of data-intensive digital environments.
The PCIe Gen 4 interface supports multiple generations of PCI Express standards, ranging from 1.0 to 4.0, and achieves data rates up to 16 Gbps. With the aid of CTLE, it boosts signals up to 18 dB at 8 GHz, ensuring robust performance even in demanding environments such as data centers where high data throughput is critical.
Inicore's CANmodule-IIx is a FIFO-based Controller Area Network (CAN) controller IP that provides efficient and reliable communication solutions for less complex systems that still require robust CAN functionality. With the flexibility of FIFO architecture, this module is designed for systems where message ordering and buffering are crucial yet straightforward. The CANmodule-IIx facilitates seamless data exchange over the CAN bus, ensuring that all message transactions comply with the CAN2.0B standard. This makes it particularly well-suited for automotive applications, as well as industrial systems needing basic to intermediate communication capabilities while maintaining a cost-effective footprint. As part of Inicore’s vast IP portfolio, the CANmodule-IIx is engineered with a focus on simplifying integration and reducing design complexity. Its FIFO architecture provides not only reliable communication but also enhanced data handling capabilities, allowing seamless implementation in various FPGA and ASIC environments, supporting rapid development and deployment.
The ePHY-11207 marks the frontier of eTopus's high-speed SerDes capabilities, facilitating data rates from 1 to 112Gbps. This 7nm nodal innovation is particularly significant in environments where latency precision and bandwidth are critical, such as in advanced networking interfaces and server applications. It integrates seamlessly with the existing network fabric, supporting high throughput demands and lower latency metrics, bolstered by eTopus's proprietary algorithms.
The AXI Bridge with DMA for PCIe from Smartlogic is engineered for high-performance data transfer applications, providing an array of industry-standard AXI interfaces. Designed to handle complex data streaming from FPGA to Host or vice versa, this IP core supports concurrent operations across all interfaces without interference. Its smart design allows for easy access to remote memory locations for shared and peer-to-peer memory applications. This product is notable for its ability to manage continuous data flow effectively, making it ideal for developers crafting sophisticated PCIe endpoints without deep protocol expertise. The inclusion of a kernel mode driver for Windows and Linux ensures smooth software integration, simplifying the deployment in diverse operating systems. Such integration allows developers to focus on transmitting raw data rather than crafting compliant PCIe packets, reducing complexity and development time. The core is especially valuable in network applications, where seamless Ethernet compatibility is crucial. Its robustness makes it well-suited for applications needing reliable data exchange and control over extensive data transactions, particularly in environments demanding high processing throughput and modular expansion capabilities.
Algo-Logic’s ULL 10GE PHY+MAC is designed to deliver exceptional low-latency performance tailored for 10 Gigabit Ethernet environments. The product, targeted for high-frequency trading (HFT) and high-performance computing (HPC) systems, ensures that data transactions are completed swiftly and reliably. This IP core stands out with its compliance with IEEE802.3 standards and support for both Avalon-ST and AXI4-Stream interfaces, making it a versatile choice for various FPGA platforms. Key features include local and remote fault detection, frame check sequence processing, and compatibility with SERDES. The core is engineered to offer a straightforward replacement for default high-latency vendor cores, providing trading firms with a robust solution to enhance the performance of their systems significantly. Optimizations within the core reduce gate count while maintaining system flexibility, which is crucial for maintaining the competitive edge in trading applications.
The High-Channel-Count DMA IP Core is specialized for memory-intensive applications demanding high throughput, accommodating up to 64 data streams. It efficiently allocates streams within distinct host memory regions via DMA while facilitating user logic interfacing through up to 8 AXI4 (Full/Lite) masters. In addition to supporting data reading with up to 16 AXI Stream masters, this core simplifies the development of complex PCIe endpoints by enabling users to focus solely on data payloads, eliminating the need for intricate PCIe packet management. This capability makes it ideal for data-intensive operations such as streaming, Ethernet applications, and high-level computations. The IP core is equipped for Ethernet compatibility and comes with a detailed schematic to assist in implementation, ensuring that network congestion or interruptions have minimal impact on its performance. It is designed to support high-performance data handling and fast processing for real-time applications.
The Mil1394 AS5643 Link Layer Controller offers a comprehensive hardware-based implementation, designed specifically for handling full network stacks in military and aerospace environments. This IP simplifies the routing of data packets, ensuring swift and secure communication across networks. Ideal for advanced avionics systems, it manages label lookups, DMA controllers, and message chains efficiently, thus ensuring data reliability and consistency. The interface is F-35 compatible, catering to modern military aircraft systems demanding high reliability and operational synchronization. The IP's robustness is demonstrated in the ability to maintain data integrity across varied and challenging environments. It brings forth an architecture that aids in sustaining network communications without loss, distortion, or delays, critical for mission-critical applications.
The Multi-Channel Silicon Photonic Chipset by Rockley Photonics represents a milestone in high-speed data transmission technology. It combines silicon photonics with the hybrid integration of III-V Distributed Feedback (DFB) lasers and electro-absorption modulators to deliver a high-performance chipset capable of supporting data rates of up to 400 GBASE-DR4. Each channel in the transmitter achieves substantial optical modulation amplitude (OMA) and a high extinction ratio with minimal TDECQ penalty, ensuring compliance with IEEE standards. This chipset is tailored for high-bandwidth and high-data rate applications, providing the essential infrastructure for advanced data communication networks. By merging III-V DFB lasers with electro-absorption modulators, the system can operate efficiently across multiple channels, enhancing data transfer speeds while maintaining signal integrity. The innovation of this chipset lies in its multi-channel design, which facilitates increased data throughput and reliability. It is particularly useful in data centers and network systems where rapid data exchange is critical. Rockley's chipset also emphasizes energy efficiency and signal precision, which are crucial for meeting the growing demands of modern telecommunications architectures and network environments.
YouSerdes is designed to deliver high-speed, multi-rate serial data communication, operating in the range of 2.5 to 32Gbps, which is critical for today's data-intensive environments. It integrates multiple SERDES channels, combining superior performance with efficient space and power usage. The architecture ensures that signal integrity is maintained across diverse conditions, making it a preferred choice for high-speed data transmission tasks. The design ethos of YouSerdes revolves around maximizing bandwidth and minimizing latency. This makes it suitable for integration in products that require rapid data processing and transmission, such as telecommunication infrastructure and high-performance computing systems. By ensuring consistent results across various deployment conditions, YouSerdes supports diverse application needs while offering flexibility in system design. Moreover, YouSerdes emphasizes power efficiency and high area performance, which are achieved through advanced architectural optimizations. These enhancements deliver crucial advantages in designing systems that require both speed and efficiency, reinforcing its importance in data-centric industries.
RegSpec is a comprehensive register specification tool that excels in generating Control Configuration and Status Register (CCSR) code. The tool is versatile, supporting various input formats like SystemRDL, IP-XACT, and custom formats via CSV, Excel, XML, or JSON. Its ability to output in formats such as Verilog RTL, System Verilog UVM code, and SystemC header files makes it indispensable for IP designers, offering extensive features for synchronization across multiple clock domains and interrupt handling. Additionally, RegSpec automates verification processes by generating UVM code and RALF files useful in firmware development and system modeling.
SystemBIST represents a comprehensive plug-and-play device enhancing FPGA configurations and embedded JTAG testing methodologies on PCBs. This sophisticated module allows for seamless FPGA device programming and reconfiguration in-field, supporting IEEE 1532 and IEEE 1149.1 standards. Designed with a vendor-independent approach, SystemBIST offers scalable configurations for both flash memory and CPLD devices, integrating built-in self-tests (BIST) that utilize stored test patterns in flash memory. This product simplifies the traditional complex methods of FPGA configuration, removing the need for large PROM parts and streamlining production concerns with its cost-effective design, widening its appeal across sectors needing flexible, reliable re-programmable solutions.
The SMS PCI-Express PHY IP from Soft Mixed Signal Corporation is a high-performance solution designed in compliance with the PCI-Express Base and PIPE specifications. This scalable and low-power PHY is engineered for enterprise-grade systems, supporting the PCI-Express standard seamlessly across various applications. Tailored for efficiency, it incorporates a full PIPE-compliant transceiver, delivering comprehensive support for demanding data throughput requirements. This IP boasts a sophisticated architecture that optimizes silicon area utilization, featuring innovative clock recovery mechanisms that ensure exceptional performance even in noisy environments. The PHY's design, supporting single and multi-lane configurations, makes it adaptable to various scales of integration, from desktop systems to complex enterprise servers. Integrated with multi-layer compatibility, the SMS PCI-Express PHY interfaces efficiently with existing link and transport layer blocks. It includes high-quality PMA and PCS implementations, facilitating seamless interaction with MAC and other system components. This IP is a versatile solution for systems that require robust, high-speed interconnect technology, poised to meet the evolving demands of modern data-centric applications.
The BlueLynx Chiplet Interconnect offers an advanced die-to-die interconnect solution, tailored to meet the rigorous demands of contemporary chiplet designs. With support for Universal Chiplet Interconnect Express (UCIe) and the Open Compute Project's Bunch of Wires (BoW), this IP establishes a robust physical and link layer interface for chiplet communications. It's built to connect efficiently with on-die bus standards like AMBA AXI and ACE, streamlining the process of linking chiplets within advanced package configurations. Technologically sophisticated, BlueLynx supports a variety of fabrication nodes ranging from 16nm down to 3nm, ensuring compatibility across multiple semiconductor foundries. This interconnect solution is silicon-proven and enables not only rapid development but also minimizes the traditional risks associated with new designs. Clients receive a comprehensive ASIC integration package, including platform software and design references, which allows for swift silicon bring-up and ensures that first-pass silicon achieves expected operational standards. The architecture of BlueLynx is designed to be both customizable and efficient. With data rates stretching from 2 Gb/s up to over 40 Gb/s, and low power consumption underpinning its design, BlueLynx manages to provide a high bandwidth density of over 15 Tbps/mm². This results in optimal performance scaling across diverse applications while accommodating advanced 3D packaging options. The PHY component of the IP is specifically designed for high compatibility and minimal latency, built on the architecture that supports configurable serialization and deserialization ratios, multiple PHY slices, along with detailed specifications for bump pitch and package applications.
Intellitech's Fast Access Controller (FAC) is a high-speed, pre-engineered solution tailored for enhancing design-for-test processes, particularly in environments requiring extensive flash programming through FPGA interconnections. The FAC leverages the JTAG standard to offer swift and efficient programming capabilities directly via the 1149.1 bus, reducing overall system programming time and supporting seamless integration with existing computing infrastructure. This controller is engineered for applications demanding quick microcontroller, DSP, or CPU programming in both research and commercial landscapes, facilitating improved design quality and reducing deployment cycles.
PCIe Solutions stands as a leading option for designers aiming to incorporate efficient data transfer protocols within their systems. By continually upgrading to the latest PCIe specifications while providing backward compatibility, this IP ensures robust, flexible solutions ideal for high-speed applications. Its design simplifies integration, encouraging cost-effective development without sacrificing technological superiority. The offerings include configurations for both endpoints and root complexes, optimally serving various architectural structures within electronic devices. Additionally, it features dual-mode operations and retiming capabilities, further enhancing the efficiency of data transmission processes across multiple platforms. This IP is ideal for developers focusing on enhancing system performance and reliability in sectors such as data centers, communication networks, and cloud infrastructure. The seamless compatibility with different PCIe generations means it fits well into pre-existing systems, allowing for straightforward upgrades and extensions.
Designed to cater to modern high-speed data applications, the ePHY-5607 offers impressive performance across data rates from 1Gbps to 56Gbps utilizing a highly efficient 7nm process node. Its design is finely tuned for power, performance, and area (PPA) optimization, making it suitable for an array of applications such as data centers, smart NICs, and AI storage. Benefitting from eTopus's sophisticated DSP-based receiver architecture, it is equipped to handle a wide range of insertion losses while maintaining low latency.
The FPGA Pre-Trade Risk Check IP by Algo-Logic is engineered to perform lightning-fast, real-time risk analyses prior to trade execution. This solution is tailored for financial institutions that need to adhere to strict compliance mandates while executing trades at speeds that approach the limits of current technology. By integrating directly into trading systems, the IP enables pre-trade checks without compromising speed, offering a significant advantage in the fast-paced environment of financial trading. Designed for use with FPGA technology, this risk check system provides an infrastructure for reducing the lag associated with traditional software-based risk assessments. It allows firms to verify parameters and assess risks instantly as trades are enqueued, enhancing both the speed and accuracy of trade verifications. The Pre-Trade Risk Check system built on FPGAs benefits from low-latency processing and high-determinism, crucial for maintaining a competitive edge in the trading industry. By leveraging this IP, firms can better manage operational risks and maintain regulatory compliance more efficiently.
Analog Bits presents a line of low-power SerDes IPs, including PCIe Gen 3, 4, and 5 classes, customizable to a broad spectrum of market requirements. These SerDes are expertly designed and taped out in technologies such as 8nm, 7nm, and 5nm, offering data rates of up to 32Gbps. With a focus on minimizing power consumption, Analog Bits’ SerDes support multiple protocols like PCIe, SAS, SATA, HMC, and USB, providing excellent flexibility and reliability for enterprise applications. Their efficient design ensures minimal latency, unlimited lane count, and can be strategically placed anywhere on an SoC, enhancing the versatility of system designs.
The hellaPHY Positioning Solution by PHY Wireless utilizes cutting-edge technology for high precision and secure location tracking over cellular networks. It is particularly designed to cater to massive IoT applications, providing low-power and cost-efficient solutions that work seamlessly indoors and outdoors. Leveraging 5G and advanced edge computing, this solution ensures maximum privacy and scalability, making it ideal for diverse applications ranging from smart labels to logistics tracking. This solution dramatically outperforms traditional GNSS systems by using far less data, reducing costs, and enhancing spectral efficiency. Its innovative approach involves device-based processing of standardized 5G signals, which means the device's location is calculated locally. This not only improves speed and accuracy but also maintains a high level of data security, as the location information is encrypted and not shared with third-party servers. Designed with practicality and adaptability in mind, the hellaPHY Positioning Solution integrates effortlessly into existing hardware through a simple API, supporting a range of devices without the need for extensive modifications. With PHY Wireless's patented algorithms, operators can optimize their spectrum use, and users enjoy a robust location service that meets various operational demands. The technology underlying the hellaPHY Positioning Solution stands as evidence of PHY Wireless's commitment to innovation, ensuring that their products meet the growing needs of the IoT landscape. With support for existing LTE and 5G networks, this solution offers businesses a future-proof method to enhance operational efficiencies and service offerings.
The SerDes offering from KNiulink is engineered to meet the demanding requirements of bandwidth-heavy applications. It supports a variety of protocols including PCI Express, Rapid IO, SATA/SAS, JESD204, and USB interface standards. With support for up to 112G, this high-speed receiver-transceiver solution incorporates advanced techniques to optimize both power efficiency and signal integrity. It's specifically tailored for applications requiring reduced power consumption without sacrificing data throughput, making it an ideal choice for data centers, communication networks, and AI applications. The flexibility of the SerDes architecture allows it to be configured according to specific customer requirements, facilitating seamless integration into logic circuits and larger System on Chip (SoC) designs. This adaptability is complemented by cutting-edge CMOS technology which further enhances its performance metrics. SerDes is integral to the creation of high-performance virtual and physical environments, ensuring future-proof scalability with low latency and high reliability. Engineered for superior configurability and performance, KNiulink's SerDes ensures that high-speed communication can be managed effectively even in the most challenging environments, offering solutions that are tailored to bridge the gap between current needs and future technological developments.
UTTUNGA showcases a PCIe accelerator card powered by Calligo's TUNGA technology, designed to elevate server performance across various platforms, whether x86, ARM, or PowerPC. Integrating Posit arithmetic into server architectures, UTTUNGA optimizes memory utilization and computing power, especially for HPC and AI applications. This card leverages the RISC-V instruction set to execute arithmetic in specialized Posit configurations efficiently. UTTUNGA's design facilitates the seamless integration of existing scientific libraries, empowering servers to offload tasks seamlessly and adopt Posit-based computing without extensive code modification. The accelerator card includes programmable gates, aiding in custom function integrations crucial for dynamic workloads and data types. Through UTTUNGA, Calligo demonstrates the seamless blending of conventional and new-age computing technologies, providing a versatile solution for modern data centers seeking enhanced operational capacities.
InnoSilicon's 56G SerDes Solution provides a high-speed interface offering breathtaking transmission rates of up to 56Gbps per channel. Supporting both PAM-4 and NRZ modulation schemes, it adapts easily to various high-speed protocols to serve diverse applications like data center network systems and telecom infrastructure. This IP reinforces robust signal integrity and low power consumption, making it suitable for advanced ESD and BIST functionalities. Its flexible architecture meets modern network demands, ensuring future-proof customization opportunities.
The Multi-Protocol SerDes provided by Silicon Creations serves as an essential component for high-speed data interfaces across multiple industry protocols. This SerDes portfolio accommodates a vast array of protocols such as PCIe, JESD204, XAUI, and many more, facilitating broad compatibility with industry standards. Operating across 12nm to 180nm processes, these interfaces support data rates from 100 Mbps to an impressive 32.75 Gbps. Incorporating advanced features like programmable de-serialization widths and adaptive equalization, the Multi-Protocol SerDes ensures optimal signal integrity and performance even in demanding environments. The design includes jitter cleaner functions and employs low-latency optimized PMAs, delivering high precision and speed across various operational scenarios. This comprehensive adaptability ensures seamless integration into a wide range of applications from communications to high-performance computing. Supported by robust architectures, the SerDes enables enhanced efficiency and reliability, featuring low power consumption and reduced area overheads. With a commitment to customer satisfaction, Silicon Creations offers complete solutions through partnerships with leading controller vendors, cementing its products as high-value choices for modern electronic systems.
The 1394b PHY IP core provides comprehensive support for physical layer interfacing using the IEEE 1394b standard. It's integral for high-speed signal processing and synchronization in defense and aerospace applications, offering compatibility with standard PHY-Link interfaces. Providing robust performance in high-bandwidth environments, this core facilitates seamless integration with existing systems, supporting optimal data rates and ensuring precision in signal delivery. Its deployment enhances communication reliability and security essential for mission-critical systems. The core’s meticulous design caters to sectors requiring strict adherence to precise standards and consistent connectivity. It ensures straightforward interfacing while maintaining the integrity and fidelity of high-speed data exchanges across diverse system architectures.
Pacific MicroCHIP's DSER12G is a deserializer designed for high-speed data recovery, operating between 8.5 and 11.3Gb/s. It features robust clock recovery mechanisms and is integral to modern optical tranceivers, offering ultra-low power and exceptional input sensitivity.
Advinno Technologies' LVDS (Low-Voltage Differential Signaling) solution is designed to deliver guaranteed high-speed data transmission with low power consumption. Ideal for applications requiring efficient data transfer, LVDS offers robust performance characteristics that cater to demanding communication needs. These include reduced electromagnetic interference and high-speed data throughput, critical for sectors such as telecommunications and computer networks. Developed with precision, the LVDS excels in environments where minimal power use is crucial without compromising on transmission speed. Its low-voltage design ensures that systems remain energy efficient while delivering superior data integrity. These features make the LVDS indispensable in the design of consumer electronics, automotive systems, and industrial devices requiring dependable high-bandwidth communication pathways. Advinno's LVDS provides flexibility in integration with various electronic architectures, thereby facilitating its use across diverse projects requiring reliable signal conversion and data transmission. This product ensures that clients receive a stable and efficient component suitable for both current and future technological applications.
The Mil1394 OHCI Link Layer Controller delivers a robust hardware implementation, allowing efficient management of IEEE 1394b networks. Tailored for aerospace applications, this core utilizes the standard PHY-Link interface to integrate seamlessly with PCIe and embedded processor interfaces. Focusing on high-speed connectivity and network stability, this controller supports straightforward data management across extensive and complex data environments. It is engineered to maintain synchronization and communication integrity, crucial for real-time applications in aerospace communications. Its architecture supports intricately mapped DMA controllers and message chain engines that minimize data handling time, thereby enhancing throughput and reducing latency. The core’s adaptability makes it ideal for varied defense and aviation applications, where stable, rapid data exchange is paramount.