All IPs > Wireline Communication > Error Correction/Detection
In the realm of wireline communication, ensuring the integrity and reliability of data transmission is a critical concern. This is where Error Correction and Detection semiconductor IPs play a pivotal role. These IPs are designed to identify and rectify errors that occur during data transmission, thus enhancing the overall performance and reliability of wireline communication systems. Whether it involves correcting single-bit errors or detecting complex data discrepancies, these IPs are essential for maintaining the fidelity of data transmission.
Error Correction and Detection IPs utilize various sophisticated algorithms and techniques such as Reed-Solomon, Hamming Code, and Cyclic Redundancy Check (CRC). These technologies work by adding redundancy to the data being transmitted, allowing the receiver to detect errors and, in many cases, automatically correct them. This process not only protects data integrity but also ensures higher quality of service, reducing the need for retransmissions and improving network efficiency.
These semiconductor IP blocks are implemented in a wide array of applications including broadband networks, data centers, and telecommunication systems where uninterrupted and accurate data transmission is paramount. For engineers and developers, leveraging these IPs can significantly accelerate the development process of wireline systems by providing ready-to-integrate solutions that uphold communication standards.
In this category, you will find a vast selection of Error Correction and Detection semiconductor IPs suited for various applications. These IPs are available from leading suppliers, offering solutions that support multiple protocols and data rates. With these IPs, developers can ensure their wireline communication products are robust, reliable, and capable of delivering the highest levels of performance needed in today's data-driven world.
The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The ntLDPC_WiFi6 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes and is fully compliant with IEEE 802.11 n/ac/ax standard. The Quasi-Cyclic LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_WiFi6 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Normalized Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the IEEE 802.11 n/ac/ax Wi-Fi4, Wi-Fi5 and Wi-Fi 6 standards. The ntLDPC_WiFi6 encoder IP implements a 81-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder.
The ntRSC_DP1.4 IP core is compliant with Display Port 1.4 standard as published by Video Electronics Standards Association (VESA) for use in DSC (Display Stream Compression) technology. It is based on Reed-Solomon RS(254,250), 10 bit symbols, forward error correction code, where the codeword block consists of 250 information symbols and 4 RS parity symbols. The ntRSC_DP1.4 FEC IP Core ensures error resilient / glitch-free compressed video transport (DSC) to external displays. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The ntLDPC_G98042 (17664,14592) IP Core is defined in IEEE 802.3ca-2020, it is used by ITU-T G.9804.2-09.2021 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCΕ_G98042 encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer, when multiplied by the 14592 payload block, produces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1:4,6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_G98042 decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs. system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_G98042 decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers’ LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional syndrome check early termination (ET) criterion, to maintain identical error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. A top level architecture deployment wrapper allows to expand the parallelism degree of the decoder before synthesis, effec-tively implementing a trade-off between utilized area and throughput rate. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components at 128-bit parallel bus interface. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The ntLDPC_8023CA (17664,14592) IP Core is defined in IEEE 802.3ca-2020 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCE_8023CA encoder IP implements a 256-bit parallel systematic LDPC encoder. The Generator LDPC Matrix is calculated off-line, compressed and stored in ROM. It is partitioned to 12 layers and each layer when multiplied by the 14592 payload block pro-duces 256 parity bits. The multiplier architecture may be parameterized before synthesis to generate multiple multiplier instances [1 to 6], in order to effectively process multiple layers in parallel and improve the IP throughput rate. Shortened blocks are supported with granularity of 128-bit boundaries and 384 or 512 parity bits puncturing is also optionally supported. The ntLDPCD_8023CA decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm (OMS) or Layered Lambda-min Algorithm (LMIN). Selecting between the two algorithms presents a decoding performance vs system resources utilization trade-off. The OMS algorithm is chosen for this implementation, given the high code rate of the Parity Check Matrix (PCM). The ntLDPCD_8023CA decoder IP implements a 256-bit parallel systematic LDPC layered decoder. Each layer corresponds to Z=256 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZxZ shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Roa Logic's 8b/10 Decoder provides a complete implementation of the 8b10b encoding scheme formulated by Widmer and Franaszek. This decoder is essential in ensuring accurate data transmission across communication channels by performing error detection and correction functions that are critical for maintaining data integrity. The decoder efficiently identifies special comma sequences and manages the insertion and removal of these in the data stream to align data correctly. This effective error-handling feature is crucial for systems requiring reliable data integrity throughout transmission processes. Capable of maintaining high data rates while providing robust error-checking capabilities, the 8b/10 decoder module is suitable for deployment in a wide array of digital communication systems. Offering this under a non-commercial license reinforces Roa Logic's ethos of promoting open-access tools that aid in teaching and experimenting within digital design disciplines.
Convolutional FEC codes are very popular because of their powerful error correction capability and are especially suited for correcting random errors. The most effective decoding method for these codes is the soft decision Viterbi algorithm. ntVIT core is a high performance, fully configurable convolutional FEC core, comprised of a 1/N convolutional encoder, a variable code rate puncturer/depuncturer and a soft input Viterbi decoder. Depending on the application, the core can be configured for specific code parameters requirements. The highly configurable architecture makes it ideal for a wide range of applications. The convolutional encoder maps 1 input bit to N encoded bits, to generate a rate 1/N encoded bitstream. A puncturer can be optionally used to derive higher code rates from the 1/N mother code rate. On the encoder side, the puncturer deletes certain number of bits in the encoded data stream according to a user defined puncturing pattern which indicates the deleting bit positions. On the decoder side, the depuncturer inserts a-priori-known data at the positions and flags to the Viterbi decoder these bits positions as erasures. The Viterbi decoder uses a maximum-likelihood detection recursive process to cor-rect errors in the data stream. The Viterbi input data stream can be composed of hard or soft bits. Soft decision achieves a 2 to 3dB in-crease in coding gain over hard-decision decoding. Data can be received continuously or with gaps.
The nxLink Network Infrastructure solution is tailored for building and managing next-generation low-latency trading networks. By employing FPGA technology, nxLink emphasizes minimizing latencies and optimizing bandwidth management, crucial for high-demand trading environments. nxLink serves network operators by providing smart processing capabilities that keep up with wire-speed performance and nanosecond-scale latency, essential for maintaining a competitive trading edge. This solution is beneficial for both the telecommunications sector and financial institutions, aiming to enhance the reliability and performance of their network infrastructures. nxLink's smart bandwidth allocation and fair usage policies ensure equitable bandwidth distribution among services and improve the existing network capacity by up to 20%. A distinctive feature of nxLink is its ability to arbitrate fiber optics and wireless links, ensuring seamless data service even under adverse conditions such as weather disruptions. This flexibility in routing data over various paths enhances link reliability without compromising latency, which is crucial for ensuring continuous and predictable network performance in volatile trading environments.
AccelerComm presents the Polar encoding and decoding suite for the 3GPP NR, featuring a comprehensive chain that enables quick integration and minimizes additional developmental efforts. This advanced IP utilizes PC and CRC-aided SCL decoding methods to deliver uncompromising error correction performance, adeptly handling the intricacies of 5G applications.\n\nThe Polar IP supports an extensive range of block sizes, tightly integrating each component to optimize performance while reducing latency and resource use. Its flexibility is further highlighted by its highly configurable parameters, which allow users to tailor its implementation to specific performance demands and power efficiency expectations.\n\nBy offering support for prevalent FPGA platforms like AMD and Intel, alongside ASIC optimizations, this Polar solution is a versatile option for developers seeking robust and integral solutions for burgeoning 5G networks. With ease of integration and superior performance metrics, it remains a leading solution in comprehensive 5G data processing.
The ntLDPC_5GNR Base Graph Encoder IP Core is defined in 3GPP TS 38.212 standard document and it is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. The specification defines two sets of LDPC Base Graphs and their respective derived Parity Check Matrices. Each Base Graph can be combined with 8 sets of lifting sizes (Zc) in a total of 51 different lifting sizes. This way by using the 2 Base Graphs, the 5G NR specification defines up to 102 possible distinct LDPC modes of operation to select from, for optimum decoding performance, depending on target application code block size and code rate (using the additional rate matching module features). For Base Graph 1 we have LDPC(N=66xZc,K=22xZc) sized code blocks, while for Base Graph 2 we have LDPC(N=50xZc,K=[6,8,9,10]xZc) sized code blocks. The ntLDPCE_5GNR Encoder IP implements a multi-parallel systematic LDPC encoder. Parallelism depends on the selected lifting sizes subsets chosen for implementation. Shortened blocks are supported with granularity at lifting size Zc-bit boundaries. Customizable modes generation is also supported beyond the scope of the 5G-NR specification with features such as: “flat parity bits puncturing instead of Rate Matching Bit Selection”, “maintaining the first 2xZc payload bits instead of eliminating it before transmission”, etc. The ntLDPCD_5GNR decoder IP implements a maximum lifting size of Zc_MAX-bit parallel systematic LDPC layered decoder. Each layer corresponds to Zc_MAX expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity sub-matrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
The PCD03D Turbo Decoder is adept at handling multiple state decoding for standards such as DVB-RCS and IEEE 802.16 WiMAX. Its core design features an 8-state duobinary decoding structure, facilitating precise and quick signal deconstruction. Additionally, the optional inclusion of a 64-state Viterbi decoder enhances versatility and performance in various environments. This decoder is tailored for applications where agility and high data throughput are critical, making it an invaluable asset in wireless communication infrastructures. The decoder’s architecture supports expansive VHDL core integration, providing durable solutions across FPGA platforms.
Designed for advanced network diagnostics, the 10G Universal Network Probe enables comprehensive traffic monitoring and analysis across OTN and other high-capacity networks. This probe offers versatile compatibility, ensuring streamlined integration into existing infrastructure, a critical function for maintaining high-speed data transmission fidelity and efficiency.
The LDPC solution by AccelerComm is meticulously optimized for the 5G NR standard, ensuring superior efficiency and performance. This encoder and decoder IP triumphantly addresses the pivotal needs of the 5G network by combining maximal hardware efficiency with enhanced power efficiency. It is adeptly designed to fulfill the rigorous throughput and error correction targets outlined by 3GPP standards.\n\nIntended for integration into both FPGA and ASIC environments, the LDPC IP is highly configurable, providing numerous settings to cater to a broad array of applications. Its capability to support maximum data rates while minimizing latency makes it an indispensable element in advanced communication infrastructures.\n\nWith enhanced BLER performance and an innovative design that outstrips generic LDPC solutions, this implementation significantly reduces latency and resource utilization. Offering low power consumption and half the energy per bit compared to competitors, it provides a balanced approach to meeting both diverse operational demands and stringent power budgets.
ntRSD_UF core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length, maximum number of parity symbols as well as I/O data width, internal datapath and decoding engines parallelism. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD_UF core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The core is designed and optimized for applications that need very high throughput data rates. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
In channel coding redundancy is inserted in the transmitted information bit-stream. This redundant information is used in the decoder to eliminate the channel noise. The error correction capability of a FEC system strongly depends on the amount of redundancy as well as on the coding algorithm itself. TPCs perform well in the moderate to high SNRs because the effect of error floor is less. As TPCs have more advantage when a high rate code is used, they are suitable for commercial applications in wireless and satellite communications. The ntTPC Turbo Product Codec IP core is consisted of the Turbo Product Encoder (ntTPCe) and the Turbo Product Decoder (ntTPCd) blocks. The product code C is derived from two/three constituent codes, namely C1, C2 and optionally C3. The information data is encoded in two/three dimensions. Every row of C is a code of C2 and every column of C is a code of C1. When the third coding dimension is enabled, then there are C3 C1*C2 data planes. The ntTPC core supports both e-Hamming and Single Parity Codes as the constituent codes. The core also supports shortening of rows or columns of the product table, as well as turbo shortening. Shortening is a way of providing more powerful codes by removing information bits from the code. The ntTPCe core receives the information bits row by row from left to right and transmits the encoded bits in the same order. It consists of a row, column and 3D encoder. The ntTPCd decoder receives soft information from the channel in the 2’s complement number system and the input samples are received row by row from left to right. The implemented decoding algorithm computes the extrinsic information for every dimension C1, C2, C3 by iteratively decoding words that are near the soft-input word. An advanced scalable and parametric design approach produces custom design versions tailored to end customer applications design tradeoffs.
AccelerComm's High PHY Accelerators offer an impressive portfolio of IP accelerators tailored for 5G NR, enhancing O-RAN deployments with advanced signal processing capabilities. These accelerators emphasize maximum throughput and minimal power and latency, leveraging scalable technology for ASIC, FPGA, and SoC applications.\n\nCentral to these accelerators are patented high-performance signal processing algorithms, which enhance throughput significantly, making them crucial in scenarios demanding rapid data processing and low latency. The offering is ideal for improving the speed and efficiency of high-demand networks, reinforced by extensive research led by industry experts from Southampton University.\n\nMoreover, the accelerators encompass a wide variety of signal processing techniques such as LDPC and advanced equalization, to optimize the entire data transmission process. The result is a remarkable boost in spectral efficiency and overall network performance, making these accelerators indispensable for cutting-edge wireless technologies and their future-forward deployments.
The ntLDPC_DVBS2X IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2X decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the DVB-S2 and DVB-S2X standards. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2X encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. Actual encoding is performed as a three part recursive computation process, where row sums, checksums of all produced rows column-wise and finally transposed parity bit sums are calculated. The ntLDPC_DVBS2X decoder IP implements a 360-bit parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. The decoder IP permutes each block’s parity LLRs to become compatible with the layered decoding scheme and stores channel LLRs to processes them in layered format. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity submatrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit.
ntLDPC_SDAOCT IP implements a 5G-NR Base Graph 1 systematic Encoder/Decoder based on Quasi-Cyclic LDPC Codes (QC-LDPC), with lifting size Zc=384 and Information Block Size 8448 bits. The implementation is based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that it offers high throughput at low implementation complexity. The ntLDPCE_SDAOCT Encoder IP implements a systematic LDPC Zc=384 encoder. Input and Output may be selected to be 32-bit or 128-bits per clock cycle prior to synthesis, while internal operations are 384-bits parallel per clock cycle. Depending on code rate, the respective amount of parity bits are generated and the first 2xZc=768 payload bits are discarded. There are 5 code rate modes of operation available (8448,8448)-bypass, (9984,8448)-0.8462, (11136,8448)-0.7586, (12672,8448)-0.6667 and (16896,8448)-0.5. The ntLDPCD_SDAOCT Base Graph Decoder IP may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Min-Sum Algorithm (MS) or Layered Lambda-min Algorithm (LMIN). Variations of Layered MS available are Offset Min-Sum (OMS), Normalized Min-Sum (NMS), and Normalized Offset Min-Sum (NOMS). Selecting between these algorithms presents a decoding performance vs. system resources utilization trade-off. The ntLDPCD_SDAOCT decoder IP implements a Zc=384 parallel systematic LDPC layered decoder. Each layer corresponds to Zc=384 expanded rows of the original LDPC matrix. Each layer element corresponds to the active ZcxZc shifted identity submatrices within the layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder IP also features a powerful optional early termination (ET) criterion, to maintain practically equivalent error correction performance, while significantly increasing its throughput rate and/or reducing hardware cost. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI4 stream IF.
Innowitech Solutions offers a highly efficient Convolutional Encoder and Viterbi Decoder, a critical component in error-correction methodologies for digital communication systems. This product is designed to handle any polynomial configuration, making it versatile for various encoding and decoding requirements. This encoder-decoder pair enhances data transmission reliability by reducing errors caused during the communication process. The flexibility to adapt to multiple configurations without sacrificing performance is one of its standout features, allowing it to meet diverse industry needs effectively. The design is optimized for integration on FPGA platforms, particularly fitting for applications demanding high-speed data processing and low-latency operations. This makes it especially suitable for telecommunications and data-intensive industries, offering a reliable solution to maintain data integrity across complex networks.
The DVB-S2-LDPC-BCH system provides a formidable forward error correction platform crucial for satellite communication. Utilizing LDPC coupled with BCH codes, this IP ensures quasi-error-free operation, pushing system performance near the Shannon limit. Compliant with ETSI standards, it offers robust error correction capabilities with varied throughput rates, facilitated by its synthesizable Verilog model, making it adaptable for ASIC implementations.
The ntLDPC_Ghn IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPCD_Ghn decoder IP Core may optionally implement one of two approximations of the log-domain LDPC iterative decoding algorithm (Belief propagation) known as either Layered Offset Min-Sum Algorithm or Layered Lambda-min Algorithm. Selecting between the two algorithms presents a decoding performance .vs. system resources utilization trade-off. The core is highly reconfigurable and fully compliant to the ITU-T G.9960 G.hn standard. The ntLDPCE_Ghn encoder IP implements a 360-bit parallel systematic LDPC encoder. An off-line profiling Matlab script processes the original matrices and produces a set of constants that are associated with the matrix and hardcoded in the RTL encoder. The ntLDPCD_Ghn decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. A separate off-line profiling Matlab script is used to profile the layered matrices and resolve any possible memory access conflicts. Each layer corresponds to Z=[14, 80, 360, 60, 270, 48 or 216] expanded rows of the original LDPC matrix, depending on the mode selected expansion factor. Each layer element corresponds to the active ZxZ shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been executed. The decoder also IP features a powerful optional early termination (ET) criterion, to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control handshaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The nxFeed Market Data System is engineered to facilitate seamless market data processing, specifically crafted for environments requiring ultra-low latency. Utilizing FPGA technology, this feed handler optimizes data acquisition and delivery through its capability to decode and normalize high-frequency exchange feeds efficiently. The FPGA-based design makes the nxFeed system inherently faster, significantly cutting down the processing time typically associated with market data handling. At its core, nxFeed is designed for electronic trading applications that necessitate real-time data processing. It provides a streamlined, normalized API that allows easy integration with existing trading applications or in-house ticker plants. By processing market data through NXFeed, trading firms benefit from reduced server loads and improved application performance, which is crucial for high-frequency trading. The system also supports A/B feed arbitration and resynchronizes the exchange feeds, maintaining data consistency across different venues. This feature is vital for ensuring traders can react to market changes as fast and accurately as possible. The nxFeed's robust features and scalable architecture make it an indispensable tool for trading institutions aiming to enhance their market data strategies.
ntRSD core implements a time-domain Reed-Solomon decoding algorithm. The core is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSD core supports erasure decoding thus doubling its error correction capability. The core also supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The UDP/IP Ethernet communication core is expertly crafted to enable FPGAs to interact via Ethernet utilizing the UDP protocol. Designed for both Intel and AMD FPGA architectures, this IP core allows FPGA subsystems to communicate efficiently at full wire speed of 1 Gbit/sec, also supporting slower data rates of 100 Mbit/sec and 10 Mbit/sec. It offers a straightforward interface to the user logic and supports MII, RMII, GMII, and RGMII media protocols. With the capacity to handle complete UDP, IPv4, and Ethernet layer processing, this core ensures robust data transfer while offering features like automatic ARP reply generation and header pass-through mode for individualized packet field management. This functionality ensures efficient and seamless integration into a wide array of FPGA-based designs, reducing complexity and design time. Targeted for applications in telecommunications and network systems, this IP core is an ideal candidate for projects requiring high-speed, dependable communication channels. The design's energy efficiency and minimal FPGA resource usage underpin its viability for commercial and industrial deployment.
Cyclic Design's G13 and G13X IPs are crafted for 512-byte correction blocks, suited for NAND devices with 2KB and 4KB pages. Transitioning from traditional single bit correction using Hamming codes, these IPs support higher bit corrections essential as NAND technologies advance. The G13 IP offers a modular, customizable drop-in upgrade enhancing existing controller architectures with minimal investment, ensuring compatibility with both existing hardware and software.
ntRSC_IESS core is a highly integrated solution implementing a time-domain Reed-Solomon Forward Error Correction algorithm. The core supports several programming features including codeword size, error threshold, number of parity bytes, reverse or forward order of the output, mode of operation (encode, decode or pass-through), shortened code support, erasures or error only decoding. Very low latency, high speed, simple interfacing and programmability make this core ideal for many applications including Intelsat IESS-308, DTV, DBS, ADSL, Satellite Communications, High performance modems and networks.
The FCM2801-BD Power Amplifier from Falcomm represents a pinnacle in amplification technology, engineered to excel in ultra-efficient energy use. This power amplifier operates at a center frequency of 28 GHz, making it well-suited for high-speed wireless communications and next-generation telecom services. Its design not only prioritizes power efficiency but also durability and performance in demanding environments. The FCM2801-BD offers considerable improvements in power usage efficiency, aligning with modern demands for low-energy-consumption solutions. Thus, it caters to both commercial and industrial applications that require robust yet efficient power amplification. This product is fundamental in reducing operational costs for telecommunication providers and in advancing the performance of consumer electronics. Its precision engineering ensures it can withstand and operate efficiently in a wide range of conditions, cementing its place as a core component in innovative telecom solutions.
hellaPHY Positioning Solution is an advanced edge-based software that significantly enhances cellular positioning capabilities by leveraging 5G and existing LTE networks. This revolutionary solution provides accurate indoor and outdoor location services with remarkable efficiency, outperforming GNSS in scenarios such as indoor environments or dense urban areas. By using the sparsest PRS standards from 3GPP, it achieves high precision while maintaining extremely low power and data utilization, making it ideal for massive IoT deployments. The hellaPHY technology allows devices to calculate their location autonomously without relying on external servers, which safeguards the privacy of the users. The software's lightweight design ensures it can be integrated into the baseband MCU or application processors, offering seamless compatibility with existing hardware ecosystems. It supports rapid deployment through an API that facilitates easy integration, as well as Over-The-Air updates, which enable continuous performance improvements. With its capability to operate efficiently on the cutting edge of cellular standards, hellaPHY provides a compelling cost-effective alternative to traditional GPS and similar technologies. Additionally, its design ensures high spectral efficiency, reducing strain on network resources by utilizing minimal data transmission, thus supporting a wide range of emerging applications from industrial to consumer IoT solutions.
StreamDSP's Interlaken PHY solution is designed specifically for bridging high-bandwidth data throughput with efficient latency management, providing a highly reliable interconnect option between networking or storage devices and FPGAs. This solution facilitates robust and scalable connectivity for intensive computational tasks, capable of adapting to various data widths and system configurations with aplomb. The Interlaken PHY core offers built-in support for high-flexibility lane designs, along with features like channel bonding and dynamic lane reconfiguration. Error correction and lane management mechanisms further ensure data integrity and smooth operation even in the most demanding environments. Combining these capabilities with ease of integration into existing FPGA frameworks highlights its role as a pivotal component in data-centric operations across the tech industry.
The D-Series DDR5/4/3 Controller is designed to excel in latency, bandwidth, and area optimization. It connects to the PHY via a standard DFI 5.0 interface, facilitating seamless integration. This memory controller includes advanced scheduling technologies, ECC support, and multi-channel capabilities. Incorporating over 300 custom features available for customization, it enables significant flexibility and differentiation in memory system design. The D-Series DDR Controller is engineered to ensure robust performance in high-bandwidth requirements, making it suitable for diverse computing environments.
ntRSE core implements the Reed Solomon encoding algorithm and is parameterized in terms of bits per symbol, maximum codeword length and maximum number of parity symbols. It also supports varying on the fly shortened codes. Therefore any desirable code-rate can be easily achieved rendering the decoder ideal for fully adaptive FEC applications. ntRSE core supports continuous or burst decoding. The implementation is very low latency, high speed with a simple interface for easy integration in SoC applications.
The G15 IP is optimized for 2KB blocks, enhancing NAND controllers with a support system for higher ECC levels, simple integration across a variety of applications, and scalability for future technologies. Capable of reducing development costs while allowing customers to modify the source to fit specific requirements, it integrates seamlessly into established designs while also offering advanced ECC options.
The IPM-BCH from IP Maker is built on the BCH error-correcting code algorithm to manage NAND flash memory's inherent limitations regarding write cycles. This IP core is engineered to enhance data validity and longevity by correcting and detecting failed operations. Fully configurable, it is adept for use across various FPGA and SoC applications, making it versatile for different technological environments. BCH Encoding/Decoding capabilities are critical for ensuring the data integrity of NAND flash-based storage solutions. The IPM-BCH core can be tailored to specific project needs, balancing performance with resource utilization. Its implementation offers significant reductions in latency or might be optimized for minimal footprint, providing flexibility depending on design requirements. This technology helps extend NAND flash memory's utility within data storage applications by protecting data through robust ECC methodologies. Such implementations shorten the time-to-market by providing pre-verified, high-performance error correction, all while maintaining data accuracy through effective Galois field operations.
The ntDVBS2_FEC transmitter and receiver IPs, each instantiate an outer BCH and inner LDPC concatenated pair of encoders and decoders respectively. The Bose, Chaudhuri, and Hocquenghem (BCH) codes are the largest category of the powerful error-correction cyclic codes and belong to the block codes that are a generalization of the Hamming codes for multiple-error corrections. The Low Density Parity Check (LDPC) codes are powerful, capacity approaching channel codes and have exceptional error correction capabilities. The high degree of parallelism that they offer enables efficient, high throughput hardware architectures. The concatenation of these two error correction algorithms enable performance well close to the Shannon limit. The ntBCH_DVBS2 encoder performs BCH encoding to payload frames by appending calculated parity bits at the end of each frame. The ntBCH_DVBS2 decoder finds the error locations within a received frame, tries to correct them and indicates a successful or failed decoding procedure. The ntLDPC_DVBS2 IP Core is based on an implementation of QC-LDPC Quasi-Cyclic LDPC Codes. These LDPC codes are based on block-structured LDPC codes with circular block matrices. The entire parity check matrix can be partitioned into an array of block matrices; each block matrix is either a zero matrix or a right cyclic shift of an identity matrix. The parity check matrix designed in this way can be conveniently represented by a base matrix represented by cyclic shifts. The main advantage of this feature is that they offer high throughput at low implementation complexity. The ntLDPC_DVBS2 encoder IP implements a 360-bit parallel systematic LDPC IRA encoder. An off-line profiling Matlab script processes the original IRA matrices and produces a set of constants, associated with the matrix and hardcoded in the RTL encoder. Encoding is performed as a three part recursive computation process, where row sums, checksums of all rows column-wise and parity bit sums are calculated. The ntLDPC_DVBS2 decoder IP implements an approximation of the log-domain LDPC iterative decoding algorithm (Belief propagation), known as Layered Lambda-min2 Algorithm. The core is highly reconfigurable in terms of area, throughput and error correction performance trade-offs and is fully compliant to the DVB-S2 standard. Two highly complex off-line preprocessing series of procedures are performed to optimize the DVB LDPC parity check matrices to enable efficient RTL implementation. The ntLDPC_DVBS2 decoder IP implements a 360-LLR parallel systematic LDPC layered decoder. Two separate off-line profiling Matlab series of scripts are used to (a) process the original IRA matrices and produce the layered matrices equivalents (b) resolve any possible conflicts produced by the layered transformation. Each layer corresponds to 360 expanded rows of the original LDPC matrix. Each layer element corresponds to the active 360x360 shifted identity sub-matrices, within a layer. Each layer element is shifted accordingly and processed by the parallel decoding datapath unit, in order to update the layers LLR estimates and extrinsic information iteratively until the required number of decoding iterations has been run. The decoder also IP features two powerful optional early termination (ET) criteria (convergence and parity check), to maintain practically the same error correction performance, while significantly increasing its throughput rate. Additionally it reports how many decoding iterations have been performed when ET is activated, for system performance observation and calibration purposes. Finally a simple, yet robust, flow control hand-shaking mechanism is included in both IPs, which is used to communicate the IPs availability to adjacent system components. This logic is easily portable into any communication protocol, like AXI.
The DVB-C Demodulator is a specialized core designed for decoding digital video broadcast signals, specifically tailored toward cable systems. Compliant with the DVB-C and J83 modulation standards, this demodulator is crucial for cable networks aiming to provide high-quality digital video and broadband data services. With integrated FEC (Forward Error Correction) capabilities, this core enhances signal quality and reliability, ensuring that subscribers receive superior service. It's optimized for modern cable networks, where efficient data transmission and minimal error rates are paramount. The DVB-C Demodulator plays a vital role in cable systems, ensuring consistent and accurate decoding of broadcast signals. Its compatibility with various cable configurations and modulation standards makes it a versatile and dependable choice for service providers who aim to uphold high standards of cable and digital communication.
The Complete 5G NR Physical Layer from AccelerComm offers a robust solution for high-performance networks, whether terrestrial or satellite-based. This full-featured physical layer is versatile, supporting various specialized applications, including O-RAN, satellite, and small-cell solutions. By integrating both high and low PHY components, it delivers optimal performance, power, and area efficiency. Boasting innovative signal processing technologies, the product ensures top-tier link performance, with a strong focus on meeting the needs of demanding network environments.\n\nThe solution's adaptability allows it to be implemented as licensable IP across multiple platforms, including ARM software, FPGA, and ASIC-ready cores. This flexibility is pivotal for diverse deployment scenarios, making it an ideal choice for developers seeking to reduce project risks through comprehensive pre-integration testing on COTS development boards.\n\nFurthermore, the product's inclusion of AccelerComm's proprietary 5G acceleration technologies enables users to achieve game-changing power and performance metrics in their 5G networks. Whether for LEO satellites or dense urban networks, this physical layer solution stands out for its capacity to address unique challenges faced by modern communication infrastructures, maximizing both spectral efficiency and global network reach.
The PCE04I Inmarsat Turbo Encoder is engineered to optimize data encoding standards within satellite communications. Leveraging advanced state management, it enhances data throughput by utilizing a 16-state encoding architecture. This sophisticated development enables efficient signal processing, pivotal for high-stakes communication workflows. Furthermore, the PCE04I is adaptable across multiple frameworks, catering to diverse industry requirements. Innovation is at the forefront with the option of integrating additional state Viterbi decoders, tailoring performance to specific needs and bolstering reliability in communications.
The G14 and G14X IP series optimizes for 1KB correction blocks, designed to transition with MLC flash using 8KB page sizes. The IP supports both current MLC needs and future SLC requirements, providing a bridge as technologies shift. Offering flexibility in block size from 2 to 1800 bytes and customizable for latency and bandwidth needs, this IP ensures robust error correction including ECC4 and ECC8, vital for leveraging new SLC flash generations.
The nxAccess Trading Engine is a state-of-the-art FPGA-powered trading solution that offers comprehensive market access capabilities. Its design capitalizes on the powerful synergy of hardware-driven agility and software friendliness, making high-frequency trading more efficient through rapid data handling. This dynamic engine is tailored for market makers, high-frequency traders, and arbitrageurs, enabling them to execute strategies with unparalleled speed and precision. nxAccess leverages FPGA technology to provide ultra-low latency performance in processing market data and executing trades. The trading engine allows for the preloading of orders within hardware, which are then immediately triggered and updated with incoming market data. This ensures that traders are always executing at the most opportune moments, capitalizing on market inefficiencies faster than conventional methods. One of nxAccess's standout features is its pattern matcher, which decodes raw market data to extract key trading signals. This capability further reduces latency by bypassing traditional feed handlers, enabling quicker reactions to market changes. The engine supports varied trading strategies, providing flexibility in operations as well as the deterministic performance that is critical for maintaining a competitive edge.
The G12 BCH IP is tailored for 256-byte correction blocks and supports up to 16 bits of error correction, suiting niche applications with smaller block sizes. This design supports dynamic block sizes ranging from 2 to 450 bytes and allows optimization by specifying a maximum ECC level via parameters. The IP supports various configurations and is available in Verilog source with SystemVerilog Assertions.
TurboConcept's TC1000/2000/3000 series is an array of meticulously designed LDPC and Turbo Product codes intended to enhance data communication systems with superior error correction capabilities. These IP cores are engineered to support high throughput and low latency, crucial for advanced data communication applications. The series is versatile and accommodates a wide range of coding options, offering flexibility and adaptability in different technological environments. It is highly effective for use in applications ranging from broadband wireless to satellite communications, where data integrity and performance consistency are paramount. The inherent flexibility in their implementation allows easy adaptation to the evolving demands of digital communication networks.
TurboConcept's 4G multi-mode CTC decoder is a versatile IP core designed to meet the broad requirements of 4G mobile networks. It expertly handles various code rates and block sizes, making it a flexible solution for communication systems that demand reliable error correction under multiple modulation schemes. The decoder’s architecture supports high-speed data processing, essential for the fast-paced operations typical in 4G environments. Additionally, it is equipped to provide seamless transition and compatibility with legacy systems, ensuring network consistency and reliability.
The 5G LDPC IP core from TurboConcept is engineered to meet the stringent demands of modern wireless communications. It provides robust error correction capabilities pivotal for next-generation 5G networks. This IP core is crafted to handle the increased data bandwidth of 5G, ensuring reliable and efficient data transmission. It is tailored for 5G NR (New Radio) systems, delivering enhanced spectral efficiency and higher throughput. With its advanced implementation for both FPGA and ASIC, the 5G LDPC core supports rapid error correction which is critical for maintaining high data rates and low latency in various communication environments.
TurboConcept's 5G Polar encoder/decoder core serves as a cornerstone for secure and reliable communication in 5G networks. This IP solution plays a crucial role in data transmission security, employing polar coding techniques known for their capacity-approaching error correction performance. The 5G Polar core is optimized for use in 5G NR systems, offering superior performance in handling varying channel conditions. By providing robust performance under adverse conditions, it ensures that data integrity is maintained without sacrificing speed or efficiency. Designed for both FPGA and ASIC platforms, it guarantees flexibility in deployment, catering to diverse hardware requirements.
The TCP/IP Offload Engine from Design Gateway is crafted for high-throughput, low-latency network communication. By offloading TCP/IP stack operations from the CPU, this engine dedicates FPGA resources for processing networking protocols, ensuring enhanced system efficiency. This IP core achieves pure hardware acceleration, facilitating high-rate data transfers with minimal CPU intervention. It supports various connection speeds and is adaptable to different FPGA platforms, making it a versatile choice for high-speed networking solutions. Ideal for data centers, content delivery networks, and financial trading systems where latency and throughput are critical, the TCP/IP Offload Engine provides reliable network performance, unburdening host CPUs from intensive networking processes.
The HDR Camera ISP by BTREE is designed to handle high dynamic range imaging, enabling cameras to capture scenes with varying light levels effectively. This sophisticated Image Signal Processor (ISP) integrates extensive features to enhance image quality, such as color correction, noise reduction, and exposure control. Designed for applications requiring superior image fidelity, it is ideal for devices ranging from high-end digital cameras to mobile devices. Leveraging advanced algorithms, the ISP optimizes every pixel to ensure clarity and detail across diverse lighting conditions. This IP enriches the capture process by delivering bright and vibrant images, even in challenging environments, ensuring that both shadows and highlights retain detail. The robust HDR processing pipeline is fine-tuned to manage real-time processing demands without compromising performance. Moreover, with a focus on low power consumption and optimal performance, the Camera ISP for HDR is structured to support modern multimedia applications. Its integration ensures seamless adaptability to various camera modules while maintaining efficiency in energy usage, making it indispensable for manufacturers aiming to deliver distinguished imaging experiences.
The Stellar Packet Classification Platform for FPGAs provides a sophisticated packet processing solution capable of handling ultra-high-speed search operations. Its architecture supports advanced functions through extensive lookup rules based on complex Access Control Lists (ACL) and Longest Prefix Match (LPM), making it essential for advanced networking tasks requiring scalability and high performance.\n\nDesigned to manage numerous and varied network rules, Stellar supports performance requirements ranging from 25 Gbps to over 1 Tbps. It features the ability to execute hundreds of millions of lookups per second, catering to the demands for high-speed data forwarding and network security operations. Its design allows for seamless integration into existing network infrastructure, optimizing processes like IPv4/6 routing, firewall management, and anti-DDoS systems.\n\nIts scalable architecture enables real-time updates and modifications, supporting high-reliability systems that require minimal downtime and maximal efficiency. Stellar's capabilities are integral to maintaining robust network infrastructures, preventing intrusions, and ensuring secure data flow across complex networks. The platform's adaptability makes it a versatile component in telecommunications, data centers, and enterprise networking environments.
The Bit Chains IPs support diverse communication protocols offering flexible bandwidth and modulation options. Designed to handle both short and long frames, these chains support LTE categories, making them adaptable for varied network conditions and enhancements requiring customizable solutions.
The LDPC (Low-Density Parity-Check) Encoder/Decoder is an advanced error correction solution designed to enhance data reliability. By encoding data into codes that can be efficiently decoded to recover from errors, this technology significantly improves the robustness and reliability of data communication systems. It is particularly useful in scenarios involving high data rates and long transmission distances. This encoder/decoder stands out due to its ability to handle complex data correction tasks while maintaining low computational overhead. Its design is optimized for incorporation into ASIC and FPGA environments, making it a practical choice for diverse applications, including telecommunications and data storage solutions. The LDPC technology's strength lies in its high correction capability, which effectively reduces the error rate across various channel conditions. LDPC Encoder/Decoder ensures high performance by employing advanced algorithms that maximize data throughput without compromising data integrity. Its integration into current communication systems provides a significant boost in reliability and efficiency, making it indispensable in modern digital transmission systems where signal clarity and accuracy are critical.
A versatile decoder, the logiJPGD facilitates simultaneous decoding of up to four HD video channels adhering to the JPEG standard Baseline DCT. It is ideal for applications in video over IP, ensuring precise decompression across AMD's All Programmable SoC and FPGA platforms.<br><br>Its ability to manage multiple video streams efficiently makes it a preferred choice in broadcasting, surveillance, and any field requiring robust video data handling. With its emphasis on maintaining video integrity across multiple channels, the logiJPGD supports detailed and accurate video reproduction.<br><br>This IP core positions itself as a cornerstone for multi-stream video processing, offering exceptional decompression capabilities tailored to modern digital video applications. Its integration into existing systems facilitates enhanced functionality without compromising system performance.
BTREE's 3DNR Image Processing IP is essential for enhancing image clarity through advanced three-dimensional noise reduction techniques. This technology is integral in removing visual noise while preserving important details in images or video streams. The platform's sophisticated algorithms analyze temporal and spatial information to distinguish noise from the actual signal, significantly improving visual quality. Primarily utilized in video applications, this IP is beneficial in situations with low-light conditions or where high frame rates are necessary. With the ability to operate efficiently in real-time processing, BTREE's 3DNR ensures consistency and clarity in each frame, making it suitable for security systems, video conferencing technologies, and mobile computing devices. Efficiency is a core advantage of this IP, as it focuses on delivering high-quality outputs with minimal energy use, supporting a wide range of camera and digital media applications. Its implementation not only reduces motion distortion but also enhances the overall image performance, enabling sharper and clearer visual displays.
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