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All IPs > Other > Other > TileLink Target

TileLink Target

From Agnisys, inc.

Description

TileLink is a chip-scale connection standard that enables many masters to have synchronised memory mapped access to memory and other slave devices. TileLink is intended for use in a System On-Chip (SoC) to connect general-purpose multiprocessors, co-processors, accelerators, DMA engines, and simple or complicated devices, utilising a fast, scalable interconnect that provides both low latency and high-throughput transfers.

Deliverables
Soft IP
  • Synthesizable RTL
  • Verilog integration testbench
  • Datasheet
  • Hardware user guide
  • IDesignSpec tool to configure
Features
  • TL-UL both 1.7 and 1.8 standard
  • TL-UL: 'PutFullData', 'PutPartialData', 'Get', 'AccessAck', 'AccessAckData' and Error response
  • All three messages above, with and without latency transaction
Tech Specs
Class Value
Categories Other > Other
Availability All Countries & Regions
Applications
  • AI
  • Mobile
  • Autonomous Technology
  • Research & Science and Engineering Services
  • Military & Aerospace
  • Information & Technology
  • Semiconductor Industry
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