The SMS OC-3/12 Transceiver Core represents a pivotal advancement in SONET/SDH transceiver technology, designed to adhere to stringent jitter specifications using a novel deep sub-micron single poly CMOS design. The transceiver incorporates a fully integrated architecture, which features internal clock synthesis, precise clock recovery, wave shaping, and a low-jitter LVPECL interface. Its design complies with all relevant ANSI, Bellcore, and ITU jitter specifications, proving its applicability for use in complex multi-port customer SOC designs. This transceiver is adept at handling multiple integration scenarios on a single IC, making it suitable for sophisticated System-On-Chip applications. Advanced proprietary signal processing techniques embedded in the transceiver ensure effective clock recovery by providing on-chip noise filtering, a significant enhancement over existing solutions. As designed for multiple integration, it supports various selectable reference frequencies, boasting a customized CMOS architecture to precisely control jitter transfer, tolerance, and generation.
