All IPs > Interface Controller & PHY > D2D
Device-to-Device (D2D) communication is a critical component in modern electronics, enabling direct interaction between devices without intermediary network infrastructure. Within our Interface Controller & PHY category, the D2D segment offers specialized semiconductor IPs designed to streamline and enhance these direct connections. These IPs are indispensable in creating an efficient communication link that can handle the increasing data demands seen in consumer electronics, automotive systems, and IoT devices.
Our D2D semiconductor IPs consist of essential building blocks such as interface controllers and Physical Layer (PHY) IP cores. These components are engineered to facilitate seamless communication between devices, whether it be for transferring data, synchronizing functions, or sharing resources in real-time. By leveraging these IPs, manufacturers can achieve low latency, high-speed data transfer, and robust connectivity, making these components suitable for applications requiring precise and rapid interaction.
Incorporating D2D IPs into your design allows for efficient use of bandwidth and power, critical factors in battery-operated or compact devices. The versatility of these semiconductor IPs makes them a popular choice in developing smart home devices, wearables, and vehicle infotainment systems, where direct and reliable device-to-device communication is paramount. These IPs also help minimize reliance on external network structures, providing a more secure and localized network environment.
The D2D interface controller and PHY IPs in our collection are developed to cater to the demanding needs of modern technological solutions. Whether you are designing a new IoT ecosystem or enhancing an automobile's connectivity suite, selecting the right D2D IP core can significantly impact your product’s performance and user experience. Explore our offerings to find the IP solutions that best align with your innovation goals, ensuring your devices communicate effectively and efficiently.
Panmnesia's CXL 3.1 Switch is a pivotal component in networking a vast array of CXL-enabled devices, setting the bar with its exceptional scalability and diverse connectivity. The switch supports seamless integration of hundreds of devices including memory, CPUs, and accelerators, facilitating flexible, high-performance configurations suited to demanding applications in data centers and beyond. Panmnesia's design enables easy scalability and efficient memory node expansion, reflecting their dedication to resource-efficient memory management. The CXL 3.1 Switch features a robust architecture that supports a wide array of network topologies, allowing for multi-level switching and complex node configurations. Its design addresses the unique challenges of composable server architecture, enabling fine-grained resource allocation. The switch leverages Panmnesia's proprietary CXL technology, underpinning its ability to perform management tasks across integrated memory spaces with minimal overhead, crucial for achieving high-speed, low-latency data exchange. Incorporating CXL standards, it is fully compatible with both legacy and next-generation devices, ensuring broad interoperability. The architecture allows servers to tailor resource availability by employing type-specific CXL features, such as port-based routing and multi-level switching. These features empower operators with the tools to configure extensive networks of diverse devices efficiently, thereby maximizing data center performance while minimizing costs.
The CT25205 is a sophisticated digital controller designed for 10BASE-T1S Ethernet communications. Compatible with IEEE 802.3cg, it integrates the PMA, PCS, and PLCA Reconciliation sublayers, making it highly suitable for standard cells and FPGA systems. This synthesizable IP core supports seamless integration into any standard IEEE CSMA/CD Clause 4 Ethernet MAC via MII, which enhances its versatility for a multitude of applications. Its embedded PLCA RS uniquely allows existing MAC implementations to adopt advanced PLCA capabilities effortlessly, ensuring an increase in functionality without hardware overhauls. In conjunction with other Canova Tech IPs, such as the CT25208 MAC controller and CT25210 topology discovery IP, it provides a complete solution for implementing 10BASE-T1S within Zonal Gateways System on Chips (SoCs) and microcontrollers. The amalgamation of these components offers a streamlined approach to developing efficient network communication protocols, paving the way for innovative uses in industrial and automotive sectors where reliable data transmission is critical. This IP is especially adept at working alongside standard OPEN Alliance 10BASE-T1S PMD interfaces, reinforcing its compatibility with established industry protocols. For those developing multi-drop Ethernet solutions, the CT25205 stands as a premier choice. Its design, which ensures adherence to IEEE standards while promoting enhanced reliability and performance, makes it an attractive option for a range of applications, from simplifying connectivity in industrial setups to fortifying communications in vehicular networks, underscoring Canova Tech’s commitment to technological advancement and innovation.
MAXVY UCIe VIP , a state-of-the-art solution that offers a comprehensive set of features and capabilities to ensure the quality and performance of your UCIe designs. MAXVY UCIe VIP is fully compliant with UCIe Specification version 1.0 and supports all the layers of the UCIe stack, such as FDI, RDI, LogPHY, PCIe, and CXL protocols. MAXVY UCIe VIP is also very user-friendly and flexible, with simple APIs, easy integrations, and configurable parameters. You can easily customize and control the UCIe functionality according to your needs. MAXVY UCIe VIP also provides a rich set of verification capabilities, such as protocol checks, functional coverage, traffic generation, error injection, and debug tools. You can easily monitor, detect, and report any issues or violations in your UCIe designs. MAXVY UCIe VIP is compatible with the industry-standard Universal Verification Methodology (UVM) and supports all leading simulators. With MAXVY UCIe VIP, very flexible for unit level testing, you can achieve faster verification closure and higher quality of your UCIe designs.
Eliyan's NuLink Die-to-Die PHY technology represents a significant advancement in chiplet interconnect solutions. Designed for standard packaging, this innovative PHY IP delivers robust high-performance with low power consumption, a balance that is crucial for modern semiconductor designs. The NuLink PHY supports multiple industry standards, including the Universal Chiplet Interface Express (UCIe) and Bunch of Wires (BoW), ensuring it can cater to a wide range of applications. A standout feature of the NuLink PHY is its simultaneous bidirectional (SBD) signaling capability, which allows data to be sent and received over the same wire at the same time, effectively doubling bandwidth. This makes it an ideal solution for data-intensive applications such as AI training and inference, particularly those requiring ultra-low latency and high reliability. The technology is also adaptable for different substrates, including both silicon and organic, offering designers flexibility in their packaging approaches. NuLink's architecture stems from extensive industry insights and is informed by Eliyan’s commitment to innovation. The platform provides a power-efficient and cost-effective alternative to traditional advanced packaging solutions. It achieves interposer-like performance metrics without the complexity and cost associated with such methods, enabling operational efficiency and reduced time-to-market for new semiconductor products.
The ePHY-5616 is a high-performance SerDes solution from eTopus, designed for versatile use across enterprise, data center, and 5G applications. Operating efficiently at data rates from 1 to 56 Gbps, this product exploits advanced DSP techniques for superior signal integrity and robustness. It accommodates wide insertion loss ranges of 10dB to over 35dB, thus ensuring reliable performance in challenging communication environments. Its architecture supports direct optical drives and quad/octal configurations, making it ideal for network interface cards, routers, and high-speed switches in a data center setup. The embedded DSP architecture is developed with eTopus's proprietary algorithms, which enable rapid SerDes tuning and performance optimization. The ePHY-5616 is also characterized by its low Bit Error Rate (BER), ensuring data reliability and integrity. Moreover, it supports multiple protocols, including Ethernet and PCIe, enhancing its integration potential in modern broadband networks.
The Die-to-Die Interconnect from SkyeChip delivers a streamlined solution for high-speed data transfer between dies, ensuring minimal power overhead while maintaining high performance. Compliant with the Universal Chiplet Interconnect Express (UCIe) 2.0 specification, this IP supports transfer rates up to 32 Gbps per pin and integrates easily into diverse packaging technologies. Built-in tests and self-repair functions further enhance reliability and yield in multi-die systems.
The logiSPI facilitates bridging between Serial Peripheral Interface (SPI) equipment and AMD's FPGA and Zynq 7000 All Programmable SoC using the AXI4 protocol. This bridge allows seamless communication across board-level interconnects for diverse microcontroller and FPGA combinations.<br><br>Highly useful in a myriad of electronic system designs, the logiSPI supports modular interfacing between devices, significantly enhancing operational versatility and easing development complexity. It finds use in embedded systems, IoT solutions, and intricate control circuits over wide-ranging applications.<br><br>The logiSPI core optimizes inter-chip communication, providing flexibility and efficiency necessary for sophisticated designs that require reliable interaction between individual components, enhancing overall system synergy and performance.
The ARINC 818 Streaming Core is designed to facilitate real-time conversion from pixel buses to ARINC 818 formatted Fibre Channel streams and vice versa. This core is optimized for aerospace applications where precise, high-speed streaming and data formatting are crucial. With this capability, it supports seamless integration into advanced aerospace systems like avionics displays. Capable of converting data efficiently, it alleviates the complexities associated with handling video streams in real-time, thereby ensuring that transmissions meet the high demands of military and aerospace objectives. By maintaining a strong focus on data integrity, the core helps achieve superior performance in data transmission, ensuring that critical systems maintain optimal operational readiness. The engineering behind this core provides an efficient bridge between different data formats, enabling robust communications across complex networks. The ARINC 818 Streaming Core reflects advanced design methodologies tailored for rigorous requirements, bringing about enhanced reliability and efficiency to the systems it serves.
eTopus's ePHY-11207 stands out in their SerDes lineup by achieving data rates up to 112 Gbps, a leap forward for scenarios demanding ultra-high bandwidth and low-latency communication. Constructed on a 7nm platform, this product is tailored for state-of-the-art applications in both enterprise and advanced data center environments. The architecture of the ePHY-11207 is conducive to handling extensive insertion loss ranges and high-sensitivity demands typical of contemporary optical and copper interconnects. Its adaptability is further enhanced by embedded proprietary DSP algorithms that permit fine-tuning of performance in sub-millisecond timeframes, a feature that assures operational stability even amidst jitter-inducing environments. In addition to backing numerous protocols such as Ethernet and PCIe, the ePHY-11207's low BER and extensive diagnostic capabilities make it a prime candidate for rapid deployment in high-density network settings. Such versatility not only supports robust infrastructure but also enhances overall throughput efficiency.
YouSerdes by Brite Semiconductor is a versatile multi-rate serializer/deserializer solution, capable of handling data transfer speeds from 2.5Gbps to 32Gbps. It is known for its superior performance, compact area usage, and power efficiency among its peers. The IP is designed to accommodate a wide array of interfaces, including but not limited to PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, and various SATA and XAUI implementations. Its architecture supports dynamic reconfiguration, allowing flexible channel arrangements and optimal resource utilization. The core design of YouSerdes optimizes the use of high-performance physical layers to ensure reliable data throughput across different applications. The solution features internal clock generation that eliminates the need for additional components, simplifying design efforts and reducing associated costs. Moreover, the architecture supports diverse protocols while maintaining compliance with industry standards, ensuring broad applicability. Designed for robust applications, YouSerdes is suitable for implementations in data centers, enterprise networks, and high-speed computing environments where efficiency and performance cannot be compromised. Its ability to seamlessly interface with multiple protocols in a single design makes it an attractive choice for multi-functional devices requiring adaptive data processing capabilities.
YouSerdes by Brite Semiconductor is a versatile multi-rate serializer/deserializer solution, capable of handling data transfer speeds from 2.5Gbps to 32Gbps. It is known for its superior performance, compact area usage, and power efficiency among its peers. The IP is designed to accommodate a wide array of interfaces, including but not limited to PCIe Gen 4.0/3.0/2.0/1.0, USB 3.1/3.0, and various SATA and XAUI implementations. Its architecture supports dynamic reconfiguration, allowing flexible channel arrangements and optimal resource utilization. The core design of YouSerdes optimizes the use of high-performance physical layers to ensure reliable data throughput across different applications. The solution features internal clock generation that eliminates the need for additional components, simplifying design efforts and reducing associated costs. Moreover, the architecture supports diverse protocols while maintaining compliance with industry standards, ensuring broad applicability. Designed for robust applications, YouSerdes is suitable for implementations in data centers, enterprise networks, and high-speed computing environments where efficiency and performance cannot be compromised. Its ability to seamlessly interface with multiple protocols in a single design makes it an attractive choice for multi-functional devices requiring adaptive data processing capabilities.
InnoSilicon's 56G SerDes Solution provides a high-speed interface offering breathtaking transmission rates of up to 56Gbps per channel. Supporting both PAM-4 and NRZ modulation schemes, it adapts easily to various high-speed protocols to serve diverse applications like data center network systems and telecom infrastructure. This IP reinforces robust signal integrity and low power consumption, making it suitable for advanced ESD and BIST functionalities. Its flexible architecture meets modern network demands, ensuring future-proof customization opportunities.
The ARINC 818 Direct Memory Access (DMA) Core delivers a complete hardware solution tailored for the efficient handling and transmission of ARINC 818 protocol data. It is specifically optimized for embedded applications, focusing on offloading formatting, timing, and buffer management. Engineered for speed and efficiency, this core simplifies the demanding task of managing high-rate data transmission by handling requests directly at the memory interface level. This uniqueness allows embedded systems to perform seamless data handling, thus enhancing overall system performance without the additional software overhead. In environments demanding precision and reliability, the ARINC 818 DMA Core stands out. Its ability to manage high data rates and reduce processing latency significantly enhances the overall throughput. This core is vital for improving the operability of sophisticated aerospace systems by ensuring data transactions are carried out smoothly and effectively.
The BlueLynx Chiplet Interconnect facilitates seamless communication between chiplets, vital for modern semiconductor designs that emphasize modularity and efficiency. This technology supports both physical and link layer interfaces, adhering to the Universal Chiplet Interconnect Express (UCIe) and Open Compute Project (OCP) Bunch of Wires (BoW) standards. BlueLynx ensures high-speed data transfer, offering customizable options to tailor designs for specific workloads and application needs. Optimized for AI, high-performance computing, and mobile markets, BlueLynx's die-to-die adaptability provides system architects with the leeway to integrate a variety of packaging types and process nodes, including 2D, advanced 2.5D, and innovative 3D packaging options. The solution is recognized for delivering a balance of bandwidth, energy efficiency, and latency, ensuring robust system performance while minimizing power consumption. This IP has been silicon-proven across multiple process nodes, including advanced technologies like 3nm, 4nm, and 5nm, and is supported by major semiconductor foundries. It offers valuable features such as low latency, improved PPA (Power, Performance, Area), and industry-standard compliance, positioning it as a reliable and high-performing interconnect solution within the semiconductor industry.
The MIPI C-PHY interface is designed to enhance bandwidth efficiency for the MIPI CSI-2 protocol, providing a data transfer rate of 5.7Gbps per lane. This interface is pivotal for applications demanding higher throughput without the need to increase signaling clocks. By improving data transmission efficiency, it serves critical needs in areas like mobile and augmented reality devices, where effective data handling is crucial to performance.
The Universal Chiplet Interconnect Express (UCIe) by Extoll is a cutting-edge technology designed to meet the increasing demand for seamless integration of chiplets within a system. UCIe offers a highly efficient interconnect framework that underpins the foundational architecture of heterogeneous systems, enabling enhanced interoperability and performance across various chip components. UCIe distinguishes itself by offering an ultra-low power profile, making it a preferred option for power-sensitive applications. Its design focuses on facilitating high bandwidth data transfer, essential for modern computing environments that require the handling of vast amounts of data with speed and precision. Furthermore, UCIe supports a diverse range of process nodes, ensuring it integrates well with existing and emerging technologies. This innovation plays a pivotal role in accelerating the transition to advanced chiplet-based architectures, enabling developers to create systems that are both scalable and efficient. By providing a robust interconnect solution, UCIe helps reduce overall system complexity, lowers development costs, and improves design flexibility — making it an indispensable tool for forward-thinking semiconductor designs.
Photowave represents a cutting-edge optical communications solution tailored for AI-driven memory applications in modern data centers. This hardware leverages photonics to offer substantial improvements in both latency and energy efficiency, supporting disaggregated memory configurations through PCIe 5.0/6.0 and CXL 2.0/3.0 interfaces. This advancement enables data center managers to efficiently scale resources, either within a single rack or across multiple servers, providing flexible and scalable data handling capabilities. With its focus on maximizing the advantages of light transmission, Photowave is set to redefine the boundaries of communication speed and energy utilization in high-performance computing environments.
The ePHY-5607 by eTopus is a versatile SerDes component operating at data rates between 1 to 56 Gbps, optimized for power, performance, and area (PPA) in a 7nm process environment. These features make it exceptionally suitable for modern data centers and AI applications, where space and energy efficiency are paramount. This component boasts superior BER and rapid Clock Data Recovery (CDR), ideal for high-speed optical and electrical interfaces. Its robust architecture is designed to minimize temperature-induced performance variations, which is crucial in maintaining consistent performance in data-dense environments. The ePHY-5607 enables scalable insertion loss, ensuring it can accommodate varying signal degradation scenarios in infrastructure deployments. Applications for the ePHY-5607 span enterprise networking and high-performance computing, addressing the critical needs for reduced latency and improved signal integrity.
InnoSilicon's UCIe Chiplet Interconnect offers a state-of-the-art solution for high-speed chiplet data transfer, optimizing latency and power efficiency. Utilizing advanced connection technology, these chiplets enable massive energy-efficient data operations simulating single-board performance across multiple chips seamlessly. The interconnect allows for frictionless communications between smaller package dies, facilitated by InnoSilicon's proprietary chiplet IP. Ideal for data-heavy sectors such as high-performance computing, 5G, and AI, users benefit from agile and cost-saving scalability.
This high-speed interface product is designed to accommodate data rates up to 12.5Gbps, providing exceptional performance for connecting digital-to-analog converters, among other uses. It supports the JESD204B standard for serial data interconnect, ensuring reliable data transfer with features including deterministic latency support and comprehensive SYSREF functionality. The design incorporates independent transmitting and receiving blocks capable of handling complex data flows, such as 8b/10b encoding and scrambling. Engineered for versatility, the IP core allows for flexible data packet and lane width configurations. This adaptability makes it suitable for a wide range of applications in radio frequency (RF) communications and high-speed data acquisition systems. Furthermore, the product's support for various foundry process nodes, including 65nm, 55nm, 40nm, and 28nm, enhances its usability across different manufacturing environments. These technical specifications make it an essential component for developers seeking efficient interconnect solutions in advanced electronics and communications systems.
Credo's SerDes PHY offerings are designed to support custom ASICs with seamless integration capabilities. By utilizing Credo's advanced SerDes technology, customers can achieve standout performance in their next-generation ASICs. The integration of these PHYs allows for high-speed data transfer, making them essential for applications requiring reliable and efficient communication channels. Featuring a unique mixed-signal DSP architecture, these SerDes PHYs provide a balanced approach to performance and manufacturing process cost-risk management, ensuring a high return on investment. The distinctive patented architecture allows these SerDes to excel in various fabrication processes, delivering cutting-edge performance while maintaining power efficiency. This solution is particularly tailored for integration into Multichip Module Systems on Chip (MCM SoCs) and 2.5D designs, enhancing the capabilities of comprehensive system solutions. SerDes PHYs are indispensable for achieving long-reach connectivity, meeting the requirements of diverse data-intensive applications such as high-performance computing and AI-driven systems. Integration simplicity and scalability are key hallmarks of Credo's SerDes technology, supporting numerous lanes without compromising on performance. This flexibility is conducive to the rapid development of bespoke solutions catered to specific customer needs, offering significant advantages in terms of project adaptability and future-proofing capabilities. By deploying Credo’s SerDes IP, businesses benefit from reduced design complexity and the ability to push system performance boundaries without excessive power consumption.
The Interconnect Generator developed by Dyumnin Semiconductors is designed to construct protocol-agnostic interconnects capable of supporting AXI and OCP master/slave configurations. This generator allows for flexibility in the creation of interconnects that can be simple, pipelined, or crossbar. Additionally, it manages varying protocol behaviors, ranging from atomic transactions to split transactions with independent address and data phases. The built-in reorder buffer provides configurable depth, allowing for multiple outstanding requests while ensuring data is delivered in sequence.
The CXL 3.0 solution from Rapid Silicon is an advanced Controller IP designed to enhance your FPGA design with superior performance and flexibility. This IP is compliant with CXL specifications up to version 3.0, along with support for earlier versions 2.0, 1.1, and 1.0. It offers seamless integration capabilities with PCIe, standing up to PCIe 6.0 and ensuring backward compatibility. The architecture of the CXL Controller IP is highly configurable, providing adaptability for specific application requirements, including lane configurations, datapath widths, and efficiency in power management. One of the standout features of the CXL 3.0 IP is its support for advanced functionalities such as lane bonding, multicast, and robust error correction mechanisms. These features ensure the IP delivers reliable and efficient performance in diverse environments. Ideal for critical data-intensive tasks, the IP is suited for telecommunications, industrial applications, and more, where data throughput and protocol bridging are crucial. With its focus on delivering unmatched speed, efficiency, and scalability, the CXL 3.0 IP from Rapid Silicon is positioned as a key component for enabling sophisticated FPGA designs tailored to meet modern technology demands. Its architecture is crafted to support the burgeoning needs of applications that require high degrees of data handling and processing accuracy, making it a preferred choice in the semiconductor industry.
VITA 17.3 Serial FPDP Gen3 solution is engineered for next-generation serial communication systems, supporting intensive data transfer operations across numerous applications. Known for its stability and excellent throughput capabilities, this IP empowers efficient and robust operations even at the extremes of performance envelopes. StreamDSP's design ensures integration simplicity and operational reliability within various FPGA environments. The IP provides configurable options for data path flow, alignment precision, and ensures resilience with its comprehensive error detection and correction functionality. This adaptability makes it an ideal choice for advanced applications that demand spotlight focus on data accuracy and speed. As contemporary data-driven processes expand, the need for such adaptable, high-speed data solutions becomes paramount, and the VITA 17.3 Serial FPDP Gen3 solution meets these needs admirably.
The Time Sensitive Network IP Core is an advanced solution explicitly crafted to support time-critical network environments. It offers remarkable precision and fault tolerance, making it ideal for applications where timing accuracy is paramount. Capable of scaling from 1Gbps to 10Gbps, this core is engineered to provide robust anti-masquerading and babbling protection functions. Integrated with the widely adopted AXI standard, the network core facilitates easy interfacing between hardware and software, which is essential for developers looking to integrate it within diverse systems efficiently. This ease of integration is coupled with its fault tolerance capabilities, ensuring network reliability in complex deployments. Applications that significantly benefit from this IP core include industrial automation, telecommunications, and any domain requiring synchronized processing and high-reliability data exchange. The Time Sensitive Network IP Core is invaluable in enhancing system efficiencies and ensuring data integrity across demanding operational environments.
The VITA 17.1 Serial FPDP Solution from StreamDSP is expertly crafted for high-speed serial data transmission, which is pivotal for real-time applications demanding reliable and continuous data handling. This IP solution supports seamless integration with popular FPGA platforms, enhancing performance without sacrificing flexibility. Whether for streaming, high-throughput scientific computations, or any number of real-time processing requirements, this IP core ensures low-latency and high-bandwidth data transfers. Besides, it offers advanced data handling features, including programmable data alignment, flexible data path configurations, and comprehensive error detection capabilities, thereby optimizing the core for diverse high-speed data tasks. With its versatile configuration options, the VITA 17.1 Serial FPDP Solution simplifies the manageability of complex system environments, providing a robust foundation for any high-performance digital system.
Zetti is recognized as the pioneering small-scale PCIe Gen 5 transport layer switch, specially designed to cater to the growing needs of high-performance CPU and GPU environments. Its backward compatibility with previous PCIe generations ensures versatility for various devices and platforms, making it well-suited for industries ranging from IoT to telecoms. Supporting multiple peripherals and equipped with six downstream ports, Zetti's architecture allows for concurrent operation of these ports at varied speeds, thereby optimizing performance for differing workloads. The switch's unique premium features, such as Hot Plug and Peer to Peer communication, provide enhancements in operational efficiency and data throughput. Zetti also incorporates advanced diagnostic features, essential for maintaining robust performance in field operations. Its integration within systems is seamless, thanks to its sophisticated design that flags a new standard in switch technology, facilitating superior functionality in multi-peripheral devices like industrial PCs and smart home technology.
The Chiplet Interface solutions provided by Neuron IP include cutting-edge PHY & D2D Adapter IP for chiplet products. These solutions are built around the latest UCIe v1.1 specification and are designed to support a wide range of application verticals. They are well-known for their unparalleled PPA-differentiated architecture, which includes 32Gbps UCIe-Advanced and Standard cores. These interfaces are set to revolutionize the way microprocessors work in ultra-low latency environments, enhancing both performance and efficiency.
The Prodigy FPGA-Based Emulator by Tachyum serves as a comprehensive evaluation platform for developers looking to assess, test, and enhance software applications on the Prodigy processor architecture. As an emulation platform, it offers detailed insights into performance metrics and serves as a critical tool for debugging and compatibility verification. Capable of emulating eight processor cores on a single FPGA board, this system includes vector and matrix processing units for robust data handling, further illustrating Tachyum's focus on creating versatile and effective solutions for data-heavy applications. The FPGA platform, structured with multiple FPGA and I/O boards connected via cables, provides a realistic simulation of actual processor environments, offering precise performance measurement capabilities. Developer tools and libraries are also integrated into the emulator, facilitating application development across various programming languages and environments. It is particularly beneficial for those transitioning to the Prodigy architecture, as it provides pre-built systems that support a range of key applications and utilities. This makes it a preferred platform for real-world workload simulation and helps in ensuring software compatibility across diverse operational environments.
The Evo Gen 5 PCIe Card is meticulously designed for high-performance AI inferencing tasks, providing an ideal solution for enterprise-grade applications. This PCIe card leverages advanced technology to deliver outstanding efficiency in large-scale AI computations, particularly focusing on supporting LLMs (Large Language Models). By optimizing the distribution of processing loads, it significantly enhances the performance of resource-intensive AI models, ensuring seamless and rapid computations required in modern-day AI workloads. An integral feature of the Evo Gen 5 is its capability to offload the majority of processing demands from CPUs, enabling systems to achieve maximal output without overburdening core computing resources. This card not only improves throughput but also maintains energy efficiency, making it an attractive choice for data centers seeking to upgrade their infrastructure for AI tasks. Moreover, its seamless integration with existing systems ensures that businesses can easily adopt this cutting-edge technology without extensive modifications. The Evo Gen 5 PCIe Card stands out with its robust reliability and scalable AI solutions tailored to meet diverse industrial needs, driving innovation in AI deployment across a myriad of sectors.
FireCore PHY & Link Layer Solutions offer a versatile platform that combines the benefits of IEEE-1394b-2008 and AS5643 standards for advanced data communication. These solutions are tailored to suit the needs of industries requiring reliable data capture, verification, and analysis, particularly within aerospace and imaging sectors. The FireCore family embodies adaptability, with customizable options for the number of PHY ports and various data streaming protocols. One of FireCore's standout features is its support for high transmission speeds, reaching up to S3200, catering to environments where speed and precision are paramount. Its multi-protocol support includes built-in AS5643 functions, making them well-suited for high-stakes applications such as avionics systems where accuracy and reliability can't be compromised. FireCore Solutions are distinguished by their capability to offload processing from the host CPU, thereby streamlining operational load and enhancing system efficiency. With robust error injection and Bit Error Rate Testing features, they ensure comprehensive diagnostics and high system integrity, setting new benchmarks for PHY and Link Layer IP core solutions.
The Regli PCIe Retimer from Kandou is crafted to deliver unparalleled signal integrity and minimal latency specifically for PCIe 5.0 and CXL 2.0 protocols. It stands out with an error rate as low as 1E-12, ensuring razor-sharp signal accuracy across your PCIe network. Operating at sub-10 nanoseconds latency, Regli is among the fastest retimers available, facilitating rapid data transmission with high reliability. Security is a top priority with Regli, which incorporates measures that solidify its defenses against potential vulnerabilities. It also supports bifurcation, simplifying system design and offering significant flexibility in various implementations. This makes it a preferred choice for designers who demand both performance and adaptability within network components. Regli is not just about speed; it’s a comprehensive solution that enhances functionality across various applications, including PCIe and CXL storage, 5G infrastructure, and hyperscale data centers. Its advanced on-chip diagnostics further assist in maintaining optimal system health, making it a reliable asset in high-speed communication setups.
AresCORE UCIe Die-to-Die PHY is engineered to provide ultra-low power, high-bandwidth connections between dies within a single package. It supports data rates of up to 64 Gbps per lane and is essential for applications demanding high throughput and minimal latency like AI and data centers. The IP efficiently supports various advanced packaging technologies, ensuring reduced IO complexity and increased power savings, facilitating robust connectivity within multi-die systems.
Designed for high-performance and efficiency, the High-speed LVDS Solutions provide a robust differential signaling interface capable of operating frequencies up to 1 GHz. The module includes driver and receiver components optimized for low power consumption and operates from a 1.8V I/O power supply while maintaining core supply voltages within the 1.0V to 1.1V range. Featuring integrated low power consumption and a versatile common mode range, these solutions are perfectly designed for environments requiring reliable and high-speed data transmission. The LVDS driver is capable of handling 50Ω and 100Ω differential termination, supporting a wide range of data throughput requirements, which makes it suitable for modern high-speed circuit designs. Aragio Solutions ensures that these LVDS solutions are compliant with the IEEE standards, providing a reliable framework for both input and output components. Silicon validation ensures that the implementations are production-ready and can be easily integrated into a variety of applications demanding high-speed data transfer coupled with low energy consumption.
The CXL 3.1 Controller by Panmnesia exemplifies state-of-the-art advancements in data management and connectivity, designed specifically to address the demands of modern expansive memory systems. This controller is engineered to deliver minimal latency with unmatched operational efficiency, ensuring rapid communication between CPUs, memory expanders, and accelerators, while significantly cutting down on processing delays. Embedded with Panmnesia’s proprietary low-latency CXL IP, the controller supports comprehensive communication functions that facilitate streamlined memory operations across disaggregated resources. By automating key memory management tasks, the controller minimizes manual overhead, allowing for flawless integration with existing system architectures. This results in reduced lag and enhanced throughput, making it an ideal fit for AI applications and high-performance computing where speed is paramount. The CXL 3.1 Controller is praised for its double-digit nanosecond latency — a milestone setting new industry standards for data flow efficiency. Its architecture seamlessly connects multiple system devices, optimizing both resource and power usage, thereby reducing operational expenses. Through Panmnesia’s intent to place top-tier CXL solutions at the forefront of technology, this controller demonstrates exceptional performance gains for organizations aiming to scale their data operations efficiently.
Actt’s SerDes IP offers high-speed interface capabilities, supporting multiple protocols such as USB, PCIe, and SATA. This solution is positioned to facilitate robust data communication across various applications where high performance and reliable data transfer are critical. The SerDes technology meets the stringent requirements of these data protocols, ensuring seamless integration with advanced system architectures.
The GammaCORE UCIe Die-to-Die Controller IP builds on the UCIe 2.0 specification to facilitate seamless multi-die communication in systems. Featuring a customizable streaming protocol layer, it interfaces effectively with Alphawave's AresCORE UCIe PHY, forming a complete, robust chiplet ecosystem solution that supports diverse SOC interfaces.
The Die-to-Die IP represents an innovative leap in the integration of chips within complex electronic systems. This technology is critical for facilitating data communication between heterogeneous dies within a single package, enhancing both system performance and functionality. By employing advanced 2.5D and 3D packaging technologies, the Die-to-Die IP allows for closer placement of dies, reducing latency and power consumption which are crucial factors for high-performance computing environments. This IP is ideal for AI and HPC applications that demand rapid data transfers and robust computational capabilities. The Die-to-Die solution uses silicon interposer technology in 2.5D packaging to ensure efficient signal routing between dies. In contrast, 3D integration employs through-silicon vias (TSVs) to vertically stack chips, further reducing signal path lengths and thereby minimizing latency. A significant advantage of GUC's Die-to-Die IP is its adaptability to various process nodes and packaging solutions, making it suitable for a wide range of design architectures. This adaptability ensures that as technology scales, the IP continues to provide efficiency gains, thereby prolonging product lifecycle and enhancing return on investment for high-scale data architecture deployments.
The logiHSSL Slave HSSL Controller is tailored for applications requiring high-speed serial communication, providing support for the Infineon High Speed Serial Link (HSSL). It integrates the security and functional safety offered by Infineon's AURIX microcontrollers with the wide-ranging potential of AMD's programmable devices.<br><br>This controller is instrumental for systems where data integrity and security are paramount, typically found in automotive, industrial, and aerospace sectors. It facilitates high-speed data transfers, ensuring reliable communication across different hardware components.<br><br>By leveraging its capabilities, engineers can manage and implement complex communication protocols within their designs, enhancing system performance and ensuring robust operational integrity. The logiHSSL proves essential for applications where high-speed and secure data transmission are required.
Sofics has verified its TakeCharge ESD protection clamps on technology nodes between 0.25um CMOS down to 3nm across various fabs and foundries. The ESD clamps are silicon and product proven in more than 5000 mass produced IC-products. The cells provide competitive advantage through improved yield, reduced silicon footprint and enable low-leakage, high-speed or high voltage tolerant interfaces. The ESD protection described in this document can be used for 1.6V chiplet (die-2-die) interface pads in the GF 22nm FDX technology. The ESD robustness is strongly reduced in order to reduce the size and capacitance.
Broadcom's Automotive Multigigabit Ethernet Switch, known for its robust multilayer security features, is designed to revolutionize in-car networking. Integrating cutting-edge security technologies such as MACsec, this Ethernet switch enhances automotive network reliability by encrypting data transmitted over Ethernet lines, offering robust protection against cyber threats. The switch boasts a sophisticated array of multigigabit connectivity options, enabling it to support the latest automotive Ethernet standards. This functionality ensures seamless data exchanges between various electronic systems within a vehicle, facilitating advanced automotive technologies such as ADAS (Advanced Driver Assistance Systems) and autonomous driving platforms. Built to meet AEC-Q100 standards, it is ideally suited for automotive environments, where reliability and performance are non-negotiable. The integration of ARM Cortex M7 programmability allows further customization and capability expansion, making it a vital component in the burgeoning field of connected vehicle technology.
The USB 4.0 Device Controller IP Core is crafted for devices requiring high-speed USB connections. Designed to offer enhanced performance with backward compatibility, it ensures power and data transfer at up to 40Gbps. It is verified using FPGA prototypes with standard PHYs, providing reliability across various designs. With support for both USB4 Gen 2x2 (20 Gbps) and Gen 3x2 (40 Gbps) links, it features options for PCIe and DisplayPort adaptation, broadening its application scope. The device includes advanced energy-efficient configurations to minimize consumption and optimize power use. Ideal for mass storage, consumer electronics, and automotive applications, it provides the infrastructure for developing high-performance USB solutions that demand efficiency and backward compatibility with previous USB standards.
The 32G UCIe PHY from Global UniChip marks a significant departure in chip-to-chip connectivity, supporting the Universal Chiplet Interconnect Express (UCIe) standard, which propels data transfer rates to new heights. With a data rate of 32 Gbps per lane, this PHY offers unmatched speed and efficiency, ideal for high-demand applications in AI and high-performance computing environments. This IP is built on TSMC's N3P process and CoWoS packaging technology, enabling robust and reliable operation with high bandwidth density, indispensable for executing large-scale network applications efficiently. What sets this PHY apart is its ability to deliver 10 Tbps per 1 mm of die edge, ensuring that data throughput can meet the intensive demands of modern computing applications. It comes with features like Dynamic Voltage and Frequency Scaling (DVFS), which allows for real-time adjustments to maintain optimal performance and power usage. Its proactive monitoring features are enabled by proteanTecs, ensuring signal integrity is maintained without operational interruptions - a critical need for maintaining system stability and reliability. Integrating this UCIe PHY facilitates a smooth transition from traditional single-chip networks-on-chip (NoC) architecture to more scalable, chiplet-based solutions. This shift unlocks new possibilities in modular processor designs, pushing performance boundaries while ensuring minimal power consumption. This architecture not only meets current computational requirements but also anticipates future scalability needs, positioning it as a cornerstone for futuristic data processing solutions.
CoaXPress (CXP) is a prominent global standard for high-speed imaging in professional and industrial applications, including machine vision, medical imaging, life sciences, broadcasting, and defense. It combines the simplicity of coaxial cables with high-speed serial data transmission technology, offering a beneficial solution for imaging and data transmission requirements. EASii IC has developed CoaXPress IP for both Device and Host applications to meet internal camera and recorder design requirements. The IP is compliant with CoaXPress versions 1.1.1 and 2.0, enabling up to 256 video streams from multiple cameras through 1 to 8 coaxial cable connections. This setup allows a data rate ranging from 1.25 Gbps to 12.5 Gbps per cable, with total transfer rates reaching up to 100 Gbps. Dynamic link reconfiguration and hardware-based video-stream management are key features, supporting enhanced error detection and recovery. EASii IC offers a comprehensive CoaXPress design environment, including FPGA CoaXPress Device and Host IP cores, with associated hardware like FMC-CXP boards that stack to provide increased bandwidth capabilities.
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