The RV32EC_P2 is a 2-stage pipeline RISC-V processor core engineered to serve small, low-power embedded applications, focusing on executing secure and trusted firmware. It adheres strictly to the RISC-V RV32E base instruction set, with compliance to the RISC-V User-Level ISA V2.2, and supports an optional 'M' standard extension for arithmetic operations like integer multiplication and division. Its architecture includes a straightforward machine-mode with direct physical memory addressing, supporting 20 extended interrupts with vectored handling for rapid response.
Designed for both ASIC and FPGA design processes, the processor can integrate application-specific instructions pertinent to DSP operations, featuring tightly-coupled memory interfaces for ROM and SRAM operations. The processor is complemented by machine-mode timers compatible with AHB and APB interfaces, enhancing its application breadth across differing performance environments. Furthermore, it employs a power-conserving clock gating mechanism during idle states to minimize power consumption.
This processor core interacts seamlessly with memory blocks for code and I/O interfaces using AHB-Lite and APB interfaces. Its architecture ensures fast cycle instruction execution, with most completing in a single cycle, making it a suitable candidate for efficiency-driven applications. It is part of a broader suite equipped with development tools, encompassing a GNU tool chain and Eclipse IDE for firmware development, supported by ASTC's VLAB system-level design.
