Riviera-PRO is a verification and simulation tool designed to meet the demands of cutting-edge FPGA and SoC development. It provides an environment where engineers can maximize testbench productivity through advanced automation and reusability features. Riviera-PRO leverages a high-performance simulation engine, combining it with powerful debugging capabilities to ensure seamless design verification.
Among its most notable features is the ability to support metric-driven verification methodologies, enabling thorough checks and balances throughout the project lifecycle. The tool also integrates seamlessly with Universal Verification Methodology (UVM), Open Source VHDL Verification Methodology (OSVVM), and more, providing a versatile environment for verifying a wide range of engineering designs.
For engineers working in industries with rigorous standards, such as aerospace or automotive sectors, Riviera-PRO's scalability and efficiency in handling simulation acceleration and emulation capabilities make it an invaluable addition to the engineering toolkit, ensuring projects are delivered both on time and specification.
