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All IPs > Analog & Mixed Signal > Clock Synthesizer > pPLL05 Family

pPLL05 Family

From Perceptia Devies Australia

Description

Paired for low power and low voltage applications, the pPLL05 Family excels in embedding clocks for IoT and digital systems. Operating efficiently below standard core voltages, this family offers fractional-N PLL capability for systems running at frequencies up to 1GHz, revolutionizing power efficiency in design.

Utilizing the second-generation all-digital PLL architecture, the pPLL05 Family sustains a compact size and maintains excellent functional performance across processes. It offers fine-grained control over input/output frequencies, facilitating ease in porting across different technologies and foundries.

Aimed at enhancing integration in digital environments, the pPLL05 features high testability and offers several deliverables including detailed behavioral models and integration guides. This design guarantees consistent results and supports high precision with use across multiple nodes and foundries.

Features
  • Low power consumption
  • Compact footprint
  • High flexibility in frequency selection
Foundries & Process Nodes
Foundry Process Nodes
GLOBALFOUNDARIES 22nm FD-SOI
28nm
Samsung 8nm LPP
TSMC 10nm
UMC 1000nm
Tech Specs
Class Value
Categories Analog & Mixed Signal > Clock Synthesizer
Analog & Mixed Signal > PLL
Interface Controller & PHY > AMBA AHB / APB/ AXI
Power Consumption <1.0mW
Die Area <0.01 sq mm
Maximum Frequency 1GHz
Power (W) <1W
Availability All Countries & Regions
Applications
  • IoT
  • Embedded systems
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